1 // SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2020, The Linux Foundation. All rights reserved.
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/qcom,gcc-msm8974.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/power/qcom-rpmpd.h>
12 #include <dt-bindings/reset/qcom,gcc-msm8974.h>
17 interrupt-parent = <&intc>;
22 device_type = "memory";
28 compatible = "fixed-clock";
30 clock-frequency = <19200000>;
33 sleep_clk: sleep_clk {
34 compatible = "fixed-clock";
36 clock-frequency = <32768>;
42 compatible = "qcom,scm-msm8226", "qcom,scm";
43 clocks = <&gcc GCC_CE1_CLK>, <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>;
44 clock-names = "core", "bus", "iface";
53 smem_region: smem@3000000 {
54 reg = <0x3000000 0x100000>;
58 adsp_region: adsp@dc00000 {
59 reg = <0x0dc00000 0x1900000>;
65 compatible = "qcom,smd";
68 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
69 qcom,ipc = <&apcs 8 0>;
72 rpm_requests: rpm-requests {
73 compatible = "qcom,rpm-msm8226";
74 qcom,smd-channels = "rpm_requests";
76 rpmpd: power-controller {
77 compatible = "qcom,msm8226-rpmpd";
78 #power-domain-cells = <1>;
79 operating-points-v2 = <&rpmpd_opp_table>;
81 rpmpd_opp_table: opp-table {
82 compatible = "operating-points-v2";
87 rpmpd_opp_svs_krait: opp2 {
90 rpmpd_opp_svs_soc: opp3 {
96 rpmpd_opp_turbo: opp5 {
99 rpmpd_opp_super_turbo: opp6 {
109 compatible = "qcom,smem";
111 memory-region = <&smem_region>;
112 qcom,rpm-msg-ram = <&rpm_msg_ram>;
114 hwlocks = <&tcsr_mutex 3>;
118 compatible = "qcom,smp2p";
119 qcom,smem = <443>, <429>;
121 interrupt-parent = <&intc>;
122 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
124 qcom,ipc = <&apcs 8 10>;
126 qcom,local-pid = <0>;
127 qcom,remote-pid = <2>;
129 adsp_smp2p_out: master-kernel {
130 qcom,entry-name = "master-kernel";
131 #qcom,smem-state-cells = <1>;
134 adsp_smp2p_in: slave-kernel {
135 qcom,entry-name = "slave-kernel";
137 interrupt-controller;
138 #interrupt-cells = <2>;
143 compatible = "simple-bus";
144 #address-cells = <1>;
148 intc: interrupt-controller@f9000000 {
149 compatible = "qcom,msm-qgic2";
150 reg = <0xf9000000 0x1000>,
152 interrupt-controller;
153 #interrupt-cells = <3>;
156 apcs: syscon@f9011000 {
157 compatible = "syscon";
158 reg = <0xf9011000 0x1000>;
161 sdhc_1: mmc@f9824900 {
162 compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4";
163 reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
164 reg-names = "hc", "core";
165 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
166 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
167 interrupt-names = "hc_irq", "pwr_irq";
168 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
169 <&gcc GCC_SDCC1_APPS_CLK>,
171 clock-names = "iface", "core", "xo";
172 pinctrl-names = "default";
173 pinctrl-0 = <&sdhc1_default_state>;
177 sdhc_2: mmc@f98a4900 {
178 compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4";
179 reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
180 reg-names = "hc", "core";
181 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
182 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
183 interrupt-names = "hc_irq", "pwr_irq";
184 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
185 <&gcc GCC_SDCC2_APPS_CLK>,
187 clock-names = "iface", "core", "xo";
188 pinctrl-names = "default";
189 pinctrl-0 = <&sdhc2_default_state>;
193 sdhc_3: mmc@f9864900 {
194 compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4";
195 reg = <0xf9864900 0x11c>, <0xf9864000 0x800>;
196 reg-names = "hc", "core";
197 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
198 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
199 interrupt-names = "hc_irq", "pwr_irq";
200 clocks = <&gcc GCC_SDCC3_AHB_CLK>,
201 <&gcc GCC_SDCC3_APPS_CLK>,
203 clock-names = "iface", "core", "xo";
204 pinctrl-names = "default";
205 pinctrl-0 = <&sdhc3_default_state>;
209 blsp1_uart1: serial@f991d000 {
210 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
211 reg = <0xf991d000 0x1000>;
212 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
213 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
214 clock-names = "core", "iface";
218 blsp1_uart3: serial@f991f000 {
219 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
220 reg = <0xf991f000 0x1000>;
221 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
222 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
223 clock-names = "core", "iface";
227 blsp1_uart4: serial@f9920000 {
228 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
229 reg = <0xf9920000 0x1000>;
230 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
231 clocks = <&gcc GCC_BLSP1_UART4_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
232 clock-names = "core", "iface";
236 blsp1_i2c1: i2c@f9923000 {
238 compatible = "qcom,i2c-qup-v2.1.1";
239 reg = <0xf9923000 0x1000>;
240 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
241 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
242 clock-names = "core", "iface";
243 pinctrl-names = "default";
244 pinctrl-0 = <&blsp1_i2c1_pins>;
245 #address-cells = <1>;
249 blsp1_i2c2: i2c@f9924000 {
251 compatible = "qcom,i2c-qup-v2.1.1";
252 reg = <0xf9924000 0x1000>;
253 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
254 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
255 clock-names = "core", "iface";
256 pinctrl-names = "default";
257 pinctrl-0 = <&blsp1_i2c2_pins>;
258 #address-cells = <1>;
262 blsp1_i2c3: i2c@f9925000 {
264 compatible = "qcom,i2c-qup-v2.1.1";
265 reg = <0xf9925000 0x1000>;
266 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
267 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
268 clock-names = "core", "iface";
269 pinctrl-names = "default";
270 pinctrl-0 = <&blsp1_i2c3_pins>;
271 #address-cells = <1>;
275 blsp1_i2c4: i2c@f9926000 {
277 compatible = "qcom,i2c-qup-v2.1.1";
278 reg = <0xf9926000 0x1000>;
279 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
280 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
281 clock-names = "core", "iface";
282 pinctrl-names = "default";
283 pinctrl-0 = <&blsp1_i2c4_pins>;
284 #address-cells = <1>;
288 blsp1_i2c5: i2c@f9927000 {
290 compatible = "qcom,i2c-qup-v2.1.1";
291 reg = <0xf9927000 0x1000>;
292 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
293 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
294 clock-names = "core", "iface";
295 pinctrl-names = "default";
296 pinctrl-0 = <&blsp1_i2c5_pins>;
297 #address-cells = <1>;
302 compatible = "qcom,ci-hdrc";
303 reg = <0xf9a55000 0x200>,
305 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
306 clocks = <&gcc GCC_USB_HS_AHB_CLK>,
307 <&gcc GCC_USB_HS_SYSTEM_CLK>;
308 clock-names = "iface", "core";
309 assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
310 assigned-clock-rates = <75000000>;
311 resets = <&gcc GCC_USB_HS_BCR>;
312 reset-names = "core";
318 ahb-burst-config = <0>;
319 phy-names = "usb-phy";
320 phys = <&usb_hs_phy>;
326 compatible = "qcom,usb-hs-phy-msm8226",
329 clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
330 clock-names = "ref", "sleep";
331 resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>;
332 reset-names = "phy", "por";
333 qcom,init-seq = /bits/ 8 <0x0 0x44
334 0x1 0x68 0x2 0x24 0x3 0x13>;
339 gcc: clock-controller@fc400000 {
340 compatible = "qcom,gcc-msm8226";
341 reg = <0xfc400000 0x4000>;
344 #power-domain-cells = <1>;
347 tlmm: pinctrl@fd510000 {
348 compatible = "qcom,msm8226-pinctrl";
349 reg = <0xfd510000 0x4000>;
352 gpio-ranges = <&tlmm 0 0 117>;
353 interrupt-controller;
354 #interrupt-cells = <2>;
355 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
357 blsp1_i2c1_pins: blsp1-i2c1 {
358 pins = "gpio2", "gpio3";
359 function = "blsp_i2c1";
360 drive-strength = <2>;
364 blsp1_i2c2_pins: blsp1-i2c2 {
365 pins = "gpio6", "gpio7";
366 function = "blsp_i2c2";
367 drive-strength = <2>;
371 blsp1_i2c3_pins: blsp1-i2c3 {
372 pins = "gpio10", "gpio11";
373 function = "blsp_i2c3";
374 drive-strength = <2>;
378 blsp1_i2c4_pins: blsp1-i2c4 {
379 pins = "gpio14", "gpio15";
380 function = "blsp_i2c4";
381 drive-strength = <2>;
385 blsp1_i2c5_pins: blsp1-i2c5 {
386 pins = "gpio18", "gpio19";
387 function = "blsp_i2c5";
388 drive-strength = <2>;
392 sdhc1_default_state: sdhc1-default-state {
395 drive-strength = <10>;
400 pins = "sdc1_cmd", "sdc1_data";
401 drive-strength = <10>;
406 sdhc2_default_state: sdhc2-default-state {
409 drive-strength = <10>;
414 pins = "sdc2_cmd", "sdc2_data";
415 drive-strength = <10>;
420 sdhc3_default_state: sdhc3-default-state {
424 drive-strength = <8>;
431 drive-strength = <8>;
436 pins = "gpio39", "gpio40", "gpio41", "gpio42";
438 drive-strength = <8>;
445 compatible = "qcom,pshold";
446 reg = <0xfc4ab000 0x4>;
449 spmi_bus: spmi@fc4cf000 {
450 compatible = "qcom,spmi-pmic-arb";
451 reg-names = "core", "intr", "cnfg";
452 reg = <0xfc4cf000 0x1000>,
455 interrupt-names = "periph_irq";
456 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
459 #address-cells = <2>;
461 interrupt-controller;
462 #interrupt-cells = <4>;
466 compatible = "qcom,prng";
467 reg = <0xf9bff000 0x200>;
468 clocks = <&gcc GCC_PRNG_AHB_CLK>;
469 clock-names = "core";
473 compatible = "arm,armv7-timer-mem";
474 reg = <0xf9020000 0x1000>;
475 #address-cells = <1>;
481 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
482 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
483 reg = <0xf9021000 0x1000>,
489 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
490 reg = <0xf9023000 0x1000>;
496 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
497 reg = <0xf9024000 0x1000>;
503 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
504 reg = <0xf9025000 0x1000>;
510 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
511 reg = <0xf9026000 0x1000>;
517 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
518 reg = <0xf9027000 0x1000>;
524 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
525 reg = <0xf9028000 0x1000>;
530 rpm_msg_ram: memory@fc428000 {
531 compatible = "qcom,rpm-msg-ram";
532 reg = <0xfc428000 0x4000>;
535 tcsr_mutex: hwlock@fd484000 {
536 compatible = "qcom,msm8226-tcsr-mutex", "qcom,tcsr-mutex";
537 reg = <0xfd484000 0x1000>;
541 adsp: remoteproc@fe200000 {
542 compatible = "qcom,msm8226-adsp-pil";
543 reg = <0xfe200000 0x100>;
545 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
546 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
547 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
548 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
549 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
550 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
552 power-domains = <&rpmpd MSM8226_VDDCX>;
553 power-domain-names = "cx";
555 clocks = <&xo_board>;
558 memory-region = <&adsp_region>;
560 qcom,smem-states = <&adsp_smp2p_out 0>;
561 qcom,smem-state-names = "stop";
566 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
568 qcom,ipc = <&apcs 8 8>;
577 compatible = "arm,armv7-timer";
578 interrupts = <GIC_PPI 2
579 (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>,
581 (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>,
583 (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>,
585 (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>;