arch/arm/boot/dts/qcom-msm8226.dtsi

   1 // SPDX-License-Identifier: BSD-3-Clause
   2 /*
   3  * Copyright (c) 2020, The Linux Foundation. All rights reserved.
   4  */
   5
   6 /dts-v1/;
   7
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9 #include <dt-bindings/clock/qcom,gcc-msm8974.h>
  10 #include <dt-bindings/gpio/gpio.h>
  11 #include <dt-bindings/power/qcom-rpmpd.h>
  12 #include <dt-bindings/reset/qcom,gcc-msm8974.h>
  13
  14 / {
  15         #address-cells = <1>;
  16         #size-cells = <1>;
  17         interrupt-parent = <&intc>;
  18
  19         chosen { };
  20
  21         memory@0 {
  22                 device_type = "memory";
  23                 reg = <0x0 0x0>;
  24         };
  25
  26         clocks {
  27                 xo_board: xo_board {
  28                         compatible = "fixed-clock";
  29                         #clock-cells = <0>;
  30                         clock-frequency = <19200000>;
  31                 };
  32
  33                 sleep_clk: sleep_clk {
  34                         compatible = "fixed-clock";
  35                         #clock-cells = <0>;
  36                         clock-frequency = <32768>;
  37                 };
  38         };
  39
  40         firmware {
  41                 scm {
  42                         compatible = "qcom,scm-msm8226", "qcom,scm";
  43                         clocks = <&gcc GCC_CE1_CLK>, <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>;
  44                         clock-names = "core", "bus", "iface";
  45                 };
  46         };
  47
  48         reserved-memory {
  49                 #address-cells = <1>;
  50                 #size-cells = <1>;
  51                 ranges;
  52
  53                 smem_region: smem@3000000 {
  54                         reg = <0x3000000 0x100000>;
  55                         no-map;
  56                 };
  57
  58                 adsp_region: adsp@dc00000 {
  59                         reg = <0x0dc00000 0x1900000>;
  60                         no-map;
  61                 };
  62         };
  63
  64         smd {
  65                 compatible = "qcom,smd";
  66
  67                 rpm {
  68                         interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
  69                         qcom,ipc = <&apcs 8 0>;
  70                         qcom,smd-edge = <15>;
  71
  72                         rpm_requests: rpm-requests {
  73                                 compatible = "qcom,rpm-msm8226";
  74                                 qcom,smd-channels = "rpm_requests";
  75
  76                                 rpmpd: power-controller {
  77                                         compatible = "qcom,msm8226-rpmpd";
  78                                         #power-domain-cells = <1>;
  79                                         operating-points-v2 = <&rpmpd_opp_table>;
  80
  81                                         rpmpd_opp_table: opp-table {
  82                                                 compatible = "operating-points-v2";
  83
  84                                                 rpmpd_opp_ret: opp1 {
  85                                                         opp-level = <1>;
  86                                                 };
  87                                                 rpmpd_opp_svs_krait: opp2 {
  88                                                         opp-level = <2>;
  89                                                 };
  90                                                 rpmpd_opp_svs_soc: opp3 {
  91                                                         opp-level = <3>;
  92                                                 };
  93                                                 rpmpd_opp_nom: opp4 {
  94                                                         opp-level = <4>;
  95                                                 };
  96                                                 rpmpd_opp_turbo: opp5 {
  97                                                         opp-level = <5>;
  98                                                 };
  99                                                 rpmpd_opp_super_turbo: opp6 {
 100                                                         opp-level = <6>;
 101                                                 };
 102                                         };
 103                                 };
 104                         };
 105                 };
 106         };
 107
 108         smem {
 109                 compatible = "qcom,smem";
 110
 111                 memory-region = <&smem_region>;
 112                 qcom,rpm-msg-ram = <&rpm_msg_ram>;
 113
 114                 hwlocks = <&tcsr_mutex 3>;
 115         };
 116
 117         smp2p-adsp {
 118                 compatible = "qcom,smp2p";
 119                 qcom,smem = <443>, <429>;
 120
 121                 interrupt-parent = <&intc>;
 122                 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
 123
 124                 qcom,ipc = <&apcs 8 10>;
 125
 126                 qcom,local-pid = <0>;
 127                 qcom,remote-pid = <2>;
 128
 129                 adsp_smp2p_out: master-kernel {
 130                         qcom,entry-name = "master-kernel";
 131                         #qcom,smem-state-cells = <1>;
 132                 };
 133
 134                 adsp_smp2p_in: slave-kernel {
 135                         qcom,entry-name = "slave-kernel";
 136
 137                         interrupt-controller;
 138                         #interrupt-cells = <2>;
 139                 };
 140         };
 141
 142         soc: soc {
 143                 compatible = "simple-bus";
 144                 #address-cells = <1>;
 145                 #size-cells = <1>;
 146                 ranges;
 147
 148                 intc: interrupt-controller@f9000000 {
 149                         compatible = "qcom,msm-qgic2";
 150                         reg = <0xf9000000 0x1000>,
 151                               <0xf9002000 0x1000>;
 152                         interrupt-controller;
 153                         #interrupt-cells = <3>;
 154                 };
 155
 156                 apcs: syscon@f9011000 {
 157                         compatible = "syscon";
 158                         reg = <0xf9011000 0x1000>;
 159                 };
 160
 161                 sdhc_1: mmc@f9824900 {
 162                         compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4";
 163                         reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
 164                         reg-names = "hc", "core";
 165                         interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
 166                                      <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
 167                         interrupt-names = "hc_irq", "pwr_irq";
 168                         clocks = <&gcc GCC_SDCC1_AHB_CLK>,
 169                                  <&gcc GCC_SDCC1_APPS_CLK>,
 170                                  <&xo_board>;
 171                         clock-names = "iface", "core", "xo";
 172                         pinctrl-names = "default";
 173                         pinctrl-0 = <&sdhc1_default_state>;
 174                         status = "disabled";
 175                 };
 176
 177                 sdhc_2: mmc@f98a4900 {
 178                         compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4";
 179                         reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
 180                         reg-names = "hc", "core";
 181                         interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
 182                                      <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
 183                         interrupt-names = "hc_irq", "pwr_irq";
 184                         clocks = <&gcc GCC_SDCC2_AHB_CLK>,
 185                                  <&gcc GCC_SDCC2_APPS_CLK>,
 186                                  <&xo_board>;
 187                         clock-names = "iface", "core", "xo";
 188                         pinctrl-names = "default";
 189                         pinctrl-0 = <&sdhc2_default_state>;
 190                         status = "disabled";
 191                 };
 192
 193                 sdhc_3: mmc@f9864900 {
 194                         compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4";
 195                         reg = <0xf9864900 0x11c>, <0xf9864000 0x800>;
 196                         reg-names = "hc", "core";
 197                         interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
 198                                      <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
 199                         interrupt-names = "hc_irq", "pwr_irq";
 200                         clocks = <&gcc GCC_SDCC3_AHB_CLK>,
 201                                  <&gcc GCC_SDCC3_APPS_CLK>,
 202                                  <&xo_board>;
 203                         clock-names = "iface", "core", "xo";
 204                         pinctrl-names = "default";
 205                         pinctrl-0 = <&sdhc3_default_state>;
 206                         status = "disabled";
 207                 };
 208
 209                 blsp1_uart1: serial@f991d000 {
 210                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 211                         reg = <0xf991d000 0x1000>;
 212                         interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 213                         clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
 214                         clock-names = "core", "iface";
 215                         status = "disabled";
 216                 };
 217
 218                 blsp1_uart3: serial@f991f000 {
 219                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 220                         reg = <0xf991f000 0x1000>;
 221                         interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
 222                         clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
 223                         clock-names = "core", "iface";
 224                         status = "disabled";
 225                 };
 226
 227                 blsp1_uart4: serial@f9920000 {
 228                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 229                         reg = <0xf9920000 0x1000>;
 230                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 231                         clocks = <&gcc GCC_BLSP1_UART4_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
 232                         clock-names = "core", "iface";
 233                         status = "disabled";
 234                 };
 235
 236                 blsp1_i2c1: i2c@f9923000 {
 237                         status = "disabled";
 238                         compatible = "qcom,i2c-qup-v2.1.1";
 239                         reg = <0xf9923000 0x1000>;
 240                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 241                         clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
 242                         clock-names = "core", "iface";
 243                         pinctrl-names = "default";
 244                         pinctrl-0 = <&blsp1_i2c1_pins>;
 245                         #address-cells = <1>;
 246                         #size-cells = <0>;
 247                 };
 248
 249                 blsp1_i2c2: i2c@f9924000 {
 250                         status = "disabled";
 251                         compatible = "qcom,i2c-qup-v2.1.1";
 252                         reg = <0xf9924000 0x1000>;
 253                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 254                         clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
 255                         clock-names = "core", "iface";
 256                         pinctrl-names = "default";
 257                         pinctrl-0 = <&blsp1_i2c2_pins>;
 258                         #address-cells = <1>;
 259                         #size-cells = <0>;
 260                 };
 261
 262                 blsp1_i2c3: i2c@f9925000 {
 263                         status = "disabled";
 264                         compatible = "qcom,i2c-qup-v2.1.1";
 265                         reg = <0xf9925000 0x1000>;
 266                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 267                         clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
 268                         clock-names = "core", "iface";
 269                         pinctrl-names = "default";
 270                         pinctrl-0 = <&blsp1_i2c3_pins>;
 271                         #address-cells = <1>;
 272                         #size-cells = <0>;
 273                 };
 274
 275                 blsp1_i2c4: i2c@f9926000 {
 276                         status = "disabled";
 277                         compatible = "qcom,i2c-qup-v2.1.1";
 278                         reg = <0xf9926000 0x1000>;
 279                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 280                         clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
 281                         clock-names = "core", "iface";
 282                         pinctrl-names = "default";
 283                         pinctrl-0 = <&blsp1_i2c4_pins>;
 284                         #address-cells = <1>;
 285                         #size-cells = <0>;
 286                 };
 287
 288                 blsp1_i2c5: i2c@f9927000 {
 289                         status = "disabled";
 290                         compatible = "qcom,i2c-qup-v2.1.1";
 291                         reg = <0xf9927000 0x1000>;
 292                         interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 293                         clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
 294                         clock-names = "core", "iface";
 295                         pinctrl-names = "default";
 296                         pinctrl-0 = <&blsp1_i2c5_pins>;
 297                         #address-cells = <1>;
 298                         #size-cells = <0>;
 299                 };
 300
 301                 usb: usb@f9a55000 {
 302                         compatible = "qcom,ci-hdrc";
 303                         reg = <0xf9a55000 0x200>,
 304                               <0xf9a55200 0x200>;
 305                         interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
 306                         clocks = <&gcc GCC_USB_HS_AHB_CLK>,
 307                                  <&gcc GCC_USB_HS_SYSTEM_CLK>;
 308                         clock-names = "iface", "core";
 309                         assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
 310                         assigned-clock-rates = <75000000>;
 311                         resets = <&gcc GCC_USB_HS_BCR>;
 312                         reset-names = "core";
 313                         phy_type = "ulpi";
 314                         dr_mode = "otg";
 315                         hnp-disable;
 316                         srp-disable;
 317                         adp-disable;
 318                         ahb-burst-config = <0>;
 319                         phy-names = "usb-phy";
 320                         phys = <&usb_hs_phy>;
 321                         status = "disabled";
 322                         #reset-cells = <1>;
 323
 324                         ulpi {
 325                                 usb_hs_phy: phy {
 326                                         compatible = "qcom,usb-hs-phy-msm8226",
 327                                                      "qcom,usb-hs-phy";
 328                                         #phy-cells = <0>;
 329                                         clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
 330                                         clock-names = "ref", "sleep";
 331                                         resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>;
 332                                         reset-names = "phy", "por";
 333                                         qcom,init-seq = /bits/ 8 <0x0 0x44
 334                                                 0x1 0x68 0x2 0x24 0x3 0x13>;
 335                                 };
 336                         };
 337                 };
 338
 339                 gcc: clock-controller@fc400000 {
 340                         compatible = "qcom,gcc-msm8226";
 341                         reg = <0xfc400000 0x4000>;
 342                         #clock-cells = <1>;
 343                         #reset-cells = <1>;
 344                         #power-domain-cells = <1>;
 345                 };
 346
 347                 tlmm: pinctrl@fd510000 {
 348                         compatible = "qcom,msm8226-pinctrl";
 349                         reg = <0xfd510000 0x4000>;
 350                         gpio-controller;
 351                         #gpio-cells = <2>;
 352                         gpio-ranges = <&tlmm 0 0 117>;
 353                         interrupt-controller;
 354                         #interrupt-cells = <2>;
 355                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 356
 357                         blsp1_i2c1_pins: blsp1-i2c1 {
 358                                 pins = "gpio2", "gpio3";
 359                                 function = "blsp_i2c1";
 360                                 drive-strength = <2>;
 361                                 bias-disable;
 362                         };
 363
 364                         blsp1_i2c2_pins: blsp1-i2c2 {
 365                                 pins = "gpio6", "gpio7";
 366                                 function = "blsp_i2c2";
 367                                 drive-strength = <2>;
 368                                 bias-disable;
 369                         };
 370
 371                         blsp1_i2c3_pins: blsp1-i2c3 {
 372                                 pins = "gpio10", "gpio11";
 373                                 function = "blsp_i2c3";
 374                                 drive-strength = <2>;
 375                                 bias-disable;
 376                         };
 377
 378                         blsp1_i2c4_pins: blsp1-i2c4 {
 379                                 pins = "gpio14", "gpio15";
 380                                 function = "blsp_i2c4";
 381                                 drive-strength = <2>;
 382                                 bias-disable;
 383                         };
 384
 385                         blsp1_i2c5_pins: blsp1-i2c5 {
 386                                 pins = "gpio18", "gpio19";
 387                                 function = "blsp_i2c5";
 388                                 drive-strength = <2>;
 389                                 bias-disable;
 390                         };
 391
 392                         sdhc1_default_state: sdhc1-default-state {
 393                                 clk {
 394                                         pins = "sdc1_clk";
 395                                         drive-strength = <10>;
 396                                         bias-disable;
 397                                 };
 398
 399                                 cmd-data {
 400                                         pins = "sdc1_cmd", "sdc1_data";
 401                                         drive-strength = <10>;
 402                                         bias-pull-up;
 403                                 };
 404                         };
 405
 406                         sdhc2_default_state: sdhc2-default-state {
 407                                 clk {
 408                                         pins = "sdc2_clk";
 409                                         drive-strength = <10>;
 410                                         bias-disable;
 411                                 };
 412
 413                                 cmd-data {
 414                                         pins = "sdc2_cmd", "sdc2_data";
 415                                         drive-strength = <10>;
 416                                         bias-pull-up;
 417                                 };
 418                         };
 419
 420                         sdhc3_default_state: sdhc3-default-state {
 421                                 clk {
 422                                         pins = "gpio44";
 423                                         function = "sdc3";
 424                                         drive-strength = <8>;
 425                                         bias-disable;
 426                                 };
 427
 428                                 cmd {
 429                                         pins = "gpio43";
 430                                         function = "sdc3";
 431                                         drive-strength = <8>;
 432                                         bias-pull-up;
 433                                 };
 434
 435                                 data {
 436                                         pins = "gpio39", "gpio40", "gpio41", "gpio42";
 437                                         function = "sdc3";
 438                                         drive-strength = <8>;
 439                                         bias-pull-up;
 440                                 };
 441                         };
 442                 };
 443
 444                 restart@fc4ab000 {
 445                         compatible = "qcom,pshold";
 446                         reg = <0xfc4ab000 0x4>;
 447                 };
 448
 449                 spmi_bus: spmi@fc4cf000 {
 450                         compatible = "qcom,spmi-pmic-arb";
 451                         reg-names = "core", "intr", "cnfg";
 452                         reg = <0xfc4cf000 0x1000>,
 453                               <0xfc4cb000 0x1000>,
 454                               <0xfc4ca000 0x1000>;
 455                         interrupt-names = "periph_irq";
 456                         interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
 457                         qcom,ee = <0>;
 458                         qcom,channel = <0>;
 459                         #address-cells = <2>;
 460                         #size-cells = <0>;
 461                         interrupt-controller;
 462                         #interrupt-cells = <4>;
 463                 };
 464
 465                 rng@f9bff000 {
 466                         compatible = "qcom,prng";
 467                         reg = <0xf9bff000 0x200>;
 468                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
 469                         clock-names = "core";
 470                 };
 471
 472                 timer@f9020000 {
 473                         compatible = "arm,armv7-timer-mem";
 474                         reg = <0xf9020000 0x1000>;
 475                         #address-cells = <1>;
 476                         #size-cells = <1>;
 477                         ranges;
 478
 479                         frame@f9021000 {
 480                                 frame-number = <0>;
 481                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 482                                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 483                                 reg = <0xf9021000 0x1000>,
 484                                       <0xf9022000 0x1000>;
 485                         };
 486
 487                         frame@f9023000 {
 488                                 frame-number = <1>;
 489                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 490                                 reg = <0xf9023000 0x1000>;
 491                                 status = "disabled";
 492                         };
 493
 494                         frame@f9024000 {
 495                                 frame-number = <2>;
 496                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 497                                 reg = <0xf9024000 0x1000>;
 498                                 status = "disabled";
 499                         };
 500
 501                         frame@f9025000 {
 502                                 frame-number = <3>;
 503                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 504                                 reg = <0xf9025000 0x1000>;
 505                                 status = "disabled";
 506                         };
 507
 508                         frame@f9026000 {
 509                                 frame-number = <4>;
 510                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 511                                 reg = <0xf9026000 0x1000>;
 512                                 status = "disabled";
 513                         };
 514
 515                         frame@f9027000 {
 516                                 frame-number = <5>;
 517                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 518                                 reg = <0xf9027000 0x1000>;
 519                                 status = "disabled";
 520                         };
 521
 522                         frame@f9028000 {
 523                                 frame-number = <6>;
 524                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 525                                 reg = <0xf9028000 0x1000>;
 526                                 status = "disabled";
 527                         };
 528                 };
 529
 530                 rpm_msg_ram: memory@fc428000 {
 531                         compatible = "qcom,rpm-msg-ram";
 532                         reg = <0xfc428000 0x4000>;
 533                 };
 534
 535                 tcsr_mutex: hwlock@fd484000 {
 536                         compatible = "qcom,msm8226-tcsr-mutex", "qcom,tcsr-mutex";
 537                         reg = <0xfd484000 0x1000>;
 538                         #hwlock-cells = <1>;
 539                 };
 540
 541                 adsp: remoteproc@fe200000 {
 542                         compatible = "qcom,msm8226-adsp-pil";
 543                         reg = <0xfe200000 0x100>;
 544
 545                         interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
 546                                               <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
 547                                               <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
 548                                               <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
 549                                               <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
 550                         interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
 551
 552                         power-domains = <&rpmpd MSM8226_VDDCX>;
 553                         power-domain-names = "cx";
 554
 555                         clocks = <&xo_board>;
 556                         clock-names = "xo";
 557
 558                         memory-region = <&adsp_region>;
 559
 560                         qcom,smem-states = <&adsp_smp2p_out 0>;
 561                         qcom,smem-state-names = "stop";
 562
 563                         status = "disabled";
 564
 565                         smd-edge {
 566                                 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
 567
 568                                 qcom,ipc = <&apcs 8 8>;
 569                                 qcom,smd-edge = <1>;
 570
 571                                 label = "lpass";
 572                         };
 573                 };
 574         };
 575
 576         timer {
 577                 compatible = "arm,armv7-timer";
 578                 interrupts = <GIC_PPI 2
 579                                 (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>,
 580                              <GIC_PPI 3
 581                                 (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>,
 582                              <GIC_PPI 4
 583                                 (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>,
 584                              <GIC_PPI 1
 585                                 (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>;
 586         };
 587 };