2 * Device Tree Source for Qualcomm MDM9615 SoC
4 * Copyright (C) 2016 BayLibre, SAS.
5 * Author : Neil Armstrong <narmstrong@baylibre.com>
7 * This file is dual-licensed: you can use it either under the terms
8 * of the GPL or the X11 license, at your option. Note that this dual
9 * licensing only applies to this file, and not this project as a
12 * a) This file is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of the
15 * License, or (at your option) any later version.
17 * This file is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
24 * b) Permission is hereby granted, free of charge, to any person
25 * obtaining a copy of this software and associated documentation
26 * files (the "Software"), to deal in the Software without
27 * restriction, including without limitation the rights to use,
28 * copy, modify, merge, publish, distribute, sublicense, and/or
29 * sell copies of the Software, and to permit persons to whom the
30 * Software is furnished to do so, subject to the following
33 * The above copyright notice and this permission notice shall be
34 * included in all copies or substantial portions of the Software.
36 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
37 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
38 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
39 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
40 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
41 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
42 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
43 * OTHER DEALINGS IN THE SOFTWARE.
48 #include <dt-bindings/interrupt-controller/arm-gic.h>
49 #include <dt-bindings/clock/qcom,gcc-mdm9615.h>
50 #include <dt-bindings/reset/qcom,gcc-mdm9615.h>
51 #include <dt-bindings/mfd/qcom-rpm.h>
52 #include <dt-bindings/soc/qcom,gsbi.h>
57 model = "Qualcomm MDM9615";
58 compatible = "qcom,mdm9615";
59 interrupt-parent = <&intc>;
66 compatible = "arm,cortex-a5";
68 next-level-cache = <&L2>;
73 compatible = "arm,cortex-a5-pmu";
74 interrupts = <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
79 compatible = "fixed-clock";
81 clock-frequency = <19200000>;
85 vsdcc_fixed: vsdcc-regulator {
86 compatible = "regulator-fixed";
87 regulator-name = "SDCC Power";
88 regulator-min-microvolt = <2700000>;
89 regulator-max-microvolt = <2700000>;
97 compatible = "simple-bus";
99 L2: cache-controller@2040000 {
100 compatible = "arm,pl310-cache";
101 reg = <0x02040000 0x1000>;
102 arm,data-latency = <2 2 0>;
107 intc: interrupt-controller@2000000 {
108 compatible = "qcom,msm-qgic2";
109 interrupt-controller;
110 #interrupt-cells = <3>;
111 reg = <0x02000000 0x1000>,
116 compatible = "qcom,kpss-timer", "qcom,msm-timer";
117 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_EDGE_RISING)>,
118 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_EDGE_RISING)>,
119 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_EDGE_RISING)>;
120 reg = <0x0200a000 0x100>;
121 clock-frequency = <27000000>,
123 cpu-offset = <0x80000>;
126 msmgpio: pinctrl@800000 {
127 compatible = "qcom,mdm9615-pinctrl";
129 gpio-ranges = <&msmgpio 0 0 88>;
131 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
132 interrupt-controller;
133 #interrupt-cells = <2>;
134 reg = <0x800000 0x4000>;
137 gcc: clock-controller@900000 {
138 compatible = "qcom,gcc-mdm9615";
140 #power-domain-cells = <1>;
142 reg = <0x900000 0x4000>;
145 lcc: clock-controller@28000000 {
146 compatible = "qcom,lcc-mdm9615";
147 reg = <0x28000000 0x1000>;
152 l2cc: clock-controller@2011000 {
153 compatible = "qcom,kpss-gcc", "syscon";
154 reg = <0x02011000 0x1000>;
158 compatible = "qcom,prng";
159 reg = <0x1a500000 0x200>;
160 clocks = <&gcc PRNG_CLK>;
161 clock-names = "core";
162 assigned-clocks = <&gcc PRNG_CLK>;
163 assigned-clock-rates = <32000000>;
166 gsbi2: gsbi@16100000 {
167 compatible = "qcom,gsbi-v1.0.0";
169 reg = <0x16100000 0x100>;
170 clocks = <&gcc GSBI2_H_CLK>;
171 clock-names = "iface";
173 #address-cells = <1>;
177 gsbi2_i2c: i2c@16180000 {
178 compatible = "qcom,i2c-qup-v1.1.1";
179 #address-cells = <1>;
181 reg = <0x16180000 0x1000>;
182 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
184 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
185 clock-names = "core", "iface";
190 gsbi3: gsbi@16200000 {
191 compatible = "qcom,gsbi-v1.0.0";
193 reg = <0x16200000 0x100>;
194 clocks = <&gcc GSBI3_H_CLK>;
195 clock-names = "iface";
197 #address-cells = <1>;
201 gsbi3_spi: spi@16280000 {
202 compatible = "qcom,spi-qup-v1.1.1";
203 #address-cells = <1>;
205 reg = <0x16280000 0x1000>;
206 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
207 spi-max-frequency = <24000000>;
209 clocks = <&gcc GSBI3_QUP_CLK>, <&gcc GSBI3_H_CLK>;
210 clock-names = "core", "iface";
215 gsbi4: gsbi@16300000 {
216 compatible = "qcom,gsbi-v1.0.0";
218 reg = <0x16300000 0x100>;
219 clocks = <&gcc GSBI4_H_CLK>;
220 clock-names = "iface";
222 #address-cells = <1>;
226 syscon-tcsr = <&tcsr>;
228 gsbi4_serial: serial@16340000 {
229 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
230 reg = <0x16340000 0x1000>,
232 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
233 clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
234 clock-names = "core", "iface";
239 gsbi5: gsbi@16400000 {
240 compatible = "qcom,gsbi-v1.0.0";
242 reg = <0x16400000 0x100>;
243 clocks = <&gcc GSBI5_H_CLK>;
244 clock-names = "iface";
246 #address-cells = <1>;
250 syscon-tcsr = <&tcsr>;
252 gsbi5_i2c: i2c@16480000 {
253 compatible = "qcom,i2c-qup-v1.1.1";
254 #address-cells = <1>;
256 reg = <0x16480000 0x1000>;
257 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
259 /* QUP clock is not initialized, set rate */
260 assigned-clocks = <&gcc GSBI5_QUP_CLK>;
261 assigned-clock-rates = <24000000>;
263 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
264 clock-names = "core", "iface";
268 gsbi5_serial: serial@16440000 {
269 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
270 reg = <0x16440000 0x1000>,
272 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
273 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
274 clock-names = "core", "iface";
280 compatible = "qcom,ssbi";
281 reg = <0x500000 0x1000>;
282 qcom,controller-type = "pmic-arbiter";
285 compatible = "qcom,pm8018", "qcom,pm8921";
286 interrupts = <GIC_PPI 226 IRQ_TYPE_LEVEL_HIGH>;
287 #interrupt-cells = <2>;
288 interrupt-controller;
289 #address-cells = <1>;
293 compatible = "qcom,pm8018-pwrkey", "qcom,pm8921-pwrkey";
295 interrupt-parent = <&pmicintc>;
296 interrupts = <50 IRQ_TYPE_EDGE_RISING>,
297 <51 IRQ_TYPE_EDGE_RISING>;
303 compatible = "qcom,pm8018-mpp", "qcom,ssbi-mpp";
304 interrupt-controller;
305 #interrupt-cells = <2>;
309 gpio-ranges = <&pmicmpp 0 0 6>;
313 compatible = "qcom,pm8018-rtc", "qcom,pm8921-rtc";
314 interrupt-parent = <&pmicintc>;
315 interrupts = <39 IRQ_TYPE_EDGE_RISING>;
321 compatible = "qcom,pm8018-gpio", "qcom,ssbi-gpio";
323 interrupt-controller;
324 #interrupt-cells = <2>;
326 gpio-ranges = <&pmicgpio 0 0 6>;
332 sdcc1bam: dma-controller@12182000{
333 compatible = "qcom,bam-v1.3.0";
334 reg = <0x12182000 0x8000>;
335 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
336 clocks = <&gcc SDC1_H_CLK>;
337 clock-names = "bam_clk";
342 sdcc2bam: dma-controller@12142000{
343 compatible = "qcom,bam-v1.3.0";
344 reg = <0x12142000 0x8000>;
345 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
346 clocks = <&gcc SDC2_H_CLK>;
347 clock-names = "bam_clk";
353 compatible = "simple-bus";
354 #address-cells = <1>;
357 sdcc1: mmc@12180000 {
359 compatible = "arm,pl18x", "arm,primecell";
360 arm,primecell-periphid = <0x00051180>;
361 reg = <0x12180000 0x2000>;
362 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
363 interrupt-names = "cmd_irq";
364 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
365 clock-names = "mclk", "apb_pclk";
367 max-frequency = <48000000>;
370 vmmc-supply = <&vsdcc_fixed>;
371 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
372 dma-names = "tx", "rx";
373 assigned-clocks = <&gcc SDC1_CLK>;
374 assigned-clock-rates = <400000>;
377 sdcc2: mmc@12140000 {
378 compatible = "arm,pl18x", "arm,primecell";
379 arm,primecell-periphid = <0x00051180>;
381 reg = <0x12140000 0x2000>;
382 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
383 interrupt-names = "cmd_irq";
384 clocks = <&gcc SDC2_CLK>, <&gcc SDC2_H_CLK>;
385 clock-names = "mclk", "apb_pclk";
389 max-frequency = <48000000>;
391 vmmc-supply = <&vsdcc_fixed>;
392 dmas = <&sdcc2bam 2>, <&sdcc2bam 1>;
393 dma-names = "tx", "rx";
394 assigned-clocks = <&gcc SDC2_CLK>;
395 assigned-clock-rates = <400000>;
399 tcsr: syscon@1a400000 {
400 compatible = "qcom,tcsr-mdm9615", "syscon";
401 reg = <0x1a400000 0x100>;
405 compatible = "qcom,rpm-mdm9615";
406 reg = <0x108000 0x1000>;
408 qcom,ipc = <&l2cc 0x8 2>;
410 interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
411 <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
412 <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
413 interrupt-names = "ack", "err", "wakeup";
416 compatible = "qcom,rpm-pm8018-regulators";
418 vin_lvs1-supply = <&pm8018_s3>;
420 vdd_l7-supply = <&pm8018_s4>;
421 vdd_l8-supply = <&pm8018_s3>;
422 vdd_l9_l10_l11_l12-supply = <&pm8018_s5>;
426 regulator-min-microvolt = <500000>;
427 regulator-max-microvolt = <1150000>;
428 qcom,switch-mode-frequency = <1600000>;
433 regulator-min-microvolt = <1225000>;
434 regulator-max-microvolt = <1300000>;
435 qcom,switch-mode-frequency = <1600000>;
441 regulator-min-microvolt = <1800000>;
442 regulator-max-microvolt = <1800000>;
443 qcom,switch-mode-frequency = <1600000>;
448 regulator-min-microvolt = <2100000>;
449 regulator-max-microvolt = <2200000>;
450 qcom,switch-mode-frequency = <1600000>;
456 regulator-min-microvolt = <1350000>;
457 regulator-max-microvolt = <1350000>;
458 qcom,switch-mode-frequency = <1600000>;
465 regulator-min-microvolt = <1800000>;
466 regulator-max-microvolt = <1800000>;
472 regulator-min-microvolt = <1800000>;
473 regulator-max-microvolt = <1800000>;
478 regulator-min-microvolt = <3300000>;
479 regulator-max-microvolt = <3300000>;
484 regulator-min-microvolt = <2850000>;
485 regulator-max-microvolt = <2850000>;
490 regulator-min-microvolt = <1800000>;
491 regulator-max-microvolt = <2850000>;
496 regulator-min-microvolt = <1850000>;
497 regulator-max-microvolt = <1900000>;
502 regulator-min-microvolt = <1200000>;
503 regulator-max-microvolt = <1200000>;
508 regulator-min-microvolt = <750000>;
509 regulator-max-microvolt = <1150000>;
514 regulator-min-microvolt = <1050000>;
515 regulator-max-microvolt = <1050000>;
520 regulator-min-microvolt = <1050000>;
521 regulator-max-microvolt = <1050000>;
526 regulator-min-microvolt = <1050000>;
527 regulator-max-microvolt = <1050000>;
532 regulator-min-microvolt = <1850000>;
533 regulator-max-microvolt = <2950000>;
538 regulator-min-microvolt = <2850000>;
539 regulator-max-microvolt = <2850000>;
543 /* Low Voltage Switch */