arch/arm/boot/dts/qcom-mdm9615.dtsi

   1 /*
   2  * Device Tree Source for Qualcomm MDM9615 SoC
   3  *
   4  * Copyright (C) 2016 BayLibre, SAS.
   5  * Author : Neil Armstrong <narmstrong@baylibre.com>
   6  *
   7  * This file is dual-licensed: you can use it either under the terms
   8  * of the GPL or the X11 license, at your option. Note that this dual
   9  * licensing only applies to this file, and not this project as a
  10  * whole.
  11  *
  12  *  a) This file is free software; you can redistribute it and/or
  13  *     modify it under the terms of the GNU General Public License as
  14  *     published by the Free Software Foundation; either version 2 of the
  15  *     License, or (at your option) any later version.
  16  *
  17  *     This file is distributed in the hope that it will be useful,
  18  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  *     GNU General Public License for more details.
  21  *
  22  * Or, alternatively,
  23  *
  24  *  b) Permission is hereby granted, free of charge, to any person
  25  *     obtaining a copy of this software and associated documentation
  26  *     files (the "Software"), to deal in the Software without
  27  *     restriction, including without limitation the rights to use,
  28  *     copy, modify, merge, publish, distribute, sublicense, and/or
  29  *     sell copies of the Software, and to permit persons to whom the
  30  *     Software is furnished to do so, subject to the following
  31  *     conditions:
  32  *
  33  *     The above copyright notice and this permission notice shall be
  34  *     included in all copies or substantial portions of the Software.
  35  *
  36  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  37  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  38  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  39  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  40  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  41  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  42  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  43  *     OTHER DEALINGS IN THE SOFTWARE.
  44  */
  45
  46 /dts-v1/;
  47
  48 #include <dt-bindings/interrupt-controller/arm-gic.h>
  49 #include <dt-bindings/clock/qcom,gcc-mdm9615.h>
  50 #include <dt-bindings/reset/qcom,gcc-mdm9615.h>
  51 #include <dt-bindings/mfd/qcom-rpm.h>
  52 #include <dt-bindings/soc/qcom,gsbi.h>
  53
  54 / {
  55         #address-cells = <1>;
  56         #size-cells = <1>;
  57         model = "Qualcomm MDM9615";
  58         compatible = "qcom,mdm9615";
  59         interrupt-parent = <&intc>;
  60
  61         cpus {
  62                 #address-cells = <1>;
  63                 #size-cells = <0>;
  64
  65                 cpu0: cpu@0 {
  66                         compatible = "arm,cortex-a5";
  67                         device_type = "cpu";
  68                         next-level-cache = <&L2>;
  69                 };
  70         };
  71
  72         cpu-pmu {
  73                 compatible = "arm,cortex-a5-pmu";
  74                 interrupts = <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
  75         };
  76
  77         clocks {
  78                 cxo_board {
  79                         compatible = "fixed-clock";
  80                         #clock-cells = <0>;
  81                         clock-frequency = <19200000>;
  82                 };
  83         };
  84
  85         regulators {
  86                 vsdcc_fixed: vsdcc-regulator {
  87                         compatible = "regulator-fixed";
  88                         regulator-name = "SDCC Power";
  89                         regulator-min-microvolt = <2700000>;
  90                         regulator-max-microvolt = <2700000>;
  91                         regulator-always-on;
  92                 };
  93         };
  94
  95         soc: soc {
  96                 #address-cells = <1>;
  97                 #size-cells = <1>;
  98                 ranges;
  99                 compatible = "simple-bus";
 100
 101                 L2: cache-controller@2040000 {
 102                         compatible = "arm,pl310-cache";
 103                         reg = <0x02040000 0x1000>;
 104                         arm,data-latency = <2 2 0>;
 105                         cache-unified;
 106                         cache-level = <2>;
 107                 };
 108
 109                 intc: interrupt-controller@2000000 {
 110                         compatible = "qcom,msm-qgic2";
 111                         interrupt-controller;
 112                         #interrupt-cells = <3>;
 113                         reg = <0x02000000 0x1000>,
 114                               <0x02002000 0x1000>;
 115                 };
 116
 117                 timer@200a000 {
 118                         compatible = "qcom,kpss-timer", "qcom,msm-timer";
 119                         interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_EDGE_RISING)>,
 120                                      <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_EDGE_RISING)>,
 121                                      <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_EDGE_RISING)>;
 122                         reg = <0x0200a000 0x100>;
 123                         clock-frequency = <27000000>,
 124                                           <32768>;
 125                         cpu-offset = <0x80000>;
 126                 };
 127
 128                 msmgpio: pinctrl@800000 {
 129                         compatible = "qcom,mdm9615-pinctrl";
 130                         gpio-controller;
 131                         gpio-ranges = <&msmgpio 0 0 88>;
 132                         #gpio-cells = <2>;
 133                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 134                         interrupt-controller;
 135                         #interrupt-cells = <2>;
 136                         reg = <0x800000 0x4000>;
 137                 };
 138
 139                 gcc: clock-controller@900000 {
 140                         compatible = "qcom,gcc-mdm9615";
 141                         #clock-cells = <1>;
 142                         #power-domain-cells = <1>;
 143                         #reset-cells = <1>;
 144                         reg = <0x900000 0x4000>;
 145                 };
 146
 147                 lcc: clock-controller@28000000 {
 148                         compatible = "qcom,lcc-mdm9615";
 149                         reg = <0x28000000 0x1000>;
 150                         #clock-cells = <1>;
 151                         #reset-cells = <1>;
 152                 };
 153
 154                 l2cc: clock-controller@2011000 {
 155                         compatible = "qcom,kpss-gcc", "syscon";
 156                         reg = <0x02011000 0x1000>;
 157                 };
 158
 159                 rng@1a500000 {
 160                         compatible = "qcom,prng";
 161                         reg = <0x1a500000 0x200>;
 162                         clocks = <&gcc PRNG_CLK>;
 163                         clock-names = "core";
 164                         assigned-clocks = <&gcc PRNG_CLK>;
 165                         assigned-clock-rates = <32000000>;
 166                 };
 167
 168                 gsbi2: gsbi@16100000 {
 169                         compatible = "qcom,gsbi-v1.0.0";
 170                         cell-index = <2>;
 171                         reg = <0x16100000 0x100>;
 172                         clocks = <&gcc GSBI2_H_CLK>;
 173                         clock-names = "iface";
 174                         status = "disabled";
 175                         #address-cells = <1>;
 176                         #size-cells = <1>;
 177                         ranges;
 178
 179                         gsbi2_i2c: i2c@16180000 {
 180                                 compatible = "qcom,i2c-qup-v1.1.1";
 181                                 #address-cells = <1>;
 182                                 #size-cells = <0>;
 183                                 reg = <0x16180000 0x1000>;
 184                                 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
 185
 186                                 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
 187                                 clock-names = "core", "iface";
 188                                 status = "disabled";
 189                         };
 190                 };
 191
 192                 gsbi3: gsbi@16200000 {
 193                         compatible = "qcom,gsbi-v1.0.0";
 194                         cell-index = <3>;
 195                         reg = <0x16200000 0x100>;
 196                         clocks = <&gcc GSBI3_H_CLK>;
 197                         clock-names = "iface";
 198                         status = "disabled";
 199                         #address-cells = <1>;
 200                         #size-cells = <1>;
 201                         ranges;
 202
 203                         gsbi3_spi: spi@16280000 {
 204                                 compatible = "qcom,spi-qup-v1.1.1";
 205                                 #address-cells = <1>;
 206                                 #size-cells = <0>;
 207                                 reg = <0x16280000 0x1000>;
 208                                 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
 209                                 spi-max-frequency = <24000000>;
 210
 211                                 clocks = <&gcc GSBI3_QUP_CLK>, <&gcc GSBI3_H_CLK>;
 212                                 clock-names = "core", "iface";
 213                                 status = "disabled";
 214                         };
 215                 };
 216
 217                 gsbi4: gsbi@16300000 {
 218                         compatible = "qcom,gsbi-v1.0.0";
 219                         cell-index = <4>;
 220                         reg = <0x16300000 0x100>;
 221                         clocks = <&gcc GSBI4_H_CLK>;
 222                         clock-names = "iface";
 223                         status = "disabled";
 224                         #address-cells = <1>;
 225                         #size-cells = <1>;
 226                         ranges;
 227
 228                         syscon-tcsr = <&tcsr>;
 229
 230                         gsbi4_serial: serial@16340000 {
 231                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 232                                 reg = <0x16340000 0x1000>,
 233                                       <0x16300000 0x1000>;
 234                                 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
 235                                 clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
 236                                 clock-names = "core", "iface";
 237                                 status = "disabled";
 238                         };
 239                 };
 240
 241                 gsbi5: gsbi@16400000 {
 242                         compatible = "qcom,gsbi-v1.0.0";
 243                         cell-index = <5>;
 244                         reg = <0x16400000 0x100>;
 245                         clocks = <&gcc GSBI5_H_CLK>;
 246                         clock-names = "iface";
 247                         status = "disabled";
 248                         #address-cells = <1>;
 249                         #size-cells = <1>;
 250                         ranges;
 251
 252                         syscon-tcsr = <&tcsr>;
 253
 254                         gsbi5_i2c: i2c@16480000 {
 255                                 compatible = "qcom,i2c-qup-v1.1.1";
 256                                 #address-cells = <1>;
 257                                 #size-cells = <0>;
 258                                 reg = <0x16480000 0x1000>;
 259                                 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
 260
 261                                 /* QUP clock is not initialized, set rate */
 262                                 assigned-clocks = <&gcc GSBI5_QUP_CLK>;
 263                                 assigned-clock-rates = <24000000>;
 264
 265                                 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
 266                                 clock-names = "core", "iface";
 267                                 status = "disabled";
 268                         };
 269
 270                         gsbi5_serial: serial@16440000 {
 271                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 272                                 reg = <0x16440000 0x1000>,
 273                                       <0x16400000 0x1000>;
 274                                 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
 275                                 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
 276                                 clock-names = "core", "iface";
 277                                 status = "disabled";
 278                         };
 279                 };
 280
 281                 qcom,ssbi@500000 {
 282                         compatible = "qcom,ssbi";
 283                         reg = <0x500000 0x1000>;
 284                         qcom,controller-type = "pmic-arbiter";
 285
 286                         pmicintc: pmic@0 {
 287                                 compatible = "qcom,pm8018", "qcom,pm8921";
 288                                 interrupts = <GIC_PPI 226 IRQ_TYPE_LEVEL_HIGH>;
 289                                 #interrupt-cells = <2>;
 290                                 interrupt-controller;
 291                                 #address-cells = <1>;
 292                                 #size-cells = <0>;
 293
 294                                 pwrkey@1c {
 295                                         compatible = "qcom,pm8018-pwrkey", "qcom,pm8921-pwrkey";
 296                                         reg = <0x1c>;
 297                                         interrupt-parent = <&pmicintc>;
 298                                         interrupts = <50 IRQ_TYPE_EDGE_RISING>,
 299                                                      <51 IRQ_TYPE_EDGE_RISING>;
 300                                         debounce = <15625>;
 301                                         pull-up;
 302                                 };
 303
 304                                 pmicmpp: mpps@50 {
 305                                         compatible = "qcom,pm8018-mpp", "qcom,ssbi-mpp";
 306                                         interrupt-controller;
 307                                         #interrupt-cells = <2>;
 308                                         reg = <0x50>;
 309                                         gpio-controller;
 310                                         #gpio-cells = <2>;
 311                                         gpio-ranges = <&pmicmpp 0 0 6>;
 312                                 };
 313
 314                                 rtc@11d {
 315                                         compatible = "qcom,pm8018-rtc", "qcom,pm8921-rtc";
 316                                         interrupt-parent = <&pmicintc>;
 317                                         interrupts = <39 IRQ_TYPE_EDGE_RISING>;
 318                                         reg = <0x11d>;
 319                                         allow-set-time;
 320                                 };
 321
 322                                 pmicgpio: gpio@150 {
 323                                         compatible = "qcom,pm8018-gpio", "qcom,ssbi-gpio";
 324                                         interrupt-controller;
 325                                         #interrupt-cells = <2>;
 326                                         gpio-controller;
 327                                         gpio-ranges = <&pmicgpio 0 0 6>;
 328                                         #gpio-cells = <2>;
 329                                 };
 330                         };
 331                 };
 332
 333                 sdcc1bam: dma-controller@12182000{
 334                         compatible = "qcom,bam-v1.3.0";
 335                         reg = <0x12182000 0x8000>;
 336                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 337                         clocks = <&gcc SDC1_H_CLK>;
 338                         clock-names = "bam_clk";
 339                         #dma-cells = <1>;
 340                         qcom,ee = <0>;
 341                 };
 342
 343                 sdcc2bam: dma-controller@12142000{
 344                         compatible = "qcom,bam-v1.3.0";
 345                         reg = <0x12142000 0x8000>;
 346                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 347                         clocks = <&gcc SDC2_H_CLK>;
 348                         clock-names = "bam_clk";
 349                         #dma-cells = <1>;
 350                         qcom,ee = <0>;
 351                 };
 352
 353                 amba {
 354                         compatible = "simple-bus";
 355                         #address-cells = <1>;
 356                         #size-cells = <1>;
 357                         ranges;
 358                         sdcc1: mmc@12180000 {
 359                                 status = "disabled";
 360                                 compatible = "arm,pl18x", "arm,primecell";
 361                                 arm,primecell-periphid = <0x00051180>;
 362                                 reg = <0x12180000 0x2000>;
 363                                 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
 364                                 interrupt-names = "cmd_irq";
 365                                 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
 366                                 clock-names = "mclk", "apb_pclk";
 367                                 bus-width = <8>;
 368                                 max-frequency = <48000000>;
 369                                 cap-sd-highspeed;
 370                                 cap-mmc-highspeed;
 371                                 vmmc-supply = <&vsdcc_fixed>;
 372                                 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
 373                                 dma-names = "tx", "rx";
 374                                 assigned-clocks = <&gcc SDC1_CLK>;
 375                                 assigned-clock-rates = <400000>;
 376                         };
 377
 378                         sdcc2: mmc@12140000 {
 379                                 compatible = "arm,pl18x", "arm,primecell";
 380                                 arm,primecell-periphid = <0x00051180>;
 381                                 status = "disabled";
 382                                 reg = <0x12140000 0x2000>;
 383                                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 384                                 interrupt-names = "cmd_irq";
 385                                 clocks = <&gcc SDC2_CLK>, <&gcc SDC2_H_CLK>;
 386                                 clock-names = "mclk", "apb_pclk";
 387                                 bus-width = <4>;
 388                                 cap-sd-highspeed;
 389                                 cap-mmc-highspeed;
 390                                 max-frequency = <48000000>;
 391                                 no-1-8-v;
 392                                 vmmc-supply = <&vsdcc_fixed>;
 393                                 dmas = <&sdcc2bam 2>, <&sdcc2bam 1>;
 394                                 dma-names = "tx", "rx";
 395                                 assigned-clocks = <&gcc SDC2_CLK>;
 396                                 assigned-clock-rates = <400000>;
 397                         };
 398                 };
 399
 400                 tcsr: syscon@1a400000 {
 401                         compatible = "qcom,tcsr-mdm9615", "syscon";
 402                         reg = <0x1a400000 0x100>;
 403                 };
 404
 405                 rpm: rpm@108000 {
 406                         compatible = "qcom,rpm-mdm9615";
 407                         reg = <0x108000 0x1000>;
 408
 409                         qcom,ipc = <&l2cc 0x8 2>;
 410
 411                         interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
 412                                      <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
 413                                      <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
 414                         interrupt-names = "ack", "err", "wakeup";
 415
 416                         regulators {
 417                                 compatible = "qcom,rpm-pm8018-regulators";
 418
 419                                 vin_lvs1-supply = <&pm8018_s3>;
 420
 421                                 vdd_l7-supply = <&pm8018_s4>;
 422                                 vdd_l8-supply = <&pm8018_s3>;
 423                                 vdd_l9_l10_l11_l12-supply = <&pm8018_s5>;
 424
 425                                 /* Buck SMPS */
 426                                 pm8018_s1: s1 {
 427                                         regulator-min-microvolt = <500000>;
 428                                         regulator-max-microvolt = <1150000>;
 429                                         qcom,switch-mode-frequency = <1600000>;
 430                                         bias-pull-down;
 431                                 };
 432
 433                                 pm8018_s2: s2 {
 434                                         regulator-min-microvolt = <1225000>;
 435                                         regulator-max-microvolt = <1300000>;
 436                                         qcom,switch-mode-frequency = <1600000>;
 437                                         bias-pull-down;
 438                                 };
 439
 440                                 pm8018_s3: s3 {
 441                                         regulator-always-on;
 442                                         regulator-min-microvolt = <1800000>;
 443                                         regulator-max-microvolt = <1800000>;
 444                                         qcom,switch-mode-frequency = <1600000>;
 445                                         bias-pull-down;
 446                                 };
 447
 448                                 pm8018_s4: s4 {
 449                                         regulator-min-microvolt = <2100000>;
 450                                         regulator-max-microvolt = <2200000>;
 451                                         qcom,switch-mode-frequency = <1600000>;
 452                                         bias-pull-down;
 453                                 };
 454
 455                                 pm8018_s5: s5 {
 456                                         regulator-always-on;
 457                                         regulator-min-microvolt = <1350000>;
 458                                         regulator-max-microvolt = <1350000>;
 459                                         qcom,switch-mode-frequency = <1600000>;
 460                                         bias-pull-down;
 461                                 };
 462
 463                                 /* PMOS LDO */
 464                                 pm8018_l2: l2 {
 465                                         regulator-always-on;
 466                                         regulator-min-microvolt = <1800000>;
 467                                         regulator-max-microvolt = <1800000>;
 468                                         bias-pull-down;
 469                                 };
 470
 471                                 pm8018_l3: l3 {
 472                                         regulator-always-on;
 473                                         regulator-min-microvolt = <1800000>;
 474                                         regulator-max-microvolt = <1800000>;
 475                                         bias-pull-down;
 476                                 };
 477
 478                                 pm8018_l4: l4 {
 479                                         regulator-min-microvolt = <3300000>;
 480                                         regulator-max-microvolt = <3300000>;
 481                                         bias-pull-down;
 482                                 };
 483
 484                                 pm8018_l5: l5 {
 485                                         regulator-min-microvolt = <2850000>;
 486                                         regulator-max-microvolt = <2850000>;
 487                                         bias-pull-down;
 488                                 };
 489
 490                                 pm8018_l6: l6 {
 491                                         regulator-min-microvolt = <1800000>;
 492                                         regulator-max-microvolt = <2850000>;
 493                                         bias-pull-down;
 494                                 };
 495
 496                                 pm8018_l7: l7 {
 497                                         regulator-min-microvolt = <1850000>;
 498                                         regulator-max-microvolt = <1900000>;
 499                                         bias-pull-down;
 500                                 };
 501
 502                                 pm8018_l8: l8 {
 503                                         regulator-min-microvolt = <1200000>;
 504                                         regulator-max-microvolt = <1200000>;
 505                                         bias-pull-down;
 506                                 };
 507
 508                                 pm8018_l9: l9 {
 509                                         regulator-min-microvolt = <750000>;
 510                                         regulator-max-microvolt = <1150000>;
 511                                         bias-pull-down;
 512                                 };
 513
 514                                 pm8018_l10: l10 {
 515                                         regulator-min-microvolt = <1050000>;
 516                                         regulator-max-microvolt = <1050000>;
 517                                         bias-pull-down;
 518                                 };
 519
 520                                 pm8018_l11: l11 {
 521                                         regulator-min-microvolt = <1050000>;
 522                                         regulator-max-microvolt = <1050000>;
 523                                         bias-pull-down;
 524                                 };
 525
 526                                 pm8018_l12: l12 {
 527                                         regulator-min-microvolt = <1050000>;
 528                                         regulator-max-microvolt = <1050000>;
 529                                         bias-pull-down;
 530                                 };
 531
 532                                 pm8018_l13: l13 {
 533                                         regulator-min-microvolt = <1850000>;
 534                                         regulator-max-microvolt = <2950000>;
 535                                         bias-pull-down;
 536                                 };
 537
 538                                 pm8018_l14: l14 {
 539                                         regulator-min-microvolt = <2850000>;
 540                                         regulator-max-microvolt = <2850000>;
 541                                         bias-pull-down;
 542                                 };
 543
 544                                 /* Low Voltage Switch */
 545                                 pm8018_lvs1: lvs1 {
 546                                         bias-pull-down;
 547                                 };
 548                         };
 549                 };
 550         };
 551 };