arch/arm/boot/dts/qcom-mdm9615.dtsi

   1 /*
   2  * Device Tree Source for Qualcomm MDM9615 SoC
   3  *
   4  * Copyright (C) 2016 BayLibre, SAS.
   5  * Author : Neil Armstrong <narmstrong@baylibre.com>
   6  *
   7  * This file is dual-licensed: you can use it either under the terms
   8  * of the GPL or the X11 license, at your option. Note that this dual
   9  * licensing only applies to this file, and not this project as a
  10  * whole.
  11  *
  12  *  a) This file is free software; you can redistribute it and/or
  13  *     modify it under the terms of the GNU General Public License as
  14  *     published by the Free Software Foundation; either version 2 of the
  15  *     License, or (at your option) any later version.
  16  *
  17  *     This file is distributed in the hope that it will be useful,
  18  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  *     GNU General Public License for more details.
  21  *
  22  * Or, alternatively,
  23  *
  24  *  b) Permission is hereby granted, free of charge, to any person
  25  *     obtaining a copy of this software and associated documentation
  26  *     files (the "Software"), to deal in the Software without
  27  *     restriction, including without limitation the rights to use,
  28  *     copy, modify, merge, publish, distribute, sublicense, and/or
  29  *     sell copies of the Software, and to permit persons to whom the
  30  *     Software is furnished to do so, subject to the following
  31  *     conditions:
  32  *
  33  *     The above copyright notice and this permission notice shall be
  34  *     included in all copies or substantial portions of the Software.
  35  *
  36  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  37  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  38  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  39  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  40  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  41  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  42  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  43  *     OTHER DEALINGS IN THE SOFTWARE.
  44  */
  45
  46 /dts-v1/;
  47
  48 #include <dt-bindings/interrupt-controller/arm-gic.h>
  49 #include <dt-bindings/clock/qcom,gcc-mdm9615.h>
  50 #include <dt-bindings/reset/qcom,gcc-mdm9615.h>
  51 #include <dt-bindings/mfd/qcom-rpm.h>
  52 #include <dt-bindings/soc/qcom,gsbi.h>
  53
  54 / {
  55         #address-cells = <1>;
  56         #size-cells = <1>;
  57         model = "Qualcomm MDM9615";
  58         compatible = "qcom,mdm9615";
  59         interrupt-parent = <&intc>;
  60
  61         cpus {
  62                 #address-cells = <1>;
  63                 #size-cells = <0>;
  64
  65                 cpu0: cpu@0 {
  66                         compatible = "arm,cortex-a5";
  67                         device_type = "cpu";
  68                         next-level-cache = <&L2>;
  69                 };
  70         };
  71
  72         cpu-pmu {
  73                 compatible = "arm,cortex-a5-pmu";
  74                 interrupts = <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
  75         };
  76
  77         clocks {
  78                 cxo_board {
  79                         compatible = "fixed-clock";
  80                         #clock-cells = <0>;
  81                         clock-frequency = <19200000>;
  82                 };
  83         };
  84
  85         vsdcc_fixed: vsdcc-regulator {
  86                 compatible = "regulator-fixed";
  87                 regulator-name = "SDCC Power";
  88                 regulator-min-microvolt = <2700000>;
  89                 regulator-max-microvolt = <2700000>;
  90                 regulator-always-on;
  91         };
  92
  93         soc: soc {
  94                 #address-cells = <1>;
  95                 #size-cells = <1>;
  96                 ranges;
  97                 compatible = "simple-bus";
  98
  99                 L2: l2-cache@2040000 {
 100                         compatible = "arm,pl310-cache";
 101                         reg = <0x02040000 0x1000>;
 102                         arm,data-latency = <2 2 0>;
 103                         cache-unified;
 104                         cache-level = <2>;
 105                 };
 106
 107                 intc: interrupt-controller@2000000 {
 108                         compatible = "qcom,msm-qgic2";
 109                         interrupt-controller;
 110                         #interrupt-cells = <3>;
 111                         reg = <0x02000000 0x1000>,
 112                               <0x02002000 0x1000>;
 113                 };
 114
 115                 timer@200a000 {
 116                         compatible = "qcom,kpss-timer", "qcom,msm-timer";
 117                         interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_EDGE_RISING)>,
 118                                      <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_EDGE_RISING)>,
 119                                      <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_EDGE_RISING)>;
 120                         reg = <0x0200a000 0x100>;
 121                         clock-frequency = <27000000>,
 122                                           <32768>;
 123                         cpu-offset = <0x80000>;
 124                 };
 125
 126                 msmgpio: pinctrl@800000 {
 127                         compatible = "qcom,mdm9615-pinctrl";
 128                         gpio-controller;
 129                         #gpio-cells = <2>;
 130                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 131                         interrupt-controller;
 132                         #interrupt-cells = <2>;
 133                         reg = <0x800000 0x4000>;
 134                 };
 135
 136                 gcc: clock-controller@900000 {
 137                         compatible = "qcom,gcc-mdm9615";
 138                         #clock-cells = <1>;
 139                         #reset-cells = <1>;
 140                         reg = <0x900000 0x4000>;
 141                 };
 142
 143                 lcc: clock-controller@28000000 {
 144                         compatible = "qcom,lcc-mdm9615";
 145                         reg = <0x28000000 0x1000>;
 146                         #clock-cells = <1>;
 147                         #reset-cells = <1>;
 148                 };
 149
 150                 l2cc: clock-controller@2011000 {
 151                         compatible = "syscon";
 152                         reg = <0x02011000 0x1000>;
 153                 };
 154
 155                 rng@1a500000 {
 156                         compatible = "qcom,prng";
 157                         reg = <0x1a500000 0x200>;
 158                         clocks = <&gcc PRNG_CLK>;
 159                         clock-names = "core";
 160                         assigned-clocks = <&gcc PRNG_CLK>;
 161                         assigned-clock-rates = <32000000>;
 162                 };
 163
 164                 gsbi2: gsbi@16100000 {
 165                         compatible = "qcom,gsbi-v1.0.0";
 166                         cell-index = <2>;
 167                         reg = <0x16100000 0x100>;
 168                         clocks = <&gcc GSBI2_H_CLK>;
 169                         clock-names = "iface";
 170                         status = "disabled";
 171                         #address-cells = <1>;
 172                         #size-cells = <1>;
 173                         ranges;
 174
 175                         gsbi2_i2c: i2c@16180000 {
 176                                 compatible = "qcom,i2c-qup-v1.1.1";
 177                                 #address-cells = <1>;
 178                                 #size-cells = <0>;
 179                                 reg = <0x16180000 0x1000>;
 180                                 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
 181
 182                                 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
 183                                 clock-names = "core", "iface";
 184                                 status = "disabled";
 185                         };
 186                 };
 187
 188                 gsbi3: gsbi@16200000 {
 189                         compatible = "qcom,gsbi-v1.0.0";
 190                         cell-index = <3>;
 191                         reg = <0x16200000 0x100>;
 192                         clocks = <&gcc GSBI3_H_CLK>;
 193                         clock-names = "iface";
 194                         status = "disabled";
 195                         #address-cells = <1>;
 196                         #size-cells = <1>;
 197                         ranges;
 198
 199                         gsbi3_spi: spi@16280000 {
 200                                 compatible = "qcom,spi-qup-v1.1.1";
 201                                 #address-cells = <1>;
 202                                 #size-cells = <0>;
 203                                 reg = <0x16280000 0x1000>;
 204                                 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
 205                                 spi-max-frequency = <24000000>;
 206
 207                                 clocks = <&gcc GSBI3_QUP_CLK>, <&gcc GSBI3_H_CLK>;
 208                                 clock-names = "core", "iface";
 209                                 status = "disabled";
 210                         };
 211                 };
 212
 213                 gsbi4: gsbi@16300000 {
 214                         compatible = "qcom,gsbi-v1.0.0";
 215                         cell-index = <4>;
 216                         reg = <0x16300000 0x100>;
 217                         clocks = <&gcc GSBI4_H_CLK>;
 218                         clock-names = "iface";
 219                         status = "disabled";
 220                         #address-cells = <1>;
 221                         #size-cells = <1>;
 222                         ranges;
 223
 224                         syscon-tcsr = <&tcsr>;
 225
 226                         gsbi4_serial: serial@16340000 {
 227                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 228                                 reg = <0x16340000 0x1000>,
 229                                       <0x16300000 0x1000>;
 230                                 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
 231                                 clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
 232                                 clock-names = "core", "iface";
 233                                 status = "disabled";
 234                         };
 235                 };
 236
 237                 gsbi5: gsbi@16400000 {
 238                         compatible = "qcom,gsbi-v1.0.0";
 239                         cell-index = <5>;
 240                         reg = <0x16400000 0x100>;
 241                         clocks = <&gcc GSBI5_H_CLK>;
 242                         clock-names = "iface";
 243                         status = "disabled";
 244                         #address-cells = <1>;
 245                         #size-cells = <1>;
 246                         ranges;
 247
 248                         syscon-tcsr = <&tcsr>;
 249
 250                         gsbi5_i2c: i2c@16480000 {
 251                                 compatible = "qcom,i2c-qup-v1.1.1";
 252                                 #address-cells = <1>;
 253                                 #size-cells = <0>;
 254                                 reg = <0x16480000 0x1000>;
 255                                 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
 256
 257                                 /* QUP clock is not initialized, set rate */
 258                                 assigned-clocks = <&gcc GSBI5_QUP_CLK>;
 259                                 assigned-clock-rates = <24000000>;
 260
 261                                 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
 262                                 clock-names = "core", "iface";
 263                                 status = "disabled";
 264                         };
 265
 266                         gsbi5_serial: serial@16440000 {
 267                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 268                                 reg = <0x16440000 0x1000>,
 269                                       <0x16400000 0x1000>;
 270                                 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
 271                                 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
 272                                 clock-names = "core", "iface";
 273                                 status = "disabled";
 274                         };
 275                 };
 276
 277                 qcom,ssbi@500000 {
 278                         compatible = "qcom,ssbi";
 279                         reg = <0x500000 0x1000>;
 280                         qcom,controller-type = "pmic-arbiter";
 281
 282                         pmicintc: pmic@0 {
 283                                 compatible = "qcom,pm8018", "qcom,pm8921";
 284                                 interrupts = <GIC_PPI 226 IRQ_TYPE_LEVEL_HIGH>;
 285                                 #interrupt-cells = <2>;
 286                                 interrupt-controller;
 287                                 #address-cells = <1>;
 288                                 #size-cells = <0>;
 289
 290                                 pwrkey@1c {
 291                                         compatible = "qcom,pm8018-pwrkey", "qcom,pm8921-pwrkey";
 292                                         reg = <0x1c>;
 293                                         interrupt-parent = <&pmicintc>;
 294                                         interrupts = <50 IRQ_TYPE_EDGE_RISING>,
 295                                                      <51 IRQ_TYPE_EDGE_RISING>;
 296                                         debounce = <15625>;
 297                                         pull-up;
 298                                 };
 299
 300                                 pmicmpp: mpp@50 {
 301                                         compatible = "qcom,pm8018-mpp", "qcom,ssbi-mpp";
 302                                         interrupt-parent = <&pmicintc>;
 303                                         interrupts = <24 IRQ_TYPE_NONE>,
 304                                                      <25 IRQ_TYPE_NONE>,
 305                                                      <26 IRQ_TYPE_NONE>,
 306                                                      <27 IRQ_TYPE_NONE>,
 307                                                      <28 IRQ_TYPE_NONE>,
 308                                                      <29 IRQ_TYPE_NONE>;
 309                                         reg = <0x50>;
 310                                         gpio-controller;
 311                                         #gpio-cells = <2>;
 312                                 };
 313
 314                                 rtc@11d {
 315                                         compatible = "qcom,pm8018-rtc", "qcom,pm8921-rtc";
 316                                         interrupt-parent = <&pmicintc>;
 317                                         interrupts = <39 IRQ_TYPE_EDGE_RISING>;
 318                                         reg = <0x11d>;
 319                                         allow-set-time;
 320                                 };
 321
 322                                 pmicgpio: gpio@150 {
 323                                         compatible = "qcom,pm8018-gpio", "qcom,ssbi-gpio";
 324                                         reg = <0x150>;
 325                                         interrupt-controller;
 326                                         #interrupt-cells = <2>;
 327                                         gpio-controller;
 328                                         gpio-ranges = <&pmicgpio 0 0 6>;
 329                                         #gpio-cells = <2>;
 330                                 };
 331                         };
 332                 };
 333
 334                 sdcc1bam: dma@12182000{
 335                         compatible = "qcom,bam-v1.3.0";
 336                         reg = <0x12182000 0x8000>;
 337                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 338                         clocks = <&gcc SDC1_H_CLK>;
 339                         clock-names = "bam_clk";
 340                         #dma-cells = <1>;
 341                         qcom,ee = <0>;
 342                 };
 343
 344                 sdcc2bam: dma@12142000{
 345                         compatible = "qcom,bam-v1.3.0";
 346                         reg = <0x12142000 0x8000>;
 347                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 348                         clocks = <&gcc SDC2_H_CLK>;
 349                         clock-names = "bam_clk";
 350                         #dma-cells = <1>;
 351                         qcom,ee = <0>;
 352                 };
 353
 354                 amba {
 355                         compatible = "simple-bus";
 356                         #address-cells = <1>;
 357                         #size-cells = <1>;
 358                         ranges;
 359                         sdcc1: sdcc@12180000 {
 360                                 status = "disabled";
 361                                 compatible = "arm,pl18x", "arm,primecell";
 362                                 arm,primecell-periphid = <0x00051180>;
 363                                 reg = <0x12180000 0x2000>;
 364                                 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
 365                                 interrupt-names = "cmd_irq";
 366                                 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
 367                                 clock-names = "mclk", "apb_pclk";
 368                                 bus-width = <8>;
 369                                 max-frequency = <48000000>;
 370                                 cap-sd-highspeed;
 371                                 cap-mmc-highspeed;
 372                                 vmmc-supply = <&vsdcc_fixed>;
 373                                 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
 374                                 dma-names = "tx", "rx";
 375                                 assigned-clocks = <&gcc SDC1_CLK>;
 376                                 assigned-clock-rates = <400000>;
 377                         };
 378
 379                         sdcc2: sdcc@12140000 {
 380                                 compatible = "arm,pl18x", "arm,primecell";
 381                                 arm,primecell-periphid = <0x00051180>;
 382                                 status = "disabled";
 383                                 reg = <0x12140000 0x2000>;
 384                                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 385                                 interrupt-names = "cmd_irq";
 386                                 clocks = <&gcc SDC2_CLK>, <&gcc SDC2_H_CLK>;
 387                                 clock-names = "mclk", "apb_pclk";
 388                                 bus-width = <4>;
 389                                 cap-sd-highspeed;
 390                                 cap-mmc-highspeed;
 391                                 max-frequency = <48000000>;
 392                                 no-1-8-v;
 393                                 vmmc-supply = <&vsdcc_fixed>;
 394                                 dmas = <&sdcc2bam 2>, <&sdcc2bam 1>;
 395                                 dma-names = "tx", "rx";
 396                                 assigned-clocks = <&gcc SDC2_CLK>;
 397                                 assigned-clock-rates = <400000>;
 398                         };
 399                 };
 400
 401                 tcsr: syscon@1a400000 {
 402                         compatible = "qcom,tcsr-mdm9615", "syscon";
 403                         reg = <0x1a400000 0x100>;
 404                 };
 405
 406                 rpm: rpm@108000 {
 407                         compatible = "qcom,rpm-mdm9615";
 408                         reg = <0x108000 0x1000>;
 409
 410                         qcom,ipc = <&l2cc 0x8 2>;
 411
 412                         interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
 413                                      <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
 414                                      <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
 415                         interrupt-names = "ack", "err", "wakeup";
 416
 417                         regulators {
 418                                 compatible = "qcom,rpm-pm8018-regulators";
 419
 420                                 vin_lvs1-supply = <&pm8018_s3>;
 421
 422                                 vdd_l7-supply = <&pm8018_s4>;
 423                                 vdd_l8-supply = <&pm8018_s3>;
 424                                 vdd_l9_l10_l11_l12-supply = <&pm8018_s5>;
 425
 426                                 /* Buck SMPS */
 427                                 pm8018_s1: s1 {
 428                                         regulator-min-microvolt = <500000>;
 429                                         regulator-max-microvolt = <1150000>;
 430                                         qcom,switch-mode-frequency = <1600000>;
 431                                         bias-pull-down;
 432                                 };
 433
 434                                 pm8018_s2: s2 {
 435                                         regulator-min-microvolt = <1225000>;
 436                                         regulator-max-microvolt = <1300000>;
 437                                         qcom,switch-mode-frequency = <1600000>;
 438                                         bias-pull-down;
 439                                 };
 440
 441                                 pm8018_s3: s3 {
 442                                         regulator-always-on;
 443                                         regulator-min-microvolt = <1800000>;
 444                                         regulator-max-microvolt = <1800000>;
 445                                         qcom,switch-mode-frequency = <1600000>;
 446                                         bias-pull-down;
 447                                 };
 448
 449                                 pm8018_s4: s4 {
 450                                         regulator-min-microvolt = <2100000>;
 451                                         regulator-max-microvolt = <2200000>;
 452                                         qcom,switch-mode-frequency = <1600000>;
 453                                         bias-pull-down;
 454                                 };
 455
 456                                 pm8018_s5: s5 {
 457                                         regulator-always-on;
 458                                         regulator-min-microvolt = <1350000>;
 459                                         regulator-max-microvolt = <1350000>;
 460                                         qcom,switch-mode-frequency = <1600000>;
 461                                         bias-pull-down;
 462                                 };
 463
 464                                 /* PMOS LDO */
 465                                 pm8018_l2: l2 {
 466                                         regulator-always-on;
 467                                         regulator-min-microvolt = <1800000>;
 468                                         regulator-max-microvolt = <1800000>;
 469                                         bias-pull-down;
 470                                 };
 471
 472                                 pm8018_l3: l3 {
 473                                         regulator-always-on;
 474                                         regulator-min-microvolt = <1800000>;
 475                                         regulator-max-microvolt = <1800000>;
 476                                         bias-pull-down;
 477                                 };
 478
 479                                 pm8018_l4: l4 {
 480                                         regulator-min-microvolt = <3300000>;
 481                                         regulator-max-microvolt = <3300000>;
 482                                         bias-pull-down;
 483                                 };
 484
 485                                 pm8018_l5: l5 {
 486                                         regulator-min-microvolt = <2850000>;
 487                                         regulator-max-microvolt = <2850000>;
 488                                         bias-pull-down;
 489                                 };
 490
 491                                 pm8018_l6: l6 {
 492                                         regulator-min-microvolt = <1800000>;
 493                                         regulator-max-microvolt = <2850000>;
 494                                         bias-pull-down;
 495                                 };
 496
 497                                 pm8018_l7: l7 {
 498                                         regulator-min-microvolt = <1850000>;
 499                                         regulator-max-microvolt = <1900000>;
 500                                         bias-pull-down;
 501                                 };
 502
 503                                 pm8018_l8: l8 {
 504                                         regulator-min-microvolt = <1200000>;
 505                                         regulator-max-microvolt = <1200000>;
 506                                         bias-pull-down;
 507                                 };
 508
 509                                 pm8018_l9: l9 {
 510                                         regulator-min-microvolt = <750000>;
 511                                         regulator-max-microvolt = <1150000>;
 512                                         bias-pull-down;
 513                                 };
 514
 515                                 pm8018_l10: l10 {
 516                                         regulator-min-microvolt = <1050000>;
 517                                         regulator-max-microvolt = <1050000>;
 518                                         bias-pull-down;
 519                                 };
 520
 521                                 pm8018_l11: l11 {
 522                                         regulator-min-microvolt = <1050000>;
 523                                         regulator-max-microvolt = <1050000>;
 524                                         bias-pull-down;
 525                                 };
 526
 527                                 pm8018_l12: l12 {
 528                                         regulator-min-microvolt = <1050000>;
 529                                         regulator-max-microvolt = <1050000>;
 530                                         bias-pull-down;
 531                                 };
 532
 533                                 pm8018_l13: l13 {
 534                                         regulator-min-microvolt = <1850000>;
 535                                         regulator-max-microvolt = <2950000>;
 536                                         bias-pull-down;
 537                                 };
 538
 539                                 pm8018_l14: l14 {
 540                                         regulator-min-microvolt = <2850000>;
 541                                         regulator-max-microvolt = <2850000>;
 542                                         bias-pull-down;
 543                                 };
 544
 545                                 /* Low Voltage Switch */
 546                                 pm8018_lvs1: lvs1 {
 547                                         bias-pull-down;
 548                                 };
 549                         };
 550                 };
 551         };
 552 };