arch/arm/boot/dts/qcom-ipq8064.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /dts-v1/;
   3
   4 #include "skeleton.dtsi"
   5 #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
   6 #include <dt-bindings/clock/qcom,lcc-ipq806x.h>
   7 #include <dt-bindings/soc/qcom,gsbi.h>
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9
  10 / {
  11         model = "Qualcomm IPQ8064";
  12         compatible = "qcom,ipq8064";
  13         interrupt-parent = <&intc>;
  14
  15         cpus {
  16                 #address-cells = <1>;
  17                 #size-cells = <0>;
  18
  19                 cpu@0 {
  20                         compatible = "qcom,krait";
  21                         enable-method = "qcom,kpss-acc-v1";
  22                         device_type = "cpu";
  23                         reg = <0>;
  24                         next-level-cache = <&L2>;
  25                         qcom,acc = <&acc0>;
  26                         qcom,saw = <&saw0>;
  27                 };
  28
  29                 cpu@1 {
  30                         compatible = "qcom,krait";
  31                         enable-method = "qcom,kpss-acc-v1";
  32                         device_type = "cpu";
  33                         reg = <1>;
  34                         next-level-cache = <&L2>;
  35                         qcom,acc = <&acc1>;
  36                         qcom,saw = <&saw1>;
  37                 };
  38
  39                 L2: l2-cache {
  40                         compatible = "cache";
  41                         cache-level = <2>;
  42                 };
  43         };
  44
  45         cpu-pmu {
  46                 compatible = "qcom,krait-pmu";
  47                 interrupts = <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
  48                                           IRQ_TYPE_LEVEL_HIGH)>;
  49         };
  50
  51         reserved-memory {
  52                 #address-cells = <1>;
  53                 #size-cells = <1>;
  54                 ranges;
  55
  56                 nss@40000000 {
  57                         reg = <0x40000000 0x1000000>;
  58                         no-map;
  59                 };
  60
  61                 smem@41000000 {
  62                         reg = <0x41000000 0x200000>;
  63                         no-map;
  64                 };
  65         };
  66
  67         clocks {
  68                 cxo_board {
  69                         compatible = "fixed-clock";
  70                         #clock-cells = <0>;
  71                         clock-frequency = <25000000>;
  72                 };
  73
  74                 pxo_board {
  75                         compatible = "fixed-clock";
  76                         #clock-cells = <0>;
  77                         clock-frequency = <25000000>;
  78                 };
  79
  80                 sleep_clk: sleep_clk {
  81                         compatible = "fixed-clock";
  82                         clock-frequency = <32768>;
  83                         #clock-cells = <0>;
  84                 };
  85         };
  86
  87         soc: soc {
  88                 #address-cells = <1>;
  89                 #size-cells = <1>;
  90                 ranges;
  91                 compatible = "simple-bus";
  92
  93                 lpass@28100000 {
  94                         compatible = "qcom,lpass-cpu";
  95                         status = "disabled";
  96                         clocks = <&lcc AHBIX_CLK>,
  97                                         <&lcc MI2S_OSR_CLK>,
  98                                         <&lcc MI2S_BIT_CLK>;
  99                         clock-names = "ahbix-clk",
 100                                         "mi2s-osr-clk",
 101                                         "mi2s-bit-clk";
 102                         interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>;
 103                         interrupt-names = "lpass-irq-lpaif";
 104                         reg = <0x28100000 0x10000>;
 105                         reg-names = "lpass-lpaif";
 106                 };
 107
 108                 qcom_pinmux: pinmux@800000 {
 109                         compatible = "qcom,ipq8064-pinctrl";
 110                         reg = <0x800000 0x4000>;
 111
 112                         gpio-controller;
 113                         #gpio-cells = <2>;
 114                         interrupt-controller;
 115                         #interrupt-cells = <2>;
 116                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 117                 };
 118
 119                 intc: interrupt-controller@2000000 {
 120                         compatible = "qcom,msm-qgic2";
 121                         interrupt-controller;
 122                         #interrupt-cells = <3>;
 123                         reg = <0x02000000 0x1000>,
 124                               <0x02002000 0x1000>;
 125                 };
 126
 127                 timer@200a000 {
 128                         compatible = "qcom,kpss-timer",
 129                                      "qcom,kpss-wdt-ipq8064", "qcom,msm-timer";
 130                         interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(2) |
 131                                                  IRQ_TYPE_EDGE_RISING)>,
 132                                      <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(2) |
 133                                                  IRQ_TYPE_EDGE_RISING)>,
 134                                      <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(2) |
 135                                                  IRQ_TYPE_EDGE_RISING)>,
 136                                      <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(2) |
 137                                                  IRQ_TYPE_EDGE_RISING)>,
 138                                      <GIC_PPI 5 (GIC_CPU_MASK_SIMPLE(2) |
 139                                                  IRQ_TYPE_EDGE_RISING)>;
 140                         reg = <0x0200a000 0x100>;
 141                         clock-frequency = <25000000>,
 142                                           <32768>;
 143                         clocks = <&sleep_clk>;
 144                         clock-names = "sleep";
 145                         cpu-offset = <0x80000>;
 146                 };
 147
 148                 acc0: clock-controller@2088000 {
 149                         compatible = "qcom,kpss-acc-v1";
 150                         reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
 151                 };
 152
 153                 acc1: clock-controller@2098000 {
 154                         compatible = "qcom,kpss-acc-v1";
 155                         reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
 156                 };
 157
 158                 saw0: regulator@2089000 {
 159                         compatible = "qcom,saw2";
 160                         reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
 161                         regulator;
 162                 };
 163
 164                 saw1: regulator@2099000 {
 165                         compatible = "qcom,saw2";
 166                         reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
 167                         regulator;
 168                 };
 169
 170                 gsbi2: gsbi@12480000 {
 171                         compatible = "qcom,gsbi-v1.0.0";
 172                         cell-index = <2>;
 173                         reg = <0x12480000 0x100>;
 174                         clocks = <&gcc GSBI2_H_CLK>;
 175                         clock-names = "iface";
 176                         #address-cells = <1>;
 177                         #size-cells = <1>;
 178                         ranges;
 179                         status = "disabled";
 180
 181                         syscon-tcsr = <&tcsr>;
 182
 183                         serial@12490000 {
 184                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 185                                 reg = <0x12490000 0x1000>,
 186                                       <0x12480000 0x1000>;
 187                                 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
 188                                 clocks = <&gcc GSBI2_UART_CLK>, <&gcc GSBI2_H_CLK>;
 189                                 clock-names = "core", "iface";
 190                                 status = "disabled";
 191                         };
 192
 193                         i2c@124a0000 {
 194                                 compatible = "qcom,i2c-qup-v1.1.1";
 195                                 reg = <0x124a0000 0x1000>;
 196                                 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
 197
 198                                 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
 199                                 clock-names = "core", "iface";
 200                                 status = "disabled";
 201
 202                                 #address-cells = <1>;
 203                                 #size-cells = <0>;
 204                         };
 205
 206                 };
 207
 208                 gsbi4: gsbi@16300000 {
 209                         compatible = "qcom,gsbi-v1.0.0";
 210                         cell-index = <4>;
 211                         reg = <0x16300000 0x100>;
 212                         clocks = <&gcc GSBI4_H_CLK>;
 213                         clock-names = "iface";
 214                         #address-cells = <1>;
 215                         #size-cells = <1>;
 216                         ranges;
 217                         status = "disabled";
 218
 219                         syscon-tcsr = <&tcsr>;
 220
 221                         gsbi4_serial: serial@16340000 {
 222                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 223                                 reg = <0x16340000 0x1000>,
 224                                       <0x16300000 0x1000>;
 225                                 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
 226                                 clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
 227                                 clock-names = "core", "iface";
 228                                 status = "disabled";
 229                         };
 230
 231                         i2c@16380000 {
 232                                 compatible = "qcom,i2c-qup-v1.1.1";
 233                                 reg = <0x16380000 0x1000>;
 234                                 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
 235
 236                                 clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>;
 237                                 clock-names = "core", "iface";
 238                                 status = "disabled";
 239
 240                                 #address-cells = <1>;
 241                                 #size-cells = <0>;
 242                         };
 243                 };
 244
 245                 gsbi5: gsbi@1a200000 {
 246                         compatible = "qcom,gsbi-v1.0.0";
 247                         cell-index = <5>;
 248                         reg = <0x1a200000 0x100>;
 249                         clocks = <&gcc GSBI5_H_CLK>;
 250                         clock-names = "iface";
 251                         #address-cells = <1>;
 252                         #size-cells = <1>;
 253                         ranges;
 254                         status = "disabled";
 255
 256                         syscon-tcsr = <&tcsr>;
 257
 258                         serial@1a240000 {
 259                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 260                                 reg = <0x1a240000 0x1000>,
 261                                       <0x1a200000 0x1000>;
 262                                 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
 263                                 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
 264                                 clock-names = "core", "iface";
 265                                 status = "disabled";
 266                         };
 267
 268                         i2c@1a280000 {
 269                                 compatible = "qcom,i2c-qup-v1.1.1";
 270                                 reg = <0x1a280000 0x1000>;
 271                                 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
 272
 273                                 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
 274                                 clock-names = "core", "iface";
 275                                 status = "disabled";
 276
 277                                 #address-cells = <1>;
 278                                 #size-cells = <0>;
 279                         };
 280
 281                         spi@1a280000 {
 282                                 compatible = "qcom,spi-qup-v1.1.1";
 283                                 reg = <0x1a280000 0x1000>;
 284                                 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
 285
 286                                 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
 287                                 clock-names = "core", "iface";
 288                                 status = "disabled";
 289
 290                                 #address-cells = <1>;
 291                                 #size-cells = <0>;
 292                         };
 293                 };
 294
 295                 gsbi7: gsbi@16600000 {
 296                         status = "disabled";
 297                         compatible = "qcom,gsbi-v1.0.0";
 298                         cell-index = <7>;
 299                         reg = <0x16600000 0x100>;
 300                         clocks = <&gcc GSBI7_H_CLK>;
 301                         clock-names = "iface";
 302                         #address-cells = <1>;
 303                         #size-cells = <1>;
 304                         ranges;
 305                         syscon-tcsr = <&tcsr>;
 306
 307                         gsbi7_serial: serial@16640000 {
 308                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 309                                 reg = <0x16640000 0x1000>,
 310                                       <0x16600000 0x1000>;
 311                                 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
 312                                 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
 313                                 clock-names = "core", "iface";
 314                                 status = "disabled";
 315                         };
 316                 };
 317
 318                 sata_phy: sata-phy@1b400000 {
 319                         compatible = "qcom,ipq806x-sata-phy";
 320                         reg = <0x1b400000 0x200>;
 321
 322                         clocks = <&gcc SATA_PHY_CFG_CLK>;
 323                         clock-names = "cfg";
 324
 325                         #phy-cells = <0>;
 326                         status = "disabled";
 327                 };
 328
 329                 sata@29000000 {
 330                         compatible = "qcom,ipq806x-ahci", "generic-ahci";
 331                         reg = <0x29000000 0x180>;
 332
 333                         interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
 334
 335                         clocks = <&gcc SFAB_SATA_S_H_CLK>,
 336                                  <&gcc SATA_H_CLK>,
 337                                  <&gcc SATA_A_CLK>,
 338                                  <&gcc SATA_RXOOB_CLK>,
 339                                  <&gcc SATA_PMALIVE_CLK>;
 340                         clock-names = "slave_face", "iface", "core",
 341                                         "rxoob", "pmalive";
 342
 343                         assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>;
 344                         assigned-clock-rates = <100000000>, <100000000>;
 345
 346                         phys = <&sata_phy>;
 347                         phy-names = "sata-phy";
 348                         status = "disabled";
 349                 };
 350
 351                 qcom,ssbi@500000 {
 352                         compatible = "qcom,ssbi";
 353                         reg = <0x00500000 0x1000>;
 354                         qcom,controller-type = "pmic-arbiter";
 355                 };
 356
 357                 gcc: clock-controller@900000 {
 358                         compatible = "qcom,gcc-ipq8064";
 359                         reg = <0x00900000 0x4000>;
 360                         #clock-cells = <1>;
 361                         #reset-cells = <1>;
 362                 };
 363
 364                 tcsr: syscon@1a400000 {
 365                         compatible = "qcom,tcsr-ipq8064", "syscon";
 366                         reg = <0x1a400000 0x100>;
 367                 };
 368
 369                 lcc: clock-controller@28000000 {
 370                         compatible = "qcom,lcc-ipq8064";
 371                         reg = <0x28000000 0x1000>;
 372                         #clock-cells = <1>;
 373                         #reset-cells = <1>;
 374                 };
 375
 376         };
 377 };