1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2015, The Linux Foundation. All rights reserved.
8 #include <dt-bindings/clock/qcom,gcc-ipq4019.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
16 model = "Qualcomm Technologies, Inc. IPQ4019";
17 compatible = "qcom,ipq4019";
18 interrupt-parent = <&intc>;
21 #address-cells = <0x1>;
25 smem_region: smem@87e00000 {
26 reg = <0x87e00000 0x080000>;
31 reg = <0x87e80000 0x180000>;
48 compatible = "arm,cortex-a7";
49 enable-method = "qcom,kpss-acc-v2";
50 next-level-cache = <&L2>;
54 clocks = <&gcc GCC_APPS_CLK_SRC>;
55 clock-frequency = <0>;
56 clock-latency = <256000>;
57 operating-points-v2 = <&cpu0_opp_table>;
62 compatible = "arm,cortex-a7";
63 enable-method = "qcom,kpss-acc-v2";
64 next-level-cache = <&L2>;
68 clocks = <&gcc GCC_APPS_CLK_SRC>;
69 clock-frequency = <0>;
70 clock-latency = <256000>;
71 operating-points-v2 = <&cpu0_opp_table>;
76 compatible = "arm,cortex-a7";
77 enable-method = "qcom,kpss-acc-v2";
78 next-level-cache = <&L2>;
82 clocks = <&gcc GCC_APPS_CLK_SRC>;
83 clock-frequency = <0>;
84 clock-latency = <256000>;
85 operating-points-v2 = <&cpu0_opp_table>;
90 compatible = "arm,cortex-a7";
91 enable-method = "qcom,kpss-acc-v2";
92 next-level-cache = <&L2>;
96 clocks = <&gcc GCC_APPS_CLK_SRC>;
97 clock-frequency = <0>;
98 clock-latency = <256000>;
99 operating-points-v2 = <&cpu0_opp_table>;
103 compatible = "cache";
105 qcom,saw = <&saw_l2>;
109 cpu0_opp_table: opp_table0 {
110 compatible = "operating-points-v2";
114 opp-hz = /bits/ 64 <48000000>;
115 clock-latency-ns = <256000>;
118 opp-hz = /bits/ 64 <200000000>;
119 clock-latency-ns = <256000>;
122 opp-hz = /bits/ 64 <500000000>;
123 clock-latency-ns = <256000>;
126 opp-hz = /bits/ 64 <716000000>;
127 clock-latency-ns = <256000>;
132 device_type = "memory";
137 compatible = "arm,cortex-a7-pmu";
138 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) |
139 IRQ_TYPE_LEVEL_HIGH)>;
143 sleep_clk: sleep_clk {
144 compatible = "fixed-clock";
145 clock-frequency = <32000>;
146 clock-output-names = "gcc_sleep_clk_src";
151 compatible = "fixed-clock";
152 clock-frequency = <48000000>;
159 compatible = "qcom,scm-ipq4019", "qcom,scm";
164 compatible = "arm,armv7-timer";
165 interrupts = <1 2 0xf08>,
169 clock-frequency = <48000000>;
174 #address-cells = <1>;
177 compatible = "simple-bus";
179 intc: interrupt-controller@b000000 {
180 compatible = "qcom,msm-qgic2";
181 interrupt-controller;
182 #interrupt-cells = <3>;
183 reg = <0x0b000000 0x1000>,
187 gcc: clock-controller@1800000 {
188 compatible = "qcom,gcc-ipq4019";
190 #power-domain-cells = <1>;
192 reg = <0x1800000 0x60000>;
196 compatible = "qcom,prng";
197 reg = <0x22000 0x140>;
198 clocks = <&gcc GCC_PRNG_AHB_CLK>;
199 clock-names = "core";
203 tlmm: pinctrl@1000000 {
204 compatible = "qcom,ipq4019-pinctrl";
205 reg = <0x01000000 0x300000>;
207 gpio-ranges = <&tlmm 0 0 100>;
209 interrupt-controller;
210 #interrupt-cells = <2>;
211 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
214 vqmmc: regulator@1948000 {
215 compatible = "qcom,vqmmc-ipq4019-regulator";
216 reg = <0x01948000 0x4>;
217 regulator-name = "vqmmc";
218 regulator-min-microvolt = <1500000>;
219 regulator-max-microvolt = <3000000>;
225 compatible = "qcom,sdhci-msm-v4";
226 reg = <0x7824900 0x11c>, <0x7824000 0x800>;
227 reg-names = "hc", "core";
228 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
229 interrupt-names = "hc_irq", "pwr_irq";
231 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
232 <&gcc GCC_SDCC1_APPS_CLK>,
234 clock-names = "iface",
240 blsp_dma: dma-controller@7884000 {
241 compatible = "qcom,bam-v1.7.0";
242 reg = <0x07884000 0x23000>;
243 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
244 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
245 clock-names = "bam_clk";
251 blsp1_spi1: spi@78b5000 { /* BLSP1 QUP1 */
252 compatible = "qcom,spi-qup-v2.2.1";
253 reg = <0x78b5000 0x600>;
254 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
255 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
256 <&gcc GCC_BLSP1_AHB_CLK>;
257 clock-names = "core", "iface";
258 #address-cells = <1>;
260 dmas = <&blsp_dma 4>, <&blsp_dma 5>;
261 dma-names = "tx", "rx";
265 blsp1_spi2: spi@78b6000 { /* BLSP1 QUP2 */
266 compatible = "qcom,spi-qup-v2.2.1";
267 reg = <0x78b6000 0x600>;
268 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
269 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
270 <&gcc GCC_BLSP1_AHB_CLK>;
271 clock-names = "core", "iface";
272 #address-cells = <1>;
274 dmas = <&blsp_dma 6>, <&blsp_dma 7>;
275 dma-names = "tx", "rx";
279 blsp1_i2c3: i2c@78b7000 { /* BLSP1 QUP3 */
280 compatible = "qcom,i2c-qup-v2.2.1";
281 reg = <0x78b7000 0x600>;
282 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
283 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
284 <&gcc GCC_BLSP1_AHB_CLK>;
285 clock-names = "core", "iface";
286 #address-cells = <1>;
288 dmas = <&blsp_dma 8>, <&blsp_dma 9>;
289 dma-names = "tx", "rx";
293 blsp1_i2c4: i2c@78b8000 { /* BLSP1 QUP4 */
294 compatible = "qcom,i2c-qup-v2.2.1";
295 reg = <0x78b8000 0x600>;
296 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
297 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
298 <&gcc GCC_BLSP1_AHB_CLK>;
299 clock-names = "core", "iface";
300 #address-cells = <1>;
302 dmas = <&blsp_dma 10>, <&blsp_dma 11>;
303 dma-names = "tx", "rx";
307 cryptobam: dma-controller@8e04000 {
308 compatible = "qcom,bam-v1.7.0";
309 reg = <0x08e04000 0x20000>;
310 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
311 clocks = <&gcc GCC_CRYPTO_AHB_CLK>;
312 clock-names = "bam_clk";
315 qcom,controlled-remotely;
319 crypto: crypto@8e3a000 {
320 compatible = "qcom,crypto-v5.1";
321 reg = <0x08e3a000 0x6000>;
322 clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
323 <&gcc GCC_CRYPTO_AXI_CLK>,
324 <&gcc GCC_CRYPTO_CLK>;
325 clock-names = "iface", "bus", "core";
326 dmas = <&cryptobam 2>, <&cryptobam 3>;
327 dma-names = "rx", "tx";
331 acc0: clock-controller@b088000 {
332 compatible = "qcom,kpss-acc-v2";
333 reg = <0x0b088000 0x1000>, <0xb008000 0x1000>;
336 acc1: clock-controller@b098000 {
337 compatible = "qcom,kpss-acc-v2";
338 reg = <0x0b098000 0x1000>, <0xb008000 0x1000>;
341 acc2: clock-controller@b0a8000 {
342 compatible = "qcom,kpss-acc-v2";
343 reg = <0x0b0a8000 0x1000>, <0xb008000 0x1000>;
346 acc3: clock-controller@b0b8000 {
347 compatible = "qcom,kpss-acc-v2";
348 reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>;
351 saw0: regulator@b089000 {
352 compatible = "qcom,saw2";
353 reg = <0x0b089000 0x1000>, <0x0b009000 0x1000>;
357 saw1: regulator@b099000 {
358 compatible = "qcom,saw2";
359 reg = <0x0b099000 0x1000>, <0x0b009000 0x1000>;
363 saw2: regulator@b0a9000 {
364 compatible = "qcom,saw2";
365 reg = <0x0b0a9000 0x1000>, <0x0b009000 0x1000>;
369 saw3: regulator@b0b9000 {
370 compatible = "qcom,saw2";
371 reg = <0x0b0b9000 0x1000>, <0x0b009000 0x1000>;
375 saw_l2: regulator@b012000 {
376 compatible = "qcom,saw2";
377 reg = <0xb012000 0x1000>;
381 blsp1_uart1: serial@78af000 {
382 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
383 reg = <0x78af000 0x200>;
384 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
386 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
387 <&gcc GCC_BLSP1_AHB_CLK>;
388 clock-names = "core", "iface";
389 dmas = <&blsp_dma 0>, <&blsp_dma 1>;
390 dma-names = "tx", "rx";
393 blsp1_uart2: serial@78b0000 {
394 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
395 reg = <0x78b0000 0x200>;
396 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
398 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
399 <&gcc GCC_BLSP1_AHB_CLK>;
400 clock-names = "core", "iface";
401 dmas = <&blsp_dma 2>, <&blsp_dma 3>;
402 dma-names = "tx", "rx";
405 watchdog: watchdog@b017000 {
406 compatible = "qcom,kpss-wdt", "qcom,kpss-wdt-ipq4019";
407 reg = <0xb017000 0x40>;
408 clocks = <&sleep_clk>;
414 compatible = "qcom,pshold";
415 reg = <0x4ab000 0x4>;
418 pcie0: pci@40000000 {
419 compatible = "qcom,pcie-ipq4019";
420 reg = <0x40000000 0xf1d
424 reg-names = "dbi", "elbi", "parf", "config";
426 linux,pci-domain = <0>;
427 bus-range = <0x00 0xff>;
429 #address-cells = <3>;
432 ranges = <0x81000000 0x0 0x00000000 0x40200000 0x0 0x00100000>,
433 <0x82000000 0x0 0x40300000 0x40300000 0x0 0x00d00000>;
435 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
436 interrupt-names = "msi";
437 #interrupt-cells = <1>;
438 interrupt-map-mask = <0 0 0 0x7>;
439 interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
440 <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
441 <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
442 <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
443 clocks = <&gcc GCC_PCIE_AHB_CLK>,
444 <&gcc GCC_PCIE_AXI_M_CLK>,
445 <&gcc GCC_PCIE_AXI_S_CLK>;
450 resets = <&gcc PCIE_AXI_M_ARES>,
451 <&gcc PCIE_AXI_S_ARES>,
452 <&gcc PCIE_PIPE_ARES>,
453 <&gcc PCIE_AXI_M_VMIDMT_ARES>,
454 <&gcc PCIE_AXI_S_XPU_ARES>,
455 <&gcc PCIE_PARF_XPU_ARES>,
456 <&gcc PCIE_PHY_ARES>,
457 <&gcc PCIE_AXI_M_STICKY_ARES>,
458 <&gcc PCIE_PIPE_STICKY_ARES>,
459 <&gcc PCIE_PWR_ARES>,
460 <&gcc PCIE_AHB_ARES>,
461 <&gcc PCIE_PHY_AHB_ARES>;
462 reset-names = "axi_m",
478 qpic_bam: dma-controller@7984000 {
479 compatible = "qcom,bam-v1.7.0";
480 reg = <0x7984000 0x1a000>;
481 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
482 clocks = <&gcc GCC_QPIC_CLK>;
483 clock-names = "bam_clk";
489 nand: nand-controller@79b0000 {
490 compatible = "qcom,ipq4019-nand";
491 reg = <0x79b0000 0x1000>;
492 #address-cells = <1>;
494 clocks = <&gcc GCC_QPIC_CLK>,
495 <&gcc GCC_QPIC_AHB_CLK>;
496 clock-names = "core", "aon";
498 dmas = <&qpic_bam 0>,
501 dma-names = "tx", "rx", "cmd";
507 nand-ecc-strength = <4>;
508 nand-ecc-step-size = <512>;
509 nand-bus-width = <8>;
513 wifi0: wifi@a000000 {
514 compatible = "qcom,ipq4019-wifi";
515 reg = <0xa000000 0x200000>;
516 resets = <&gcc WIFI0_CPU_INIT_RESET>,
517 <&gcc WIFI0_RADIO_SRIF_RESET>,
518 <&gcc WIFI0_RADIO_WARM_RESET>,
519 <&gcc WIFI0_RADIO_COLD_RESET>,
520 <&gcc WIFI0_CORE_WARM_RESET>,
521 <&gcc WIFI0_CORE_COLD_RESET>;
522 reset-names = "wifi_cpu_init", "wifi_radio_srif",
523 "wifi_radio_warm", "wifi_radio_cold",
524 "wifi_core_warm", "wifi_core_cold";
525 clocks = <&gcc GCC_WCSS2G_CLK>,
526 <&gcc GCC_WCSS2G_REF_CLK>,
527 <&gcc GCC_WCSS2G_RTC_CLK>;
528 clock-names = "wifi_wcss_cmd", "wifi_wcss_ref",
530 interrupts = <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>,
531 <GIC_SPI 33 IRQ_TYPE_EDGE_RISING>,
532 <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>,
533 <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
534 <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
535 <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>,
536 <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>,
537 <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>,
538 <GIC_SPI 40 IRQ_TYPE_EDGE_RISING>,
539 <GIC_SPI 41 IRQ_TYPE_EDGE_RISING>,
540 <GIC_SPI 42 IRQ_TYPE_EDGE_RISING>,
541 <GIC_SPI 43 IRQ_TYPE_EDGE_RISING>,
542 <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>,
543 <GIC_SPI 45 IRQ_TYPE_EDGE_RISING>,
544 <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>,
545 <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>,
546 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
547 interrupt-names = "msi0", "msi1", "msi2", "msi3",
548 "msi4", "msi5", "msi6", "msi7",
549 "msi8", "msi9", "msi10", "msi11",
550 "msi12", "msi13", "msi14", "msi15",
555 wifi1: wifi@a800000 {
556 compatible = "qcom,ipq4019-wifi";
557 reg = <0xa800000 0x200000>;
558 resets = <&gcc WIFI1_CPU_INIT_RESET>,
559 <&gcc WIFI1_RADIO_SRIF_RESET>,
560 <&gcc WIFI1_RADIO_WARM_RESET>,
561 <&gcc WIFI1_RADIO_COLD_RESET>,
562 <&gcc WIFI1_CORE_WARM_RESET>,
563 <&gcc WIFI1_CORE_COLD_RESET>;
564 reset-names = "wifi_cpu_init", "wifi_radio_srif",
565 "wifi_radio_warm", "wifi_radio_cold",
566 "wifi_core_warm", "wifi_core_cold";
567 clocks = <&gcc GCC_WCSS5G_CLK>,
568 <&gcc GCC_WCSS5G_REF_CLK>,
569 <&gcc GCC_WCSS5G_RTC_CLK>;
570 clock-names = "wifi_wcss_cmd", "wifi_wcss_ref",
572 interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>,
573 <GIC_SPI 49 IRQ_TYPE_EDGE_RISING>,
574 <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>,
575 <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>,
576 <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>,
577 <GIC_SPI 53 IRQ_TYPE_EDGE_RISING>,
578 <GIC_SPI 54 IRQ_TYPE_EDGE_RISING>,
579 <GIC_SPI 55 IRQ_TYPE_EDGE_RISING>,
580 <GIC_SPI 56 IRQ_TYPE_EDGE_RISING>,
581 <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>,
582 <GIC_SPI 58 IRQ_TYPE_EDGE_RISING>,
583 <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>,
584 <GIC_SPI 60 IRQ_TYPE_EDGE_RISING>,
585 <GIC_SPI 61 IRQ_TYPE_EDGE_RISING>,
586 <GIC_SPI 62 IRQ_TYPE_EDGE_RISING>,
587 <GIC_SPI 63 IRQ_TYPE_EDGE_RISING>,
588 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
589 interrupt-names = "msi0", "msi1", "msi2", "msi3",
590 "msi4", "msi5", "msi6", "msi7",
591 "msi8", "msi9", "msi10", "msi11",
592 "msi12", "msi13", "msi14", "msi15",
598 #address-cells = <1>;
600 compatible = "qcom,ipq4019-mdio";
601 reg = <0x90000 0x64>;
604 ethphy0: ethernet-phy@0 {
608 ethphy1: ethernet-phy@1 {
612 ethphy2: ethernet-phy@2 {
616 ethphy3: ethernet-phy@3 {
620 ethphy4: ethernet-phy@4 {
625 usb3_ss_phy: ssphy@9a000 {
626 compatible = "qcom,usb-ss-ipq4019-phy";
628 reg = <0x9a000 0x800>;
629 reg-names = "phy_base";
630 resets = <&gcc USB3_UNIPHY_PHY_ARES>;
631 reset-names = "por_rst";
635 usb3_hs_phy: hsphy@a6000 {
636 compatible = "qcom,usb-hs-ipq4019-phy";
638 reg = <0xa6000 0x40>;
639 reg-names = "phy_base";
640 resets = <&gcc USB3_HSPHY_POR_ARES>, <&gcc USB3_HSPHY_S_ARES>;
641 reset-names = "por_rst", "srif_rst";
646 compatible = "qcom,ipq4019-dwc3", "qcom,dwc3";
647 reg = <0x8af8800 0x100>;
648 #address-cells = <1>;
650 clocks = <&gcc GCC_USB3_MASTER_CLK>,
651 <&gcc GCC_USB3_SLEEP_CLK>,
652 <&gcc GCC_USB3_MOCK_UTMI_CLK>;
653 clock-names = "core", "sleep", "mock_utmi";
658 compatible = "snps,dwc3";
659 reg = <0x8a00000 0xf8000>;
660 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
661 phys = <&usb3_hs_phy>, <&usb3_ss_phy>;
662 phy-names = "usb2-phy", "usb3-phy";
667 usb2_hs_phy: hsphy@a8000 {
668 compatible = "qcom,usb-hs-ipq4019-phy";
670 reg = <0xa8000 0x40>;
671 reg-names = "phy_base";
672 resets = <&gcc USB2_HSPHY_POR_ARES>, <&gcc USB2_HSPHY_S_ARES>;
673 reset-names = "por_rst", "srif_rst";
678 compatible = "qcom,ipq4019-dwc3", "qcom,dwc3";
679 reg = <0x60f8800 0x100>;
680 #address-cells = <1>;
682 clocks = <&gcc GCC_USB2_MASTER_CLK>,
683 <&gcc GCC_USB2_SLEEP_CLK>,
684 <&gcc GCC_USB2_MOCK_UTMI_CLK>;
685 clock-names = "master", "sleep", "mock_utmi";
690 compatible = "snps,dwc3";
691 reg = <0x6000000 0xf8000>;
692 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
693 phys = <&usb2_hs_phy>;
694 phy-names = "usb2-phy";