arch/arm/boot/dts/qcom-ipq4019.dtsi

   1 /*
   2  * Copyright (c) 2015, The Linux Foundation. All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 and
   6  * only version 2 as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 /dts-v1/;
  15
  16 #include "skeleton.dtsi"
  17 #include <dt-bindings/clock/qcom,gcc-ipq4019.h>
  18 #include <dt-bindings/interrupt-controller/arm-gic.h>
  19 #include <dt-bindings/interrupt-controller/irq.h>
  20
  21 / {
  22         model = "Qualcomm Technologies, Inc. IPQ4019";
  23         compatible = "qcom,ipq4019";
  24         interrupt-parent = <&intc>;
  25
  26         aliases {
  27                 spi0 = &spi_0;
  28                 i2c0 = &i2c_0;
  29         };
  30
  31         cpus {
  32                 #address-cells = <1>;
  33                 #size-cells = <0>;
  34                 cpu@0 {
  35                         device_type = "cpu";
  36                         compatible = "arm,cortex-a7";
  37                         enable-method = "qcom,kpss-acc-v1";
  38                         qcom,acc = <&acc0>;
  39                         qcom,saw = <&saw0>;
  40                         reg = <0x0>;
  41                         clocks = <&gcc GCC_APPS_CLK_SRC>;
  42                         clock-frequency = <0>;
  43                         operating-points = <
  44                                 /* kHz  uV (fixed) */
  45                                 48000   1100000
  46                                 200000  1100000
  47                                 500000  1100000
  48                                 666000  1100000
  49                         >;
  50                         clock-latency = <256000>;
  51                 };
  52
  53                 cpu@1 {
  54                         device_type = "cpu";
  55                         compatible = "arm,cortex-a7";
  56                         enable-method = "qcom,kpss-acc-v1";
  57                         qcom,acc = <&acc1>;
  58                         qcom,saw = <&saw1>;
  59                         reg = <0x1>;
  60                         clocks = <&gcc GCC_APPS_CLK_SRC>;
  61                         clock-frequency = <0>;
  62                 };
  63
  64                 cpu@2 {
  65                         device_type = "cpu";
  66                         compatible = "arm,cortex-a7";
  67                         enable-method = "qcom,kpss-acc-v1";
  68                         qcom,acc = <&acc2>;
  69                         qcom,saw = <&saw2>;
  70                         reg = <0x2>;
  71                         clocks = <&gcc GCC_APPS_CLK_SRC>;
  72                         clock-frequency = <0>;
  73                 };
  74
  75                 cpu@3 {
  76                         device_type = "cpu";
  77                         compatible = "arm,cortex-a7";
  78                         enable-method = "qcom,kpss-acc-v1";
  79                         qcom,acc = <&acc3>;
  80                         qcom,saw = <&saw3>;
  81                         reg = <0x3>;
  82                         clocks = <&gcc GCC_APPS_CLK_SRC>;
  83                         clock-frequency = <0>;
  84                 };
  85         };
  86
  87         pmu {
  88                 compatible = "arm,cortex-a7-pmu";
  89                 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) |
  90                                          IRQ_TYPE_LEVEL_HIGH)>;
  91         };
  92
  93         clocks {
  94                 sleep_clk: sleep_clk {
  95                         compatible = "fixed-clock";
  96                         clock-frequency = <32000>;
  97                         clock-output-names = "gcc_sleep_clk_src";
  98                         #clock-cells = <0>;
  99                 };
 100
 101                 xo: xo {
 102                         compatible = "fixed-clock";
 103                         clock-frequency = <48000000>;
 104                         #clock-cells = <0>;
 105                 };
 106         };
 107
 108         timer {
 109                 compatible = "arm,armv7-timer";
 110                 interrupts = <1 2 0xf08>,
 111                              <1 3 0xf08>,
 112                              <1 4 0xf08>,
 113                              <1 1 0xf08>;
 114                 clock-frequency = <48000000>;
 115         };
 116
 117         soc {
 118                 #address-cells = <1>;
 119                 #size-cells = <1>;
 120                 ranges;
 121                 compatible = "simple-bus";
 122
 123                 intc: interrupt-controller@b000000 {
 124                         compatible = "qcom,msm-qgic2";
 125                         interrupt-controller;
 126                         #interrupt-cells = <3>;
 127                         reg = <0x0b000000 0x1000>,
 128                         <0x0b002000 0x1000>;
 129                 };
 130
 131                 gcc: clock-controller@1800000 {
 132                         compatible = "qcom,gcc-ipq4019";
 133                         #clock-cells = <1>;
 134                         #reset-cells = <1>;
 135                         reg = <0x1800000 0x60000>;
 136                 };
 137
 138                 rng@22000 {
 139                         compatible = "qcom,prng";
 140                         reg = <0x22000 0x140>;
 141                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
 142                         clock-names = "core";
 143                         status = "disabled";
 144                 };
 145
 146                 tlmm: pinctrl@1000000 {
 147                         compatible = "qcom,ipq4019-pinctrl";
 148                         reg = <0x01000000 0x300000>;
 149                         gpio-controller;
 150                         #gpio-cells = <2>;
 151                         interrupt-controller;
 152                         #interrupt-cells = <2>;
 153                         interrupts = <0 208 0>;
 154                 };
 155
 156                 blsp_dma: dma@7884000 {
 157                         compatible = "qcom,bam-v1.7.0";
 158                         reg = <0x07884000 0x23000>;
 159                         interrupts = <GIC_SPI 238 IRQ_TYPE_NONE>;
 160                         clocks = <&gcc GCC_BLSP1_AHB_CLK>;
 161                         clock-names = "bam_clk";
 162                         #dma-cells = <1>;
 163                         qcom,ee = <0>;
 164                         status = "disabled";
 165                 };
 166
 167                 spi_0: spi@78b5000 {
 168                         compatible = "qcom,spi-qup-v2.2.1";
 169                         reg = <0x78b5000 0x600>;
 170                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 171                         clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
 172                                  <&gcc GCC_BLSP1_AHB_CLK>;
 173                         clock-names = "core", "iface";
 174                         #address-cells = <1>;
 175                         #size-cells = <0>;
 176                         status = "disabled";
 177                 };
 178
 179                 i2c_0: i2c@78b7000 {
 180                         compatible = "qcom,i2c-qup-v2.2.1";
 181                         reg = <0x78b7000 0x600>;
 182                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 183                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 184                                  <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>;
 185                         clock-names = "iface", "core";
 186                         #address-cells = <1>;
 187                         #size-cells = <0>;
 188                         status = "disabled";
 189                 };
 190
 191
 192                 cryptobam: dma@8e04000 {
 193                         compatible = "qcom,bam-v1.7.0";
 194                         reg = <0x08e04000 0x20000>;
 195                         interrupts = <GIC_SPI 207 0>;
 196                         clocks = <&gcc GCC_CRYPTO_AHB_CLK>;
 197                         clock-names = "bam_clk";
 198                         #dma-cells = <1>;
 199                         qcom,ee = <1>;
 200                         qcom,controlled-remotely;
 201                         status = "disabled";
 202                 };
 203
 204                 crypto@8e3a000 {
 205                         compatible = "qcom,crypto-v5.1";
 206                         reg = <0x08e3a000 0x6000>;
 207                         clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
 208                                  <&gcc GCC_CRYPTO_AXI_CLK>,
 209                                  <&gcc GCC_CRYPTO_CLK>;
 210                         clock-names = "iface", "bus", "core";
 211                         dmas = <&cryptobam 2>, <&cryptobam 3>;
 212                         dma-names = "rx", "tx";
 213                         status = "disabled";
 214                 };
 215
 216                 acc0: clock-controller@b088000 {
 217                         compatible = "qcom,kpss-acc-v1";
 218                         reg = <0x0b088000 0x1000>, <0xb008000 0x1000>;
 219                 };
 220
 221                 acc1: clock-controller@b098000 {
 222                         compatible = "qcom,kpss-acc-v1";
 223                         reg = <0x0b098000 0x1000>, <0xb008000 0x1000>;
 224                 };
 225
 226                 acc2: clock-controller@b0a8000 {
 227                         compatible = "qcom,kpss-acc-v1";
 228                         reg = <0x0b0a8000 0x1000>, <0xb008000 0x1000>;
 229                 };
 230
 231                 acc3: clock-controller@b0b8000 {
 232                         compatible = "qcom,kpss-acc-v1";
 233                         reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>;
 234                 };
 235
 236                 saw0: regulator@b089000 {
 237                         compatible = "qcom,saw2";
 238                         reg = <0x0b089000 0x1000>, <0x0b009000 0x1000>;
 239                         regulator;
 240                 };
 241
 242                 saw1: regulator@b099000 {
 243                         compatible = "qcom,saw2";
 244                         reg = <0x0b099000 0x1000>, <0x0b009000 0x1000>;
 245                         regulator;
 246                 };
 247
 248                 saw2: regulator@b0a9000 {
 249                         compatible = "qcom,saw2";
 250                         reg = <0x0b0a9000 0x1000>, <0x0b009000 0x1000>;
 251                         regulator;
 252                 };
 253
 254                 saw3: regulator@b0b9000 {
 255                         compatible = "qcom,saw2";
 256                         reg = <0x0b0b9000 0x1000>, <0x0b009000 0x1000>;
 257                         regulator;
 258                 };
 259
 260                 serial@78af000 {
 261                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 262                         reg = <0x78af000 0x200>;
 263                         interrupts = <0 107 0>;
 264                         status = "disabled";
 265                         clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
 266                                 <&gcc GCC_BLSP1_AHB_CLK>;
 267                         clock-names = "core", "iface";
 268                         dmas = <&blsp_dma 1>, <&blsp_dma 0>;
 269                         dma-names = "rx", "tx";
 270                 };
 271
 272                 serial@78b0000 {
 273                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 274                         reg = <0x78b0000 0x200>;
 275                         interrupts = <0 108 0>;
 276                         status = "disabled";
 277                         clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
 278                                 <&gcc GCC_BLSP1_AHB_CLK>;
 279                         clock-names = "core", "iface";
 280                         dmas = <&blsp_dma 3>, <&blsp_dma 2>;
 281                         dma-names = "rx", "tx";
 282                 };
 283
 284                 watchdog@b017000 {
 285                         compatible = "qcom,kpss-wdt", "qcom,kpss-wdt-ipq4019";
 286                         reg = <0xb017000 0x40>;
 287                         clocks = <&sleep_clk>;
 288                         timeout-sec = <10>;
 289                         status = "disabled";
 290                 };
 291
 292                 restart@4ab000 {
 293                         compatible = "qcom,pshold";
 294                         reg = <0x4ab000 0x4>;
 295                 };
 296
 297                 wifi0: wifi@a000000 {
 298                         compatible = "qcom,ipq4019-wifi";
 299                         reg = <0xa000000 0x200000>;
 300                         resets = <&gcc WIFI0_CPU_INIT_RESET>,
 301                                  <&gcc WIFI0_RADIO_SRIF_RESET>,
 302                                  <&gcc WIFI0_RADIO_WARM_RESET>,
 303                                  <&gcc WIFI0_RADIO_COLD_RESET>,
 304                                  <&gcc WIFI0_CORE_WARM_RESET>,
 305                                  <&gcc WIFI0_CORE_COLD_RESET>;
 306                         reset-names = "wifi_cpu_init", "wifi_radio_srif",
 307                                       "wifi_radio_warm", "wifi_radio_cold",
 308                                       "wifi_core_warm", "wifi_core_cold";
 309                         clocks = <&gcc GCC_WCSS2G_CLK>,
 310                                  <&gcc GCC_WCSS2G_REF_CLK>,
 311                                  <&gcc GCC_WCSS2G_RTC_CLK>;
 312                         clock-names = "wifi_wcss_cmd", "wifi_wcss_ref",
 313                                       "wifi_wcss_rtc";
 314                         interrupts = <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>,
 315                                      <GIC_SPI 33 IRQ_TYPE_EDGE_RISING>,
 316                                      <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>,
 317                                      <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
 318                                      <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
 319                                      <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>,
 320                                      <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>,
 321                                      <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>,
 322                                      <GIC_SPI 40 IRQ_TYPE_EDGE_RISING>,
 323                                      <GIC_SPI 41 IRQ_TYPE_EDGE_RISING>,
 324                                      <GIC_SPI 42 IRQ_TYPE_EDGE_RISING>,
 325                                      <GIC_SPI 43 IRQ_TYPE_EDGE_RISING>,
 326                                      <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>,
 327                                      <GIC_SPI 45 IRQ_TYPE_EDGE_RISING>,
 328                                      <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>,
 329                                      <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>,
 330                                      <GIC_SPI 168 IRQ_TYPE_NONE>;
 331                         interrupt-names =  "msi0",  "msi1",  "msi2",  "msi3",
 332                                            "msi4",  "msi5",  "msi6",  "msi7",
 333                                            "msi8",  "msi9", "msi10", "msi11",
 334                                           "msi12", "msi13", "msi14", "msi15",
 335                                           "legacy";
 336                         status = "disabled";
 337                 };
 338
 339                 wifi1: wifi@a800000 {
 340                         compatible = "qcom,ipq4019-wifi";
 341                         reg = <0xa800000 0x200000>;
 342                         resets = <&gcc WIFI1_CPU_INIT_RESET>,
 343                                  <&gcc WIFI1_RADIO_SRIF_RESET>,
 344                                  <&gcc WIFI1_RADIO_WARM_RESET>,
 345                                  <&gcc WIFI1_RADIO_COLD_RESET>,
 346                                  <&gcc WIFI1_CORE_WARM_RESET>,
 347                                  <&gcc WIFI1_CORE_COLD_RESET>;
 348                         reset-names = "wifi_cpu_init", "wifi_radio_srif",
 349                                       "wifi_radio_warm", "wifi_radio_cold",
 350                                       "wifi_core_warm", "wifi_core_cold";
 351                         clocks = <&gcc GCC_WCSS5G_CLK>,
 352                                  <&gcc GCC_WCSS5G_REF_CLK>,
 353                                  <&gcc GCC_WCSS5G_RTC_CLK>;
 354                         clock-names = "wifi_wcss_cmd", "wifi_wcss_ref",
 355                                       "wifi_wcss_rtc";
 356                         interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>,
 357                                      <GIC_SPI 49 IRQ_TYPE_EDGE_RISING>,
 358                                      <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>,
 359                                      <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>,
 360                                      <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>,
 361                                      <GIC_SPI 53 IRQ_TYPE_EDGE_RISING>,
 362                                      <GIC_SPI 54 IRQ_TYPE_EDGE_RISING>,
 363                                      <GIC_SPI 55 IRQ_TYPE_EDGE_RISING>,
 364                                      <GIC_SPI 56 IRQ_TYPE_EDGE_RISING>,
 365                                      <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>,
 366                                      <GIC_SPI 58 IRQ_TYPE_EDGE_RISING>,
 367                                      <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>,
 368                                      <GIC_SPI 60 IRQ_TYPE_EDGE_RISING>,
 369                                      <GIC_SPI 61 IRQ_TYPE_EDGE_RISING>,
 370                                      <GIC_SPI 62 IRQ_TYPE_EDGE_RISING>,
 371                                      <GIC_SPI 63 IRQ_TYPE_EDGE_RISING>,
 372                                      <GIC_SPI 169 IRQ_TYPE_NONE>;
 373                         interrupt-names =  "msi0",  "msi1",  "msi2",  "msi3",
 374                                            "msi4",  "msi5",  "msi6",  "msi7",
 375                                            "msi8",  "msi9", "msi10", "msi11",
 376                                           "msi12", "msi13", "msi14", "msi15",
 377                                           "legacy";
 378                         status = "disabled";
 379                 };
 380         };
 381 };