2 * Copyright (c) 2015, The Linux Foundation. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
16 #include "skeleton.dtsi"
17 #include <dt-bindings/clock/qcom,gcc-ipq4019.h>
18 #include <dt-bindings/interrupt-controller/arm-gic.h>
19 #include <dt-bindings/interrupt-controller/irq.h>
22 model = "Qualcomm Technologies, Inc. IPQ4019";
23 compatible = "qcom,ipq4019";
24 interrupt-parent = <&intc>;
27 #address-cells = <0x1>;
31 smem_region: smem@87e00000 {
32 reg = <0x87e00000 0x080000>;
37 reg = <0x87e80000 0x180000>;
54 compatible = "arm,cortex-a7";
55 enable-method = "qcom,kpss-acc-v1";
59 clocks = <&gcc GCC_APPS_CLK_SRC>;
60 clock-frequency = <0>;
68 clock-latency = <256000>;
73 compatible = "arm,cortex-a7";
74 enable-method = "qcom,kpss-acc-v1";
78 clocks = <&gcc GCC_APPS_CLK_SRC>;
79 clock-frequency = <0>;
87 clock-latency = <256000>;
92 compatible = "arm,cortex-a7";
93 enable-method = "qcom,kpss-acc-v1";
97 clocks = <&gcc GCC_APPS_CLK_SRC>;
98 clock-frequency = <0>;
106 clock-latency = <256000>;
111 compatible = "arm,cortex-a7";
112 enable-method = "qcom,kpss-acc-v1";
116 clocks = <&gcc GCC_APPS_CLK_SRC>;
117 clock-frequency = <0>;
125 clock-latency = <256000>;
130 compatible = "arm,cortex-a7-pmu";
131 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) |
132 IRQ_TYPE_LEVEL_HIGH)>;
136 sleep_clk: sleep_clk {
137 compatible = "fixed-clock";
138 clock-frequency = <32000>;
139 clock-output-names = "gcc_sleep_clk_src";
144 compatible = "fixed-clock";
145 clock-frequency = <48000000>;
152 compatible = "qcom,scm-ipq4019";
157 compatible = "arm,armv7-timer";
158 interrupts = <1 2 0xf08>,
162 clock-frequency = <48000000>;
166 #address-cells = <1>;
169 compatible = "simple-bus";
171 intc: interrupt-controller@b000000 {
172 compatible = "qcom,msm-qgic2";
173 interrupt-controller;
174 #interrupt-cells = <3>;
175 reg = <0x0b000000 0x1000>,
179 gcc: clock-controller@1800000 {
180 compatible = "qcom,gcc-ipq4019";
183 reg = <0x1800000 0x60000>;
187 compatible = "qcom,prng";
188 reg = <0x22000 0x140>;
189 clocks = <&gcc GCC_PRNG_AHB_CLK>;
190 clock-names = "core";
194 tlmm: pinctrl@1000000 {
195 compatible = "qcom,ipq4019-pinctrl";
196 reg = <0x01000000 0x300000>;
199 interrupt-controller;
200 #interrupt-cells = <2>;
201 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
204 blsp_dma: dma@7884000 {
205 compatible = "qcom,bam-v1.7.0";
206 reg = <0x07884000 0x23000>;
207 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
208 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
209 clock-names = "bam_clk";
215 blsp1_spi1: spi@78b5000 { /* BLSP1 QUP1 */
216 compatible = "qcom,spi-qup-v2.2.1";
217 reg = <0x78b5000 0x600>;
218 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
219 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
220 <&gcc GCC_BLSP1_AHB_CLK>;
221 clock-names = "core", "iface";
222 #address-cells = <1>;
224 dmas = <&blsp_dma 5>, <&blsp_dma 4>;
225 dma-names = "rx", "tx";
229 blsp1_spi2: spi@78b6000 { /* BLSP1 QUP2 */
230 compatible = "qcom,spi-qup-v2.2.1";
231 reg = <0x78b6000 0x600>;
232 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
233 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
234 <&gcc GCC_BLSP1_AHB_CLK>;
235 clock-names = "core", "iface";
236 #address-cells = <1>;
238 dmas = <&blsp_dma 7>, <&blsp_dma 6>;
239 dma-names = "rx", "tx";
243 blsp1_i2c3: i2c@78b7000 { /* BLSP1 QUP3 */
244 compatible = "qcom,i2c-qup-v2.2.1";
245 reg = <0x78b7000 0x600>;
246 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
247 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
248 <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>;
249 clock-names = "iface", "core";
250 #address-cells = <1>;
252 dmas = <&blsp_dma 9>, <&blsp_dma 8>;
253 dma-names = "rx", "tx";
257 blsp1_i2c4: i2c@78b8000 { /* BLSP1 QUP4 */
258 compatible = "qcom,i2c-qup-v2.2.1";
259 reg = <0x78b8000 0x600>;
260 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
261 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
262 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
263 clock-names = "iface", "core";
264 #address-cells = <1>;
266 dmas = <&blsp_dma 11>, <&blsp_dma 10>;
267 dma-names = "rx", "tx";
271 cryptobam: dma@8e04000 {
272 compatible = "qcom,bam-v1.7.0";
273 reg = <0x08e04000 0x20000>;
274 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
275 clocks = <&gcc GCC_CRYPTO_AHB_CLK>;
276 clock-names = "bam_clk";
279 qcom,controlled-remotely;
284 compatible = "qcom,crypto-v5.1";
285 reg = <0x08e3a000 0x6000>;
286 clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
287 <&gcc GCC_CRYPTO_AXI_CLK>,
288 <&gcc GCC_CRYPTO_CLK>;
289 clock-names = "iface", "bus", "core";
290 dmas = <&cryptobam 2>, <&cryptobam 3>;
291 dma-names = "rx", "tx";
295 acc0: clock-controller@b088000 {
296 compatible = "qcom,kpss-acc-v1";
297 reg = <0x0b088000 0x1000>, <0xb008000 0x1000>;
300 acc1: clock-controller@b098000 {
301 compatible = "qcom,kpss-acc-v1";
302 reg = <0x0b098000 0x1000>, <0xb008000 0x1000>;
305 acc2: clock-controller@b0a8000 {
306 compatible = "qcom,kpss-acc-v1";
307 reg = <0x0b0a8000 0x1000>, <0xb008000 0x1000>;
310 acc3: clock-controller@b0b8000 {
311 compatible = "qcom,kpss-acc-v1";
312 reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>;
315 saw0: regulator@b089000 {
316 compatible = "qcom,saw2";
317 reg = <0x0b089000 0x1000>, <0x0b009000 0x1000>;
321 saw1: regulator@b099000 {
322 compatible = "qcom,saw2";
323 reg = <0x0b099000 0x1000>, <0x0b009000 0x1000>;
327 saw2: regulator@b0a9000 {
328 compatible = "qcom,saw2";
329 reg = <0x0b0a9000 0x1000>, <0x0b009000 0x1000>;
333 saw3: regulator@b0b9000 {
334 compatible = "qcom,saw2";
335 reg = <0x0b0b9000 0x1000>, <0x0b009000 0x1000>;
339 blsp1_uart1: serial@78af000 {
340 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
341 reg = <0x78af000 0x200>;
342 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
344 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
345 <&gcc GCC_BLSP1_AHB_CLK>;
346 clock-names = "core", "iface";
347 dmas = <&blsp_dma 1>, <&blsp_dma 0>;
348 dma-names = "rx", "tx";
351 blsp1_uart2: serial@78b0000 {
352 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
353 reg = <0x78b0000 0x200>;
354 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
356 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
357 <&gcc GCC_BLSP1_AHB_CLK>;
358 clock-names = "core", "iface";
359 dmas = <&blsp_dma 3>, <&blsp_dma 2>;
360 dma-names = "rx", "tx";
364 compatible = "qcom,kpss-wdt", "qcom,kpss-wdt-ipq4019";
365 reg = <0xb017000 0x40>;
366 clocks = <&sleep_clk>;
372 compatible = "qcom,pshold";
373 reg = <0x4ab000 0x4>;
376 pcie0: pci@40000000 {
377 compatible = "qcom,pcie-ipq4019", "snps,dw-pcie";
378 reg = <0x40000000 0xf1d
382 reg-names = "dbi", "elbi", "parf", "config";
384 linux,pci-domain = <0>;
385 bus-range = <0x00 0xff>;
387 #address-cells = <3>;
390 ranges = <0x81000000 0 0x40200000 0x40200000 0 0x00100000>,
391 <0x82000000 0 0x40300000 0x40300000 0 0x00d00000>;
393 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
394 interrupt-names = "msi";
395 #interrupt-cells = <1>;
396 interrupt-map-mask = <0 0 0 0x7>;
397 interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
398 <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
399 <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
400 <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
401 clocks = <&gcc GCC_PCIE_AHB_CLK>,
402 <&gcc GCC_PCIE_AXI_M_CLK>,
403 <&gcc GCC_PCIE_AXI_S_CLK>;
408 resets = <&gcc PCIE_AXI_M_ARES>,
409 <&gcc PCIE_AXI_S_ARES>,
410 <&gcc PCIE_PIPE_ARES>,
411 <&gcc PCIE_AXI_M_VMIDMT_ARES>,
412 <&gcc PCIE_AXI_S_XPU_ARES>,
413 <&gcc PCIE_PARF_XPU_ARES>,
414 <&gcc PCIE_PHY_ARES>,
415 <&gcc PCIE_AXI_M_STICKY_ARES>,
416 <&gcc PCIE_PIPE_STICKY_ARES>,
417 <&gcc PCIE_PWR_ARES>,
418 <&gcc PCIE_AHB_ARES>,
419 <&gcc PCIE_PHY_AHB_ARES>;
420 reset-names = "axi_m",
436 qpic_bam: dma@7984000 {
437 compatible = "qcom,bam-v1.7.0";
438 reg = <0x7984000 0x1a000>;
439 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
440 clocks = <&gcc GCC_QPIC_CLK>;
441 clock-names = "bam_clk";
447 nand: qpic-nand@79b0000 {
448 compatible = "qcom,ipq4019-nand";
449 reg = <0x79b0000 0x1000>;
450 #address-cells = <1>;
452 clocks = <&gcc GCC_QPIC_CLK>,
453 <&gcc GCC_QPIC_AHB_CLK>;
454 clock-names = "core", "aon";
456 dmas = <&qpic_bam 0>,
459 dma-names = "tx", "rx", "cmd";
465 nand-ecc-strength = <4>;
466 nand-ecc-step-size = <512>;
467 nand-bus-width = <8>;
471 wifi0: wifi@a000000 {
472 compatible = "qcom,ipq4019-wifi";
473 reg = <0xa000000 0x200000>;
474 resets = <&gcc WIFI0_CPU_INIT_RESET>,
475 <&gcc WIFI0_RADIO_SRIF_RESET>,
476 <&gcc WIFI0_RADIO_WARM_RESET>,
477 <&gcc WIFI0_RADIO_COLD_RESET>,
478 <&gcc WIFI0_CORE_WARM_RESET>,
479 <&gcc WIFI0_CORE_COLD_RESET>;
480 reset-names = "wifi_cpu_init", "wifi_radio_srif",
481 "wifi_radio_warm", "wifi_radio_cold",
482 "wifi_core_warm", "wifi_core_cold";
483 clocks = <&gcc GCC_WCSS2G_CLK>,
484 <&gcc GCC_WCSS2G_REF_CLK>,
485 <&gcc GCC_WCSS2G_RTC_CLK>;
486 clock-names = "wifi_wcss_cmd", "wifi_wcss_ref",
488 interrupts = <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>,
489 <GIC_SPI 33 IRQ_TYPE_EDGE_RISING>,
490 <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>,
491 <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
492 <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
493 <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>,
494 <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>,
495 <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>,
496 <GIC_SPI 40 IRQ_TYPE_EDGE_RISING>,
497 <GIC_SPI 41 IRQ_TYPE_EDGE_RISING>,
498 <GIC_SPI 42 IRQ_TYPE_EDGE_RISING>,
499 <GIC_SPI 43 IRQ_TYPE_EDGE_RISING>,
500 <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>,
501 <GIC_SPI 45 IRQ_TYPE_EDGE_RISING>,
502 <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>,
503 <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>,
504 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
505 interrupt-names = "msi0", "msi1", "msi2", "msi3",
506 "msi4", "msi5", "msi6", "msi7",
507 "msi8", "msi9", "msi10", "msi11",
508 "msi12", "msi13", "msi14", "msi15",
513 wifi1: wifi@a800000 {
514 compatible = "qcom,ipq4019-wifi";
515 reg = <0xa800000 0x200000>;
516 resets = <&gcc WIFI1_CPU_INIT_RESET>,
517 <&gcc WIFI1_RADIO_SRIF_RESET>,
518 <&gcc WIFI1_RADIO_WARM_RESET>,
519 <&gcc WIFI1_RADIO_COLD_RESET>,
520 <&gcc WIFI1_CORE_WARM_RESET>,
521 <&gcc WIFI1_CORE_COLD_RESET>;
522 reset-names = "wifi_cpu_init", "wifi_radio_srif",
523 "wifi_radio_warm", "wifi_radio_cold",
524 "wifi_core_warm", "wifi_core_cold";
525 clocks = <&gcc GCC_WCSS5G_CLK>,
526 <&gcc GCC_WCSS5G_REF_CLK>,
527 <&gcc GCC_WCSS5G_RTC_CLK>;
528 clock-names = "wifi_wcss_cmd", "wifi_wcss_ref",
530 interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>,
531 <GIC_SPI 49 IRQ_TYPE_EDGE_RISING>,
532 <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>,
533 <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>,
534 <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>,
535 <GIC_SPI 53 IRQ_TYPE_EDGE_RISING>,
536 <GIC_SPI 54 IRQ_TYPE_EDGE_RISING>,
537 <GIC_SPI 55 IRQ_TYPE_EDGE_RISING>,
538 <GIC_SPI 56 IRQ_TYPE_EDGE_RISING>,
539 <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>,
540 <GIC_SPI 58 IRQ_TYPE_EDGE_RISING>,
541 <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>,
542 <GIC_SPI 60 IRQ_TYPE_EDGE_RISING>,
543 <GIC_SPI 61 IRQ_TYPE_EDGE_RISING>,
544 <GIC_SPI 62 IRQ_TYPE_EDGE_RISING>,
545 <GIC_SPI 63 IRQ_TYPE_EDGE_RISING>,
546 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
547 interrupt-names = "msi0", "msi1", "msi2", "msi3",
548 "msi4", "msi5", "msi6", "msi7",
549 "msi8", "msi9", "msi10", "msi11",
550 "msi12", "msi13", "msi14", "msi15",