2 * Copyright (c) 2015, The Linux Foundation. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
16 #include "skeleton.dtsi"
17 #include <dt-bindings/clock/qcom,gcc-ipq4019.h>
18 #include <dt-bindings/interrupt-controller/arm-gic.h>
19 #include <dt-bindings/interrupt-controller/irq.h>
22 model = "Qualcomm Technologies, Inc. IPQ4019";
23 compatible = "qcom,ipq4019";
24 interrupt-parent = <&intc>;
36 compatible = "arm,cortex-a7";
37 enable-method = "qcom,kpss-acc-v1";
41 clocks = <&gcc GCC_APPS_CLK_SRC>;
42 clock-frequency = <0>;
50 clock-latency = <256000>;
55 compatible = "arm,cortex-a7";
56 enable-method = "qcom,kpss-acc-v1";
60 clocks = <&gcc GCC_APPS_CLK_SRC>;
61 clock-frequency = <0>;
66 compatible = "arm,cortex-a7";
67 enable-method = "qcom,kpss-acc-v1";
71 clocks = <&gcc GCC_APPS_CLK_SRC>;
72 clock-frequency = <0>;
77 compatible = "arm,cortex-a7";
78 enable-method = "qcom,kpss-acc-v1";
82 clocks = <&gcc GCC_APPS_CLK_SRC>;
83 clock-frequency = <0>;
88 compatible = "arm,cortex-a7-pmu";
89 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) |
90 IRQ_TYPE_LEVEL_HIGH)>;
94 sleep_clk: sleep_clk {
95 compatible = "fixed-clock";
96 clock-frequency = <32000>;
97 clock-output-names = "gcc_sleep_clk_src";
103 #address-cells = <1>;
106 compatible = "simple-bus";
108 intc: interrupt-controller@b000000 {
109 compatible = "qcom,msm-qgic2";
110 interrupt-controller;
111 #interrupt-cells = <3>;
112 reg = <0x0b000000 0x1000>,
116 gcc: clock-controller@1800000 {
117 compatible = "qcom,gcc-ipq4019";
120 reg = <0x1800000 0x60000>;
123 tlmm: pinctrl@0x01000000 {
124 compatible = "qcom,ipq4019-pinctrl";
125 reg = <0x01000000 0x300000>;
128 interrupt-controller;
129 #interrupt-cells = <2>;
130 interrupts = <0 208 0>;
133 blsp_dma: dma@7884000 {
134 compatible = "qcom,bam-v1.7.0";
135 reg = <0x07884000 0x23000>;
136 interrupts = <GIC_SPI 238 IRQ_TYPE_NONE>;
137 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
138 clock-names = "bam_clk";
145 compatible = "qcom,spi-qup-v2.2.1";
146 reg = <0x78b5000 0x600>;
147 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
148 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
149 <&gcc GCC_BLSP1_AHB_CLK>;
150 clock-names = "core", "iface";
151 #address-cells = <1>;
157 compatible = "qcom,i2c-qup-v2.2.1";
158 reg = <0x78b7000 0x600>;
159 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
160 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
161 <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>;
162 clock-names = "iface", "core";
163 #address-cells = <1>;
169 cryptobam: dma@8e04000 {
170 compatible = "qcom,bam-v1.7.0";
171 reg = <0x08e04000 0x20000>;
172 interrupts = <GIC_SPI 207 0>;
173 clocks = <&gcc GCC_CRYPTO_AHB_CLK>;
174 clock-names = "bam_clk";
177 qcom,controlled-remotely;
182 compatible = "qcom,crypto-v5.1";
183 reg = <0x08e3a000 0x6000>;
184 clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
185 <&gcc GCC_CRYPTO_AXI_CLK>,
186 <&gcc GCC_CRYPTO_CLK>;
187 clock-names = "iface", "bus", "core";
188 dmas = <&cryptobam 2>, <&cryptobam 3>;
189 dma-names = "rx", "tx";
193 acc0: clock-controller@b088000 {
194 compatible = "qcom,kpss-acc-v1";
195 reg = <0x0b088000 0x1000>, <0xb008000 0x1000>;
198 acc1: clock-controller@b098000 {
199 compatible = "qcom,kpss-acc-v1";
200 reg = <0x0b098000 0x1000>, <0xb008000 0x1000>;
203 acc2: clock-controller@b0a8000 {
204 compatible = "qcom,kpss-acc-v1";
205 reg = <0x0b0a8000 0x1000>, <0xb008000 0x1000>;
208 acc3: clock-controller@b0b8000 {
209 compatible = "qcom,kpss-acc-v1";
210 reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>;
213 saw0: regulator@b089000 {
214 compatible = "qcom,saw2";
215 reg = <0x0b089000 0x1000>, <0x0b009000 0x1000>;
219 saw1: regulator@b099000 {
220 compatible = "qcom,saw2";
221 reg = <0x0b099000 0x1000>, <0x0b009000 0x1000>;
225 saw2: regulator@b0a9000 {
226 compatible = "qcom,saw2";
227 reg = <0x0b0a9000 0x1000>, <0x0b009000 0x1000>;
231 saw3: regulator@b0b9000 {
232 compatible = "qcom,saw2";
233 reg = <0x0b0b9000 0x1000>, <0x0b009000 0x1000>;
238 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
239 reg = <0x78af000 0x200>;
240 interrupts = <0 107 0>;
242 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
243 <&gcc GCC_BLSP1_AHB_CLK>;
244 clock-names = "core", "iface";
245 dmas = <&blsp_dma 1>, <&blsp_dma 0>;
246 dma-names = "rx", "tx";
250 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
251 reg = <0x78b0000 0x200>;
252 interrupts = <0 108 0>;
254 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
255 <&gcc GCC_BLSP1_AHB_CLK>;
256 clock-names = "core", "iface";
257 dmas = <&blsp_dma 3>, <&blsp_dma 2>;
258 dma-names = "rx", "tx";
262 compatible = "qcom,kpss-wdt", "qcom,kpss-wdt-ipq4019";
263 reg = <0xb017000 0x40>;
264 clocks = <&sleep_clk>;
270 compatible = "qcom,pshold";
271 reg = <0x4ab000 0x4>;