1 // SPDX-License-Identifier: GPL-2.0
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/clock/qcom,gcc-apq8084.h>
6 #include <dt-bindings/gpio/gpio.h>
11 model = "Qualcomm APQ 8084";
12 compatible = "qcom,apq8084";
13 interrupt-parent = <&intc>;
20 smem_mem: smem_region@fa00000 {
21 reg = <0xfa00000 0x200000>;
32 compatible = "qcom,krait";
34 enable-method = "qcom,kpss-acc-v2";
35 next-level-cache = <&L2>;
38 cpu-idle-states = <&CPU_SPC>;
43 compatible = "qcom,krait";
45 enable-method = "qcom,kpss-acc-v2";
46 next-level-cache = <&L2>;
49 cpu-idle-states = <&CPU_SPC>;
54 compatible = "qcom,krait";
56 enable-method = "qcom,kpss-acc-v2";
57 next-level-cache = <&L2>;
60 cpu-idle-states = <&CPU_SPC>;
65 compatible = "qcom,krait";
67 enable-method = "qcom,kpss-acc-v2";
68 next-level-cache = <&L2>;
71 cpu-idle-states = <&CPU_SPC>;
75 compatible = "qcom,arch-cache";
82 compatible = "qcom,idle-state-spc",
84 entry-latency-us = <150>;
85 exit-latency-us = <200>;
86 min-residency-us = <2000>;
92 device_type = "memory";
98 compatible = "qcom,scm-apq8084", "qcom,scm";
99 clocks = <&gcc GCC_CE1_CLK> , <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>;
100 clock-names = "core", "bus", "iface";
106 polling-delay-passive = <250>;
107 polling-delay = <1000>;
109 thermal-sensors = <&tsens 5>;
113 temperature = <75000>;
118 temperature = <110000>;
126 polling-delay-passive = <250>;
127 polling-delay = <1000>;
129 thermal-sensors = <&tsens 6>;
133 temperature = <75000>;
138 temperature = <110000>;
146 polling-delay-passive = <250>;
147 polling-delay = <1000>;
149 thermal-sensors = <&tsens 7>;
153 temperature = <75000>;
158 temperature = <110000>;
166 polling-delay-passive = <250>;
167 polling-delay = <1000>;
169 thermal-sensors = <&tsens 8>;
173 temperature = <75000>;
178 temperature = <110000>;
187 compatible = "qcom,krait-pmu";
188 interrupts = <GIC_PPI 7 0xf04>;
193 compatible = "fixed-clock";
195 clock-frequency = <19200000>;
198 sleep_clk: sleep_clk {
199 compatible = "fixed-clock";
201 clock-frequency = <32768>;
206 compatible = "arm,armv7-timer";
207 interrupts = <GIC_PPI 2 0xf08>,
211 clock-frequency = <19200000>;
215 compatible = "qcom,smem";
217 qcom,rpm-msg-ram = <&rpm_msg_ram>;
218 memory-region = <&smem_mem>;
220 hwlocks = <&tcsr_mutex 3>;
224 #address-cells = <1>;
227 compatible = "simple-bus";
229 intc: interrupt-controller@f9000000 {
230 compatible = "qcom,msm-qgic2";
231 interrupt-controller;
232 #interrupt-cells = <3>;
233 reg = <0xf9000000 0x1000>,
237 apcs: syscon@f9011000 {
238 compatible = "syscon";
239 reg = <0xf9011000 0x1000>;
243 compatible = "qcom,apq8084-rpm-stats";
244 reg = <0xfc190000 0x10000>;
247 qfprom: qfprom@fc4bc000 {
248 compatible = "qcom,apq8084-qfprom", "qcom,qfprom";
249 reg = <0xfc4bc000 0x1000>;
250 #address-cells = <1>;
252 tsens_calib: calib@d0 {
255 tsens_backup: backup@440 {
260 tsens: thermal-sensor@fc4a8000 {
261 compatible = "qcom,msm8974-tsens";
262 reg = <0xfc4a9000 0x1000>, /* TM */
263 <0xfc4a8000 0x1000>; /* SROT */
264 nvmem-cells = <&tsens_calib>, <&tsens_backup>;
265 nvmem-cell-names = "calib", "calib_backup";
266 #qcom,sensors = <11>;
267 #thermal-sensor-cells = <1>;
270 #address-cells = <1>;
273 compatible = "arm,armv7-timer-mem";
274 reg = <0xf9020000 0x1000>;
275 clock-frequency = <19200000>;
279 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
280 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
281 reg = <0xf9021000 0x1000>,
287 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
288 reg = <0xf9023000 0x1000>;
294 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
295 reg = <0xf9024000 0x1000>;
301 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
302 reg = <0xf9025000 0x1000>;
308 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
309 reg = <0xf9026000 0x1000>;
315 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
316 reg = <0xf9027000 0x1000>;
322 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
323 reg = <0xf9028000 0x1000>;
328 saw0: power-controller@f9089000 {
329 compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
330 reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
333 saw1: power-controller@f9099000 {
334 compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
335 reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>;
338 saw2: power-controller@f90a9000 {
339 compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
340 reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>;
343 saw3: power-controller@f90b9000 {
344 compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
345 reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>;
348 saw_l2: power-controller@f9012000 {
349 compatible = "qcom,saw2";
350 reg = <0xf9012000 0x1000>;
354 acc0: clock-controller@f9088000 {
355 compatible = "qcom,kpss-acc-v2";
356 reg = <0xf9088000 0x1000>,
360 acc1: clock-controller@f9098000 {
361 compatible = "qcom,kpss-acc-v2";
362 reg = <0xf9098000 0x1000>,
366 acc2: clock-controller@f90a8000 {
367 compatible = "qcom,kpss-acc-v2";
368 reg = <0xf90a8000 0x1000>,
372 acc3: clock-controller@f90b8000 {
373 compatible = "qcom,kpss-acc-v2";
374 reg = <0xf90b8000 0x1000>,
379 compatible = "qcom,pshold";
380 reg = <0xfc4ab000 0x4>;
383 gcc: clock-controller@fc400000 {
384 compatible = "qcom,gcc-apq8084";
387 #power-domain-cells = <1>;
388 reg = <0xfc400000 0x4000>;
391 tcsr_mutex: hwlock@fd484000 {
392 compatible = "qcom,apq8084-tcsr-mutex", "qcom,tcsr-mutex";
393 reg = <0xfd484000 0x1000>;
397 rpm_msg_ram: memory@fc428000 {
398 compatible = "qcom,rpm-msg-ram";
399 reg = <0xfc428000 0x4000>;
402 tlmm: pinctrl@fd510000 {
403 compatible = "qcom,apq8084-pinctrl";
404 reg = <0xfd510000 0x4000>;
406 gpio-ranges = <&tlmm 0 0 147>;
408 interrupt-controller;
409 #interrupt-cells = <2>;
410 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
413 blsp2_uart2: serial@f995e000 {
414 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
415 reg = <0xf995e000 0x1000>;
416 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
417 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
418 clock-names = "core", "iface";
422 sdhc_1: mmc@f9824900 {
423 compatible = "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4";
424 reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
425 reg-names = "hc", "core";
426 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
427 interrupt-names = "hc_irq", "pwr_irq";
428 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
429 <&gcc GCC_SDCC1_APPS_CLK>,
431 clock-names = "iface", "core", "xo";
435 sdhc_2: mmc@f98a4900 {
436 compatible = "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4";
437 reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
438 reg-names = "hc", "core";
439 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
440 interrupt-names = "hc_irq", "pwr_irq";
441 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
442 <&gcc GCC_SDCC2_APPS_CLK>,
444 clock-names = "iface", "core", "xo";
448 spmi_bus: spmi@fc4cf000 {
449 compatible = "qcom,spmi-pmic-arb";
450 reg-names = "core", "intr", "cnfg";
451 reg = <0xfc4cf000 0x1000>,
454 interrupt-names = "periph_irq";
455 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
458 #address-cells = <2>;
460 interrupt-controller;
461 #interrupt-cells = <4>;
466 compatible = "qcom,smd";
469 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
470 qcom,ipc = <&apcs 8 0>;
471 qcom,smd-edge = <15>;
474 compatible = "qcom,rpm-apq8084";
475 qcom,smd-channels = "rpm_requests";
478 compatible = "qcom,rpm-pma8084-regulators";
521 pma8084_lvs1: lvs1 {};
522 pma8084_lvs2: lvs2 {};
523 pma8084_lvs3: lvs3 {};
524 pma8084_lvs4: lvs4 {};
526 pma8084_5vs1: 5vs1 {};