1 // SPDX-License-Identifier: GPL-2.0
4 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
5 #include <dt-bindings/clock/qcom,lcc-msm8960.h>
6 #include <dt-bindings/reset/qcom,gcc-msm8960.h>
7 #include <dt-bindings/clock/qcom,mmcc-msm8960.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/soc/qcom,gsbi.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 model = "Qualcomm APQ8064";
16 compatible = "qcom,apq8064";
17 interrupt-parent = <&intc>;
24 smem_region: smem@80000000 {
25 reg = <0x80000000 0x200000>;
29 wcnss_mem: wcnss@8f000000 {
30 reg = <0x8f000000 0x700000>;
40 compatible = "qcom,krait";
41 enable-method = "qcom,kpss-acc-v1";
44 next-level-cache = <&L2>;
47 cpu-idle-states = <&CPU_SPC>;
51 compatible = "qcom,krait";
52 enable-method = "qcom,kpss-acc-v1";
55 next-level-cache = <&L2>;
58 cpu-idle-states = <&CPU_SPC>;
62 compatible = "qcom,krait";
63 enable-method = "qcom,kpss-acc-v1";
66 next-level-cache = <&L2>;
69 cpu-idle-states = <&CPU_SPC>;
73 compatible = "qcom,krait";
74 enable-method = "qcom,kpss-acc-v1";
77 next-level-cache = <&L2>;
80 cpu-idle-states = <&CPU_SPC>;
90 compatible = "qcom,idle-state-spc",
92 entry-latency-us = <400>;
93 exit-latency-us = <900>;
94 min-residency-us = <3000>;
100 device_type = "memory";
106 polling-delay-passive = <250>;
107 polling-delay = <1000>;
109 thermal-sensors = <&tsens 7>;
110 coefficients = <1199 0>;
114 temperature = <75000>;
119 temperature = <110000>;
127 polling-delay-passive = <250>;
128 polling-delay = <1000>;
130 thermal-sensors = <&tsens 8>;
131 coefficients = <1132 0>;
135 temperature = <75000>;
140 temperature = <110000>;
148 polling-delay-passive = <250>;
149 polling-delay = <1000>;
151 thermal-sensors = <&tsens 9>;
152 coefficients = <1199 0>;
156 temperature = <75000>;
161 temperature = <110000>;
169 polling-delay-passive = <250>;
170 polling-delay = <1000>;
172 thermal-sensors = <&tsens 10>;
173 coefficients = <1132 0>;
177 temperature = <75000>;
182 temperature = <110000>;
191 compatible = "qcom,krait-pmu";
192 interrupts = <1 10 0x304>;
196 cxo_board: cxo_board {
197 compatible = "fixed-clock";
199 clock-frequency = <19200000>;
202 pxo_board: pxo_board {
203 compatible = "fixed-clock";
205 clock-frequency = <27000000>;
208 sleep_clk: sleep_clk {
209 compatible = "fixed-clock";
211 clock-frequency = <32768>;
215 sfpb_mutex: hwmutex {
216 compatible = "qcom,sfpb-mutex";
217 syscon = <&sfpb_wrapper_mutex 0x604 0x4>;
222 compatible = "qcom,smem";
223 memory-region = <&smem_region>;
225 hwlocks = <&sfpb_mutex 3>;
229 compatible = "qcom,smd";
232 interrupts = <0 37 IRQ_TYPE_EDGE_RISING>;
234 qcom,ipc = <&l2cc 8 3>;
241 interrupts = <0 90 IRQ_TYPE_EDGE_RISING>;
243 qcom,ipc = <&l2cc 8 15>;
250 interrupts = <0 138 IRQ_TYPE_EDGE_RISING>;
252 qcom,ipc = <&sps_sic_non_secure 0x4080 0>;
259 interrupts = <0 198 IRQ_TYPE_EDGE_RISING>;
261 qcom,ipc = <&l2cc 8 25>;
269 compatible = "qcom,smsm";
271 #address-cells = <1>;
274 qcom,ipc-1 = <&l2cc 8 4>;
275 qcom,ipc-2 = <&l2cc 8 14>;
276 qcom,ipc-3 = <&l2cc 8 23>;
277 qcom,ipc-4 = <&sps_sic_non_secure 0x4094 0>;
281 #qcom,smem-state-cells = <1>;
284 modem_smsm: modem@1 {
286 interrupts = <0 38 IRQ_TYPE_EDGE_RISING>;
288 interrupt-controller;
289 #interrupt-cells = <2>;
294 interrupts = <0 89 IRQ_TYPE_EDGE_RISING>;
296 interrupt-controller;
297 #interrupt-cells = <2>;
300 wcnss_smsm: wcnss@3 {
302 interrupts = <0 204 IRQ_TYPE_EDGE_RISING>;
304 interrupt-controller;
305 #interrupt-cells = <2>;
310 interrupts = <0 137 IRQ_TYPE_EDGE_RISING>;
312 interrupt-controller;
313 #interrupt-cells = <2>;
319 compatible = "qcom,scm-apq8064", "qcom,scm";
321 clocks = <&rpmcc RPM_DAYTONA_FABRIC_CLK>;
322 clock-names = "core";
328 * These channels from the ADC are simply hardware monitors.
329 * That is why the ADC is referred to as "HKADC" - HouseKeeping
333 compatible = "iio-hwmon";
334 io-channels = <&xoadc 0x00 0x01>, /* Battery */
335 <&xoadc 0x00 0x02>, /* DC in (charger) */
336 <&xoadc 0x00 0x04>, /* VPH the main system voltage */
337 <&xoadc 0x00 0x0b>, /* Die temperature */
338 <&xoadc 0x00 0x0c>, /* Reference voltage 1.25V */
339 <&xoadc 0x00 0x0d>, /* Reference voltage 0.625V */
340 <&xoadc 0x00 0x0e>; /* Charger temperature */
344 #address-cells = <1>;
347 compatible = "simple-bus";
349 tlmm_pinmux: pinctrl@800000 {
350 compatible = "qcom,apq8064-pinctrl";
351 reg = <0x800000 0x4000>;
354 gpio-ranges = <&tlmm_pinmux 0 0 90>;
356 interrupt-controller;
357 #interrupt-cells = <2>;
358 interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
360 pinctrl-names = "default";
361 pinctrl-0 = <&ps_hold>;
364 sfpb_wrapper_mutex: syscon@1200000 {
365 compatible = "syscon";
366 reg = <0x01200000 0x8000>;
369 intc: interrupt-controller@2000000 {
370 compatible = "qcom,msm-qgic2";
371 interrupt-controller;
372 #interrupt-cells = <3>;
373 reg = <0x02000000 0x1000>,
378 compatible = "qcom,kpss-timer",
379 "qcom,kpss-wdt-apq8064", "qcom,msm-timer";
380 interrupts = <1 1 0x301>,
383 reg = <0x0200a000 0x100>;
384 clock-frequency = <27000000>,
386 cpu-offset = <0x80000>;
389 acc0: clock-controller@2088000 {
390 compatible = "qcom,kpss-acc-v1";
391 reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
394 acc1: clock-controller@2098000 {
395 compatible = "qcom,kpss-acc-v1";
396 reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
399 acc2: clock-controller@20a8000 {
400 compatible = "qcom,kpss-acc-v1";
401 reg = <0x020a8000 0x1000>, <0x02008000 0x1000>;
404 acc3: clock-controller@20b8000 {
405 compatible = "qcom,kpss-acc-v1";
406 reg = <0x020b8000 0x1000>, <0x02008000 0x1000>;
409 saw0: power-controller@2089000 {
410 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
411 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
415 saw1: power-controller@2099000 {
416 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
417 reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
421 saw2: power-controller@20a9000 {
422 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
423 reg = <0x020a9000 0x1000>, <0x02009000 0x1000>;
427 saw3: power-controller@20b9000 {
428 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
429 reg = <0x020b9000 0x1000>, <0x02009000 0x1000>;
433 sps_sic_non_secure: sps-sic-non-secure@12100000 {
434 compatible = "syscon";
435 reg = <0x12100000 0x10000>;
438 gsbi1: gsbi@12440000 {
440 compatible = "qcom,gsbi-v1.0.0";
442 reg = <0x12440000 0x100>;
443 clocks = <&gcc GSBI1_H_CLK>;
444 clock-names = "iface";
445 #address-cells = <1>;
449 syscon-tcsr = <&tcsr>;
451 gsbi1_serial: serial@12450000 {
452 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
453 reg = <0x12450000 0x100>,
455 interrupts = <0 193 IRQ_TYPE_LEVEL_HIGH>;
456 clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
457 clock-names = "core", "iface";
461 gsbi1_i2c: i2c@12460000 {
462 compatible = "qcom,i2c-qup-v1.1.1";
463 pinctrl-0 = <&i2c1_pins>;
464 pinctrl-1 = <&i2c1_pins_sleep>;
465 pinctrl-names = "default", "sleep";
466 reg = <0x12460000 0x1000>;
467 interrupts = <0 194 IRQ_TYPE_LEVEL_HIGH>;
468 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
469 clock-names = "core", "iface";
470 #address-cells = <1>;
477 gsbi2: gsbi@12480000 {
479 compatible = "qcom,gsbi-v1.0.0";
481 reg = <0x12480000 0x100>;
482 clocks = <&gcc GSBI2_H_CLK>;
483 clock-names = "iface";
484 #address-cells = <1>;
488 syscon-tcsr = <&tcsr>;
490 gsbi2_i2c: i2c@124a0000 {
491 compatible = "qcom,i2c-qup-v1.1.1";
492 reg = <0x124a0000 0x1000>;
493 pinctrl-0 = <&i2c2_pins>;
494 pinctrl-1 = <&i2c2_pins_sleep>;
495 pinctrl-names = "default", "sleep";
496 interrupts = <0 196 IRQ_TYPE_LEVEL_HIGH>;
497 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
498 clock-names = "core", "iface";
499 #address-cells = <1>;
505 gsbi3: gsbi@16200000 {
507 compatible = "qcom,gsbi-v1.0.0";
509 reg = <0x16200000 0x100>;
510 clocks = <&gcc GSBI3_H_CLK>;
511 clock-names = "iface";
512 #address-cells = <1>;
515 gsbi3_i2c: i2c@16280000 {
516 compatible = "qcom,i2c-qup-v1.1.1";
517 pinctrl-0 = <&i2c3_pins>;
518 pinctrl-1 = <&i2c3_pins_sleep>;
519 pinctrl-names = "default", "sleep";
520 reg = <0x16280000 0x1000>;
521 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
522 clocks = <&gcc GSBI3_QUP_CLK>,
524 clock-names = "core", "iface";
525 #address-cells = <1>;
531 gsbi4: gsbi@16300000 {
533 compatible = "qcom,gsbi-v1.0.0";
535 reg = <0x16300000 0x03>;
536 clocks = <&gcc GSBI4_H_CLK>;
537 clock-names = "iface";
538 #address-cells = <1>;
542 gsbi4_i2c: i2c@16380000 {
543 compatible = "qcom,i2c-qup-v1.1.1";
544 pinctrl-0 = <&i2c4_pins>;
545 pinctrl-1 = <&i2c4_pins_sleep>;
546 pinctrl-names = "default", "sleep";
547 reg = <0x16380000 0x1000>;
548 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
549 clocks = <&gcc GSBI4_QUP_CLK>,
551 clock-names = "core", "iface";
556 gsbi5: gsbi@1a200000 {
558 compatible = "qcom,gsbi-v1.0.0";
560 reg = <0x1a200000 0x03>;
561 clocks = <&gcc GSBI5_H_CLK>;
562 clock-names = "iface";
563 #address-cells = <1>;
567 gsbi5_serial: serial@1a240000 {
568 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
569 reg = <0x1a240000 0x100>,
571 interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>;
572 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
573 clock-names = "core", "iface";
577 gsbi5_spi: spi@1a280000 {
578 compatible = "qcom,spi-qup-v1.1.1";
579 reg = <0x1a280000 0x1000>;
580 interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>;
581 pinctrl-0 = <&spi5_default>;
582 pinctrl-1 = <&spi5_sleep>;
583 pinctrl-names = "default", "sleep";
584 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
585 clock-names = "core", "iface";
587 #address-cells = <1>;
592 gsbi6: gsbi@16500000 {
594 compatible = "qcom,gsbi-v1.0.0";
596 reg = <0x16500000 0x03>;
597 clocks = <&gcc GSBI6_H_CLK>;
598 clock-names = "iface";
599 #address-cells = <1>;
603 gsbi6_serial: serial@16540000 {
604 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
605 reg = <0x16540000 0x100>,
607 interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
608 clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>;
609 clock-names = "core", "iface";
613 gsbi6_i2c: i2c@16580000 {
614 compatible = "qcom,i2c-qup-v1.1.1";
615 pinctrl-0 = <&i2c6_pins>;
616 pinctrl-1 = <&i2c6_pins_sleep>;
617 pinctrl-names = "default", "sleep";
618 reg = <0x16580000 0x1000>;
619 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
620 clocks = <&gcc GSBI6_QUP_CLK>,
622 clock-names = "core", "iface";
627 gsbi7: gsbi@16600000 {
629 compatible = "qcom,gsbi-v1.0.0";
631 reg = <0x16600000 0x100>;
632 clocks = <&gcc GSBI7_H_CLK>;
633 clock-names = "iface";
634 #address-cells = <1>;
637 syscon-tcsr = <&tcsr>;
639 gsbi7_serial: serial@16640000 {
640 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
641 reg = <0x16640000 0x1000>,
643 interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>;
644 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
645 clock-names = "core", "iface";
649 gsbi7_i2c: i2c@16680000 {
650 compatible = "qcom,i2c-qup-v1.1.1";
651 pinctrl-0 = <&i2c7_pins>;
652 pinctrl-1 = <&i2c7_pins_sleep>;
653 pinctrl-names = "default", "sleep";
654 reg = <0x16680000 0x1000>;
655 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
656 clocks = <&gcc GSBI7_QUP_CLK>,
658 clock-names = "core", "iface";
664 compatible = "qcom,prng";
665 reg = <0x1a500000 0x200>;
666 clocks = <&gcc PRNG_CLK>;
667 clock-names = "core";
671 compatible = "qcom,ssbi";
672 reg = <0x00c00000 0x1000>;
673 qcom,controller-type = "pmic-arbiter";
676 compatible = "qcom,pm8821";
677 interrupt-parent = <&tlmm_pinmux>;
678 interrupts = <76 IRQ_TYPE_LEVEL_LOW>;
679 #interrupt-cells = <2>;
680 interrupt-controller;
681 #address-cells = <1>;
684 pm8821_mpps: mpps@50 {
685 compatible = "qcom,pm8821-mpp", "qcom,ssbi-mpp";
687 interrupt-controller;
688 #interrupt-cells = <2>;
691 gpio-ranges = <&pm8821_mpps 0 0 4>;
697 compatible = "qcom,ssbi";
698 reg = <0x00500000 0x1000>;
699 qcom,controller-type = "pmic-arbiter";
702 compatible = "qcom,pm8921";
703 interrupt-parent = <&tlmm_pinmux>;
705 #interrupt-cells = <2>;
706 interrupt-controller;
707 #address-cells = <1>;
710 pm8921_gpio: gpio@150 {
712 compatible = "qcom,pm8921-gpio",
715 interrupt-controller;
716 #interrupt-cells = <2>;
718 gpio-ranges = <&pm8921_gpio 0 0 44>;
723 pm8921_mpps: mpps@50 {
724 compatible = "qcom,pm8921-mpp",
729 gpio-ranges = <&pm8921_mpps 0 0 12>;
730 interrupt-controller;
731 #interrupt-cells = <2>;
735 compatible = "qcom,pm8921-rtc";
736 interrupt-parent = <&pmicintc>;
743 compatible = "qcom,pm8921-pwrkey";
745 interrupt-parent = <&pmicintc>;
746 interrupts = <50 1>, <51 1>;
752 compatible = "qcom,pm8921-adc";
754 interrupts-extended = <&pmicintc 78 IRQ_TYPE_EDGE_RISING>;
755 #address-cells = <2>;
757 #io-channel-cells = <2>;
759 vcoin: adc-channel@0 {
762 vbat: adc-channel@1 {
765 dcin: adc-channel@2 {
768 vph_pwr: adc-channel@4 {
771 batt_therm: adc-channel@8 {
774 batt_id: adc-channel@9 {
777 usb_vbus: adc-channel@a {
780 die_temp: adc-channel@b {
783 ref_625mv: adc-channel@c {
786 ref_1250mv: adc-channel@d {
789 chg_temp: adc-channel@e {
792 ref_muxoff: adc-channel@f {
799 qfprom: qfprom@700000 {
800 compatible = "qcom,apq8064-qfprom", "qcom,qfprom";
801 reg = <0x00700000 0x1000>;
802 #address-cells = <1>;
805 tsens_calib: calib@404 {
808 tsens_backup: backup_calib@414 {
813 gcc: clock-controller@900000 {
814 compatible = "qcom,gcc-apq8064", "syscon";
815 reg = <0x00900000 0x4000>;
817 #power-domain-cells = <1>;
819 clocks = <&cxo_board>,
822 clock-names = "cxo", "pxo", "pll4";
824 tsens: thermal-sensor {
825 compatible = "qcom,msm8960-tsens";
827 nvmem-cells = <&tsens_calib>, <&tsens_backup>;
828 nvmem-cell-names = "calib", "calib_backup";
829 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
830 interrupt-names = "uplow";
832 #qcom,sensors = <11>;
833 #thermal-sensor-cells = <1>;
837 lcc: clock-controller@28000000 {
838 compatible = "qcom,lcc-apq8064";
839 reg = <0x28000000 0x1000>;
842 clocks = <&pxo_board>,
851 "codec_i2s_mic_codec_clk",
852 "spare_i2s_mic_codec_clk",
853 "codec_i2s_spkr_codec_clk",
854 "spare_i2s_spkr_codec_clk",
858 mmcc: clock-controller@4000000 {
859 compatible = "qcom,mmcc-apq8064";
860 reg = <0x4000000 0x1000>;
862 #power-domain-cells = <1>;
864 clocks = <&pxo_board>,
882 l2cc: clock-controller@2011000 {
883 compatible = "qcom,kpss-gcc", "syscon";
884 reg = <0x2011000 0x1000>;
888 compatible = "qcom,rpm-apq8064";
889 reg = <0x108000 0x1000>;
890 qcom,ipc = <&l2cc 0x8 2>;
892 interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
893 <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
894 <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
895 interrupt-names = "ack", "err", "wakeup";
897 rpmcc: clock-controller {
898 compatible = "qcom,rpmcc-apq8064", "qcom,rpmcc";
900 clocks = <&pxo_board>, <&cxo_board>;
901 clock-names = "pxo", "cxo";
905 compatible = "qcom,rpm-pm8921-regulators";
941 pm8921_lvs1: lvs1 {};
942 pm8921_lvs2: lvs2 {};
943 pm8921_lvs3: lvs3 {};
944 pm8921_lvs4: lvs4 {};
945 pm8921_lvs5: lvs5 {};
946 pm8921_lvs6: lvs6 {};
947 pm8921_lvs7: lvs7 {};
949 pm8921_usb_switch: usb-switch {};
951 pm8921_hdmi_switch: hdmi-switch {
960 compatible = "qcom,ci-hdrc";
961 reg = <0x12500000 0x200>,
963 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
964 clocks = <&gcc USB_HS1_XCVR_CLK>, <&gcc USB_HS1_H_CLK>;
965 clock-names = "core", "iface";
966 assigned-clocks = <&gcc USB_HS1_XCVR_CLK>;
967 assigned-clock-rates = <60000000>;
968 resets = <&gcc USB_HS1_RESET>;
969 reset-names = "core";
971 ahb-burst-config = <0>;
972 phys = <&usb_hs1_phy>;
973 phy-names = "usb-phy";
979 compatible = "qcom,usb-hs-phy-apq8064",
981 clocks = <&sleep_clk>, <&cxo_board>;
982 clock-names = "sleep", "ref";
991 compatible = "qcom,ci-hdrc";
992 reg = <0x12520000 0x200>,
994 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
995 clocks = <&gcc USB_HS3_XCVR_CLK>, <&gcc USB_HS3_H_CLK>;
996 clock-names = "core", "iface";
997 assigned-clocks = <&gcc USB_HS3_XCVR_CLK>;
998 assigned-clock-rates = <60000000>;
999 resets = <&gcc USB_HS3_RESET>;
1000 reset-names = "core";
1002 ahb-burst-config = <0>;
1003 phys = <&usb_hs3_phy>;
1004 phy-names = "usb-phy";
1005 status = "disabled";
1010 compatible = "qcom,usb-hs-phy-apq8064",
1013 clocks = <&sleep_clk>, <&cxo_board>;
1014 clock-names = "sleep", "ref";
1016 reset-names = "por";
1021 usb4: usb@12530000 {
1022 compatible = "qcom,ci-hdrc";
1023 reg = <0x12530000 0x200>,
1025 interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
1026 clocks = <&gcc USB_HS4_XCVR_CLK>, <&gcc USB_HS4_H_CLK>;
1027 clock-names = "core", "iface";
1028 assigned-clocks = <&gcc USB_HS4_XCVR_CLK>;
1029 assigned-clock-rates = <60000000>;
1030 resets = <&gcc USB_HS4_RESET>;
1031 reset-names = "core";
1033 ahb-burst-config = <0>;
1034 phys = <&usb_hs4_phy>;
1035 phy-names = "usb-phy";
1036 status = "disabled";
1041 compatible = "qcom,usb-hs-phy-apq8064",
1044 clocks = <&sleep_clk>, <&cxo_board>;
1045 clock-names = "sleep", "ref";
1047 reset-names = "por";
1052 sata_phy0: phy@1b400000 {
1053 compatible = "qcom,apq8064-sata-phy";
1054 status = "disabled";
1055 reg = <0x1b400000 0x200>;
1056 reg-names = "phy_mem";
1057 clocks = <&gcc SATA_PHY_CFG_CLK>;
1058 clock-names = "cfg";
1062 sata0: sata@29000000 {
1063 compatible = "qcom,apq8064-ahci", "generic-ahci";
1064 status = "disabled";
1065 reg = <0x29000000 0x180>;
1066 interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
1068 clocks = <&gcc SFAB_SATA_S_H_CLK>,
1071 <&gcc SATA_RXOOB_CLK>,
1072 <&gcc SATA_PMALIVE_CLK>;
1073 clock-names = "slave_iface",
1079 assigned-clocks = <&gcc SATA_RXOOB_CLK>,
1080 <&gcc SATA_PMALIVE_CLK>;
1081 assigned-clock-rates = <100000000>, <100000000>;
1083 phys = <&sata_phy0>;
1084 phy-names = "sata-phy";
1085 ports-implemented = <0x1>;
1088 /* Temporary fixed regulator */
1089 sdcc1bam: dma-controller@12402000{
1090 compatible = "qcom,bam-v1.3.0";
1091 reg = <0x12402000 0x8000>;
1092 interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
1093 clocks = <&gcc SDC1_H_CLK>;
1094 clock-names = "bam_clk";
1099 sdcc3bam: dma-controller@12182000{
1100 compatible = "qcom,bam-v1.3.0";
1101 reg = <0x12182000 0x8000>;
1102 interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
1103 clocks = <&gcc SDC3_H_CLK>;
1104 clock-names = "bam_clk";
1109 sdcc4bam: dma-controller@121c2000{
1110 compatible = "qcom,bam-v1.3.0";
1111 reg = <0x121c2000 0x8000>;
1112 interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
1113 clocks = <&gcc SDC4_H_CLK>;
1114 clock-names = "bam_clk";
1120 compatible = "simple-bus";
1121 #address-cells = <1>;
1124 sdcc1: mmc@12400000 {
1125 status = "disabled";
1126 compatible = "arm,pl18x", "arm,primecell";
1127 pinctrl-names = "default";
1128 pinctrl-0 = <&sdcc1_pins>;
1129 arm,primecell-periphid = <0x00051180>;
1130 reg = <0x12400000 0x2000>;
1131 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
1132 interrupt-names = "cmd_irq";
1133 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
1134 clock-names = "mclk", "apb_pclk";
1136 max-frequency = <96000000>;
1140 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
1141 dma-names = "tx", "rx";
1144 sdcc3: mmc@12180000 {
1145 compatible = "arm,pl18x", "arm,primecell";
1146 arm,primecell-periphid = <0x00051180>;
1147 status = "disabled";
1148 reg = <0x12180000 0x2000>;
1149 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1150 interrupt-names = "cmd_irq";
1151 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
1152 clock-names = "mclk", "apb_pclk";
1156 max-frequency = <192000000>;
1158 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
1159 dma-names = "tx", "rx";
1162 sdcc4: mmc@121c0000 {
1163 compatible = "arm,pl18x", "arm,primecell";
1164 arm,primecell-periphid = <0x00051180>;
1165 status = "disabled";
1166 reg = <0x121c0000 0x2000>;
1167 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1168 interrupt-names = "cmd_irq";
1169 clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
1170 clock-names = "mclk", "apb_pclk";
1174 max-frequency = <48000000>;
1175 dmas = <&sdcc4bam 2>, <&sdcc4bam 1>;
1176 dma-names = "tx", "rx";
1177 pinctrl-names = "default";
1178 pinctrl-0 = <&sdc4_gpios>;
1182 tcsr: syscon@1a400000 {
1183 compatible = "qcom,tcsr-apq8064", "syscon";
1184 reg = <0x1a400000 0x100>;
1187 gpu: adreno-3xx@4300000 {
1188 compatible = "qcom,adreno-320.2", "qcom,adreno";
1189 reg = <0x04300000 0x20000>;
1190 reg-names = "kgsl_3d0_reg_memory";
1191 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
1192 interrupt-names = "kgsl_3d0_irq";
1200 <&mmcc GFX3D_AHB_CLK>,
1201 <&mmcc GFX3D_AXI_CLK>,
1202 <&mmcc MMSS_IMEM_AHB_CLK>;
1269 operating-points-v2 = <&gpu_opp_table>;
1271 gpu_opp_table: opp-table {
1272 compatible = "operating-points-v2";
1275 opp-hz = /bits/ 64 <450000000>;
1279 opp-hz = /bits/ 64 <27000000>;
1284 mmss_sfpb: syscon@5700000 {
1285 compatible = "syscon";
1286 reg = <0x5700000 0x70>;
1290 compatible = "qcom,mdss-dsi-ctrl";
1291 label = "MDSS DSI CTRL->0";
1292 #address-cells = <1>;
1294 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1295 reg = <0x04700000 0x200>;
1296 reg-names = "dsi_ctrl";
1298 clocks = <&mmcc DSI_M_AHB_CLK>,
1299 <&mmcc DSI_S_AHB_CLK>,
1300 <&mmcc AMP_AHB_CLK>,
1302 <&mmcc DSI1_BYTE_CLK>,
1303 <&mmcc DSI_PIXEL_CLK>,
1304 <&mmcc DSI1_ESC_CLK>;
1305 clock-names = "iface", "bus", "core_mmss",
1306 "src", "byte", "pixel",
1309 assigned-clocks = <&mmcc DSI1_BYTE_SRC>,
1310 <&mmcc DSI1_ESC_SRC>,
1312 <&mmcc DSI_PIXEL_SRC>;
1313 assigned-clock-parents = <&dsi0_phy 0>,
1317 syscon-sfpb = <&mmss_sfpb>;
1320 status = "disabled";
1323 #address-cells = <1>;
1334 dsi0_out: endpoint {
1341 dsi0_phy: dsi-phy@4700200 {
1342 compatible = "qcom,dsi-phy-28nm-8960";
1346 reg = <0x04700200 0x100>,
1349 reg-names = "dsi_pll", "dsi_phy", "dsi_phy_regulator";
1350 clock-names = "iface", "ref";
1351 clocks = <&mmcc DSI_M_AHB_CLK>,
1353 status = "disabled";
1357 mdp_port0: iommu@7500000 {
1358 compatible = "qcom,apq8064-iommu";
1364 <&mmcc SMMU_AHB_CLK>,
1365 <&mmcc MDP_AXI_CLK>;
1366 reg = <0x07500000 0x100000>;
1368 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
1369 <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
1373 mdp_port1: iommu@7600000 {
1374 compatible = "qcom,apq8064-iommu";
1380 <&mmcc SMMU_AHB_CLK>,
1381 <&mmcc MDP_AXI_CLK>;
1382 reg = <0x07600000 0x100000>;
1384 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
1385 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1389 gfx3d: iommu@7c00000 {
1390 compatible = "qcom,apq8064-iommu";
1396 <&mmcc SMMU_AHB_CLK>,
1397 <&mmcc GFX3D_AXI_CLK>;
1398 reg = <0x07c00000 0x100000>;
1400 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
1401 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1405 gfx3d1: iommu@7d00000 {
1406 compatible = "qcom,apq8064-iommu";
1412 <&mmcc SMMU_AHB_CLK>,
1413 <&mmcc GFX3D_AXI_CLK>;
1414 reg = <0x07d00000 0x100000>;
1416 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
1417 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
1421 pcie: pci@1b500000 {
1422 compatible = "qcom,pcie-apq8064";
1423 reg = <0x1b500000 0x1000>,
1426 <0x0ff00000 0x100000>;
1427 reg-names = "dbi", "elbi", "parf", "config";
1428 device_type = "pci";
1429 linux,pci-domain = <0>;
1430 bus-range = <0x00 0xff>;
1432 #address-cells = <3>;
1434 ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000>, /* I/O */
1435 <0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* mem */
1436 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
1437 interrupt-names = "msi";
1438 #interrupt-cells = <1>;
1439 interrupt-map-mask = <0 0 0 0x7>;
1440 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1441 <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1442 <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1443 <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1444 clocks = <&gcc PCIE_A_CLK>,
1446 <&gcc PCIE_PHY_REF_CLK>;
1447 clock-names = "core", "iface", "phy";
1448 resets = <&gcc PCIE_ACLK_RESET>,
1449 <&gcc PCIE_HCLK_RESET>,
1450 <&gcc PCIE_POR_RESET>,
1451 <&gcc PCIE_PCI_RESET>,
1452 <&gcc PCIE_PHY_RESET>;
1453 reset-names = "axi", "ahb", "por", "pci", "phy";
1454 status = "disabled";
1457 hdmi: hdmi-tx@4a00000 {
1458 compatible = "qcom,hdmi-tx-8960";
1459 pinctrl-names = "default";
1460 pinctrl-0 = <&hdmi_pinctrl>;
1461 reg = <0x04a00000 0x2f0>;
1462 reg-names = "core_physical";
1463 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
1464 clocks = <&mmcc HDMI_APP_CLK>,
1465 <&mmcc HDMI_M_AHB_CLK>,
1466 <&mmcc HDMI_S_AHB_CLK>;
1467 clock-names = "core",
1474 #address-cells = <1>;
1485 hdmi_out: endpoint {
1491 hdmi_phy: hdmi-phy@4a00400 {
1492 compatible = "qcom,hdmi-phy-8960";
1493 reg = <0x4a00400 0x60>,
1495 reg-names = "hdmi_phy",
1498 clocks = <&mmcc HDMI_S_AHB_CLK>;
1499 clock-names = "slave_iface";
1504 compatible = "qcom,mdp4";
1505 reg = <0x05100000 0xf0000>;
1506 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1507 clocks = <&mmcc MDP_CLK>,
1508 <&mmcc MDP_AHB_CLK>,
1509 <&mmcc MDP_AXI_CLK>,
1510 <&mmcc MDP_LUT_CLK>,
1511 <&mmcc HDMI_TV_CLK>,
1513 clock-names = "core_clk",
1520 iommus = <&mdp_port0 0
1526 #address-cells = <1>;
1531 mdp_lvds_out: endpoint {
1537 mdp_dsi1_out: endpoint {
1543 mdp_dsi2_out: endpoint {
1549 mdp_dtv_out: endpoint {
1555 riva: riva-pil@3204000 {
1556 compatible = "qcom,riva-pil";
1558 reg = <0x03200800 0x1000>, <0x03202000 0x2000>, <0x03204000 0x100>;
1559 reg-names = "ccu", "dxe", "pmu";
1561 interrupts-extended = <&intc GIC_SPI 199 IRQ_TYPE_EDGE_RISING>,
1562 <&wcnss_smsm 6 IRQ_TYPE_EDGE_RISING>;
1563 interrupt-names = "wdog", "fatal";
1565 memory-region = <&wcnss_mem>;
1567 vddcx-supply = <&pm8921_s3>;
1568 vddmx-supply = <&pm8921_l24>;
1569 vddpx-supply = <&pm8921_s4>;
1571 status = "disabled";
1574 compatible = "qcom,wcn3660";
1576 clocks = <&cxo_board>;
1579 vddxo-supply = <&pm8921_l4>;
1580 vddrfa-supply = <&pm8921_s2>;
1581 vddpa-supply = <&pm8921_l10>;
1582 vdddig-supply = <&pm8921_lvs2>;
1586 interrupts = <GIC_SPI 198 IRQ_TYPE_EDGE_RISING>;
1588 qcom,ipc = <&l2cc 8 25>;
1589 qcom,smd-edge = <6>;
1594 compatible = "qcom,wcnss";
1595 qcom,smd-channels = "WCNSS_CTRL";
1597 qcom,mmio = <&riva>;
1600 compatible = "qcom,wcnss-bt";
1604 compatible = "qcom,wcnss-wlan";
1606 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
1607 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
1608 interrupt-names = "tx", "rx";
1610 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
1611 qcom,smem-state-names = "tx-enable", "tx-rings-empty";
1618 compatible = "arm,coresight-etb10", "arm,primecell";
1619 reg = <0x1a01000 0x1000>;
1621 clocks = <&rpmcc RPM_QDSS_CLK>;
1622 clock-names = "apb_pclk";
1627 remote-endpoint = <&replicator_out0>;
1634 compatible = "arm,coresight-tpiu", "arm,primecell";
1635 reg = <0x1a03000 0x1000>;
1637 clocks = <&rpmcc RPM_QDSS_CLK>;
1638 clock-names = "apb_pclk";
1643 remote-endpoint = <&replicator_out1>;
1650 compatible = "arm,coresight-static-replicator";
1652 clocks = <&rpmcc RPM_QDSS_CLK>;
1653 clock-names = "apb_pclk";
1656 #address-cells = <1>;
1661 replicator_out0: endpoint {
1662 remote-endpoint = <&etb_in>;
1667 replicator_out1: endpoint {
1668 remote-endpoint = <&tpiu_in>;
1675 replicator_in: endpoint {
1676 remote-endpoint = <&funnel_out>;
1683 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1684 reg = <0x1a04000 0x1000>;
1686 clocks = <&rpmcc RPM_QDSS_CLK>;
1687 clock-names = "apb_pclk";
1690 #address-cells = <1>;
1694 * Not described input ports:
1695 * 2 - connected to STM component
1702 funnel_in0: endpoint {
1703 remote-endpoint = <&etm0_out>;
1708 funnel_in1: endpoint {
1709 remote-endpoint = <&etm1_out>;
1714 funnel_in4: endpoint {
1715 remote-endpoint = <&etm2_out>;
1720 funnel_in5: endpoint {
1721 remote-endpoint = <&etm3_out>;
1728 funnel_out: endpoint {
1729 remote-endpoint = <&replicator_in>;
1736 compatible = "arm,coresight-etm3x", "arm,primecell";
1737 reg = <0x1a1c000 0x1000>;
1739 clocks = <&rpmcc RPM_QDSS_CLK>;
1740 clock-names = "apb_pclk";
1746 etm0_out: endpoint {
1747 remote-endpoint = <&funnel_in0>;
1754 compatible = "arm,coresight-etm3x", "arm,primecell";
1755 reg = <0x1a1d000 0x1000>;
1757 clocks = <&rpmcc RPM_QDSS_CLK>;
1758 clock-names = "apb_pclk";
1764 etm1_out: endpoint {
1765 remote-endpoint = <&funnel_in1>;
1772 compatible = "arm,coresight-etm3x", "arm,primecell";
1773 reg = <0x1a1e000 0x1000>;
1775 clocks = <&rpmcc RPM_QDSS_CLK>;
1776 clock-names = "apb_pclk";
1782 etm2_out: endpoint {
1783 remote-endpoint = <&funnel_in4>;
1790 compatible = "arm,coresight-etm3x", "arm,primecell";
1791 reg = <0x1a1f000 0x1000>;
1793 clocks = <&rpmcc RPM_QDSS_CLK>;
1794 clock-names = "apb_pclk";
1800 etm3_out: endpoint {
1801 remote-endpoint = <&funnel_in5>;
1808 #include "qcom-apq8064-pins.dtsi"