3 #include "skeleton.dtsi"
4 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
5 #include <dt-bindings/reset/qcom,gcc-msm8960.h>
6 #include <dt-bindings/clock/qcom,mmcc-msm8960.h>
7 #include <dt-bindings/soc/qcom,gsbi.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 model = "Qualcomm APQ8064";
12 compatible = "qcom,apq8064";
13 interrupt-parent = <&intc>;
20 compatible = "qcom,krait";
21 enable-method = "qcom,kpss-acc-v1";
24 next-level-cache = <&L2>;
27 cpu-idle-states = <&CPU_SPC>;
31 compatible = "qcom,krait";
32 enable-method = "qcom,kpss-acc-v1";
35 next-level-cache = <&L2>;
38 cpu-idle-states = <&CPU_SPC>;
42 compatible = "qcom,krait";
43 enable-method = "qcom,kpss-acc-v1";
46 next-level-cache = <&L2>;
49 cpu-idle-states = <&CPU_SPC>;
53 compatible = "qcom,krait";
54 enable-method = "qcom,kpss-acc-v1";
57 next-level-cache = <&L2>;
60 cpu-idle-states = <&CPU_SPC>;
70 compatible = "qcom,idle-state-spc",
72 entry-latency-us = <400>;
73 exit-latency-us = <900>;
74 min-residency-us = <3000>;
80 compatible = "qcom,krait-pmu";
81 interrupts = <1 10 0x304>;
88 compatible = "simple-bus";
90 tlmm_pinmux: pinctrl@800000 {
91 compatible = "qcom,apq8064-pinctrl";
92 reg = <0x800000 0x4000>;
97 #interrupt-cells = <2>;
98 interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
100 pinctrl-names = "default";
101 pinctrl-0 = <&ps_hold>;
103 sdc4_gpios: sdc4-gpios {
105 pins = "gpio63", "gpio64", "gpio65", "gpio66", "gpio67", "gpio68";
113 function = "ps_hold";
119 pins = "gpio20", "gpio21";
126 pins = "gpio8", "gpio9";
131 gsbi6_uart_2pins: gsbi6_uart_2pins {
133 pins = "gpio14", "gpio15";
138 gsbi6_uart_4pins: gsbi6_uart_4pins {
140 pins = "gpio14", "gpio15", "gpio16", "gpio17";
145 gsbi7_uart_2pins: gsbi7_uart_2pins {
147 pins = "gpio82", "gpio83";
152 gsbi7_uart_4pins: gsbi7_uart_4pins {
154 pins = "gpio82", "gpio83", "gpio84", "gpio85";
160 intc: interrupt-controller@2000000 {
161 compatible = "qcom,msm-qgic2";
162 interrupt-controller;
163 #interrupt-cells = <3>;
164 reg = <0x02000000 0x1000>,
169 compatible = "qcom,kpss-timer", "qcom,msm-timer";
170 interrupts = <1 1 0x301>,
173 reg = <0x0200a000 0x100>;
174 clock-frequency = <27000000>,
176 cpu-offset = <0x80000>;
179 acc0: clock-controller@2088000 {
180 compatible = "qcom,kpss-acc-v1";
181 reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
184 acc1: clock-controller@2098000 {
185 compatible = "qcom,kpss-acc-v1";
186 reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
189 acc2: clock-controller@20a8000 {
190 compatible = "qcom,kpss-acc-v1";
191 reg = <0x020a8000 0x1000>, <0x02008000 0x1000>;
194 acc3: clock-controller@20b8000 {
195 compatible = "qcom,kpss-acc-v1";
196 reg = <0x020b8000 0x1000>, <0x02008000 0x1000>;
199 saw0: power-controller@2089000 {
200 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
201 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
205 saw1: power-controller@2099000 {
206 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
207 reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
211 saw2: power-controller@20a9000 {
212 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
213 reg = <0x020a9000 0x1000>, <0x02009000 0x1000>;
217 saw3: power-controller@20b9000 {
218 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
219 reg = <0x020b9000 0x1000>, <0x02009000 0x1000>;
223 gsbi1: gsbi@12440000 {
225 compatible = "qcom,gsbi-v1.0.0";
227 reg = <0x12440000 0x100>;
228 clocks = <&gcc GSBI1_H_CLK>;
229 clock-names = "iface";
230 #address-cells = <1>;
234 syscon-tcsr = <&tcsr>;
237 compatible = "qcom,i2c-qup-v1.1.1";
238 pinctrl-0 = <&i2c1_pins>;
239 pinctrl-names = "default";
240 reg = <0x12460000 0x1000>;
241 interrupts = <0 194 IRQ_TYPE_NONE>;
242 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
243 clock-names = "core", "iface";
244 #address-cells = <1>;
249 gsbi2: gsbi@12480000 {
251 compatible = "qcom,gsbi-v1.0.0";
253 reg = <0x12480000 0x100>;
254 clocks = <&gcc GSBI2_H_CLK>;
255 clock-names = "iface";
256 #address-cells = <1>;
260 syscon-tcsr = <&tcsr>;
263 compatible = "qcom,i2c-qup-v1.1.1";
264 reg = <0x124a0000 0x1000>;
265 interrupts = <0 196 IRQ_TYPE_NONE>;
266 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
267 clock-names = "core", "iface";
268 #address-cells = <1>;
273 gsbi3: gsbi@16200000 {
275 compatible = "qcom,gsbi-v1.0.0";
277 reg = <0x16200000 0x100>;
278 clocks = <&gcc GSBI3_H_CLK>;
279 clock-names = "iface";
280 #address-cells = <1>;
284 compatible = "qcom,i2c-qup-v1.1.1";
285 pinctrl-0 = <&i2c3_pins>;
286 pinctrl-names = "default";
287 reg = <0x16280000 0x1000>;
288 interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>;
289 clocks = <&gcc GSBI3_QUP_CLK>,
291 clock-names = "core", "iface";
295 gsbi6: gsbi@16500000 {
297 compatible = "qcom,gsbi-v1.0.0";
299 reg = <0x16500000 0x03>;
300 clocks = <&gcc GSBI6_H_CLK>;
301 clock-names = "iface";
302 #address-cells = <1>;
306 gsbi6_serial: serial@16540000 {
307 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
308 reg = <0x16540000 0x100>,
310 interrupts = <0 156 0x0>;
311 clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>;
312 clock-names = "core", "iface";
317 gsbi7: gsbi@16600000 {
319 compatible = "qcom,gsbi-v1.0.0";
321 reg = <0x16600000 0x100>;
322 clocks = <&gcc GSBI7_H_CLK>;
323 clock-names = "iface";
324 #address-cells = <1>;
327 syscon-tcsr = <&tcsr>;
329 gsbi7_serial: serial@16640000 {
330 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
331 reg = <0x16640000 0x1000>,
333 interrupts = <0 158 0x0>;
334 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
335 clock-names = "core", "iface";
341 compatible = "qcom,ssbi";
342 reg = <0x00500000 0x1000>;
343 qcom,controller-type = "pmic-arbiter";
346 compatible = "qcom,pm8921";
347 interrupt-parent = <&tlmm_pinmux>;
349 #interrupt-cells = <2>;
350 interrupt-controller;
351 #address-cells = <1>;
354 pm8921_gpio: gpio@150 {
356 compatible = "qcom,pm8921-gpio";
358 interrupts = <192 IRQ_TYPE_NONE>,
407 pm8921_mpps: mpps@50 {
408 compatible = "qcom,pm8921-mpp";
428 compatible = "qcom,pm8921-rtc";
429 interrupt-parent = <&pmicintc>;
436 compatible = "qcom,pm8921-pwrkey";
438 interrupt-parent = <&pmicintc>;
439 interrupts = <50 1>, <51 1>;
446 gcc: clock-controller@900000 {
447 compatible = "qcom,gcc-apq8064";
448 reg = <0x00900000 0x4000>;
453 lcc: clock-controller@28000000 {
454 compatible = "qcom,lcc-apq8064";
455 reg = <0x28000000 0x1000>;
460 mmcc: clock-controller@4000000 {
461 compatible = "qcom,mmcc-apq8064";
462 reg = <0x4000000 0x1000>;
467 l2cc: clock-controller@2011000 {
468 compatible = "syscon";
469 reg = <0x2011000 0x1000>;
473 compatible = "qcom,rpm-apq8064";
474 reg = <0x108000 0x1000>;
475 qcom,ipc = <&l2cc 0x8 2>;
477 interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
478 <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
479 <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
480 interrupt-names = "ack", "err", "wakeup";
483 compatible = "qcom,rpm-pm8921-regulators";
485 pm8921_hdmi_switch: hdmi-switch {
491 usb1_phy: phy@12500000 {
492 compatible = "qcom,usb-otg-ci";
493 reg = <0x12500000 0x400>;
494 interrupts = <GIC_SPI 100 IRQ_TYPE_NONE>;
498 clocks = <&gcc USB_HS1_XCVR_CLK>,
499 <&gcc USB_HS1_H_CLK>;
500 clock-names = "core", "iface";
502 resets = <&gcc USB_HS1_RESET>;
503 reset-names = "link";
506 usb3_phy: phy@12520000 {
507 compatible = "qcom,usb-otg-ci";
508 reg = <0x12520000 0x400>;
509 interrupts = <GIC_SPI 188 IRQ_TYPE_NONE>;
513 clocks = <&gcc USB_HS3_XCVR_CLK>,
514 <&gcc USB_HS3_H_CLK>;
515 clock-names = "core", "iface";
517 resets = <&gcc USB_HS3_RESET>;
518 reset-names = "link";
521 usb4_phy: phy@12530000 {
522 compatible = "qcom,usb-otg-ci";
523 reg = <0x12530000 0x400>;
524 interrupts = <GIC_SPI 215 IRQ_TYPE_NONE>;
528 clocks = <&gcc USB_HS4_XCVR_CLK>,
529 <&gcc USB_HS4_H_CLK>;
530 clock-names = "core", "iface";
532 resets = <&gcc USB_HS4_RESET>;
533 reset-names = "link";
536 gadget1: gadget@12500000 {
537 compatible = "qcom,ci-hdrc";
538 reg = <0x12500000 0x400>;
540 dr_mode = "peripheral";
541 interrupts = <GIC_SPI 100 IRQ_TYPE_NONE>;
542 usb-phy = <&usb1_phy>;
546 compatible = "qcom,ehci-host";
547 reg = <0x12500000 0x400>;
548 interrupts = <GIC_SPI 100 IRQ_TYPE_NONE>;
550 usb-phy = <&usb1_phy>;
554 compatible = "qcom,ehci-host";
555 reg = <0x12520000 0x400>;
556 interrupts = <GIC_SPI 188 IRQ_TYPE_NONE>;
558 usb-phy = <&usb3_phy>;
562 compatible = "qcom,ehci-host";
563 reg = <0x12530000 0x400>;
564 interrupts = <GIC_SPI 215 IRQ_TYPE_NONE>;
566 usb-phy = <&usb4_phy>;
569 sata_phy0: phy@1b400000 {
570 compatible = "qcom,apq8064-sata-phy";
572 reg = <0x1b400000 0x200>;
573 reg-names = "phy_mem";
574 clocks = <&gcc SATA_PHY_CFG_CLK>;
579 sata0: sata@29000000 {
580 compatible = "qcom,apq8064-ahci", "generic-ahci";
582 reg = <0x29000000 0x180>;
583 interrupts = <GIC_SPI 209 IRQ_TYPE_NONE>;
585 clocks = <&gcc SFAB_SATA_S_H_CLK>,
588 <&gcc SATA_RXOOB_CLK>,
589 <&gcc SATA_PMALIVE_CLK>;
590 clock-names = "slave_iface",
596 assigned-clocks = <&gcc SATA_RXOOB_CLK>,
597 <&gcc SATA_PMALIVE_CLK>;
598 assigned-clock-rates = <100000000>, <100000000>;
601 phy-names = "sata-phy";
602 ports-implemented = <0x1>;
605 /* Temporary fixed regulator */
606 sdcc1bam:dma@12402000{
607 compatible = "qcom,bam-v1.3.0";
608 reg = <0x12402000 0x8000>;
609 interrupts = <0 98 0>;
610 clocks = <&gcc SDC1_H_CLK>;
611 clock-names = "bam_clk";
616 sdcc3bam:dma@12182000{
617 compatible = "qcom,bam-v1.3.0";
618 reg = <0x12182000 0x8000>;
619 interrupts = <0 96 0>;
620 clocks = <&gcc SDC3_H_CLK>;
621 clock-names = "bam_clk";
626 sdcc4bam:dma@121c2000{
627 compatible = "qcom,bam-v1.3.0";
628 reg = <0x121c2000 0x8000>;
629 interrupts = <0 95 0>;
630 clocks = <&gcc SDC4_H_CLK>;
631 clock-names = "bam_clk";
637 compatible = "arm,amba-bus";
638 #address-cells = <1>;
641 sdcc1: sdcc@12400000 {
643 compatible = "arm,pl18x", "arm,primecell";
644 arm,primecell-periphid = <0x00051180>;
645 reg = <0x12400000 0x2000>;
646 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
647 interrupt-names = "cmd_irq";
648 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
649 clock-names = "mclk", "apb_pclk";
651 max-frequency = <96000000>;
655 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
656 dma-names = "tx", "rx";
659 sdcc3: sdcc@12180000 {
660 compatible = "arm,pl18x", "arm,primecell";
661 arm,primecell-periphid = <0x00051180>;
663 reg = <0x12180000 0x2000>;
664 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
665 interrupt-names = "cmd_irq";
666 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
667 clock-names = "mclk", "apb_pclk";
671 max-frequency = <192000000>;
673 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
674 dma-names = "tx", "rx";
677 sdcc4: sdcc@121c0000 {
678 compatible = "arm,pl18x", "arm,primecell";
679 arm,primecell-periphid = <0x00051180>;
681 reg = <0x121c0000 0x2000>;
682 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
683 interrupt-names = "cmd_irq";
684 clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
685 clock-names = "mclk", "apb_pclk";
689 max-frequency = <48000000>;
690 dmas = <&sdcc4bam 2>, <&sdcc4bam 1>;
691 dma-names = "tx", "rx";
692 pinctrl-names = "default";
693 pinctrl-0 = <&sdc4_gpios>;
697 tcsr: syscon@1a400000 {
698 compatible = "qcom,tcsr-apq8064", "syscon";
699 reg = <0x1a400000 0x100>;