arch/arm/boot/dts/qcom-apq8064.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /dts-v1/;
   3
   4 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
   5 #include <dt-bindings/clock/qcom,lcc-msm8960.h>
   6 #include <dt-bindings/reset/qcom,gcc-msm8960.h>
   7 #include <dt-bindings/clock/qcom,mmcc-msm8960.h>
   8 #include <dt-bindings/clock/qcom,rpmcc.h>
   9 #include <dt-bindings/soc/qcom,gsbi.h>
  10 #include <dt-bindings/interrupt-controller/irq.h>
  11 #include <dt-bindings/interrupt-controller/arm-gic.h>
  12 / {
  13         #address-cells = <1>;
  14         #size-cells = <1>;
  15         model = "Qualcomm APQ8064";
  16         compatible = "qcom,apq8064";
  17         interrupt-parent = <&intc>;
  18
  19         reserved-memory {
  20                 #address-cells = <1>;
  21                 #size-cells = <1>;
  22                 ranges;
  23
  24                 smem_region: smem@80000000 {
  25                         reg = <0x80000000 0x200000>;
  26                         no-map;
  27                 };
  28
  29                 wcnss_mem: wcnss@8f000000 {
  30                         reg = <0x8f000000 0x700000>;
  31                         no-map;
  32                 };
  33         };
  34
  35         cpus {
  36                 #address-cells = <1>;
  37                 #size-cells = <0>;
  38
  39                 CPU0: cpu@0 {
  40                         compatible = "qcom,krait";
  41                         enable-method = "qcom,kpss-acc-v1";
  42                         device_type = "cpu";
  43                         reg = <0>;
  44                         next-level-cache = <&L2>;
  45                         qcom,acc = <&acc0>;
  46                         qcom,saw = <&saw0>;
  47                         cpu-idle-states = <&CPU_SPC>;
  48                 };
  49
  50                 CPU1: cpu@1 {
  51                         compatible = "qcom,krait";
  52                         enable-method = "qcom,kpss-acc-v1";
  53                         device_type = "cpu";
  54                         reg = <1>;
  55                         next-level-cache = <&L2>;
  56                         qcom,acc = <&acc1>;
  57                         qcom,saw = <&saw1>;
  58                         cpu-idle-states = <&CPU_SPC>;
  59                 };
  60
  61                 CPU2: cpu@2 {
  62                         compatible = "qcom,krait";
  63                         enable-method = "qcom,kpss-acc-v1";
  64                         device_type = "cpu";
  65                         reg = <2>;
  66                         next-level-cache = <&L2>;
  67                         qcom,acc = <&acc2>;
  68                         qcom,saw = <&saw2>;
  69                         cpu-idle-states = <&CPU_SPC>;
  70                 };
  71
  72                 CPU3: cpu@3 {
  73                         compatible = "qcom,krait";
  74                         enable-method = "qcom,kpss-acc-v1";
  75                         device_type = "cpu";
  76                         reg = <3>;
  77                         next-level-cache = <&L2>;
  78                         qcom,acc = <&acc3>;
  79                         qcom,saw = <&saw3>;
  80                         cpu-idle-states = <&CPU_SPC>;
  81                 };
  82
  83                 L2: l2-cache {
  84                         compatible = "cache";
  85                         cache-level = <2>;
  86                 };
  87
  88                 idle-states {
  89                         CPU_SPC: spc {
  90                                 compatible = "qcom,idle-state-spc",
  91                                                 "arm,idle-state";
  92                                 entry-latency-us = <400>;
  93                                 exit-latency-us = <900>;
  94                                 min-residency-us = <3000>;
  95                         };
  96                 };
  97         };
  98
  99         memory@0 {
 100                 device_type = "memory";
 101                 reg = <0x0 0x0>;
 102         };
 103
 104         thermal-zones {
 105                 cpu0-thermal {
 106                         polling-delay-passive = <250>;
 107                         polling-delay = <1000>;
 108
 109                         thermal-sensors = <&tsens 7>;
 110                         coefficients = <1199 0>;
 111
 112                         trips {
 113                                 cpu_alert0: trip0 {
 114                                         temperature = <75000>;
 115                                         hysteresis = <2000>;
 116                                         type = "passive";
 117                                 };
 118                                 cpu_crit0: trip1 {
 119                                         temperature = <110000>;
 120                                         hysteresis = <2000>;
 121                                         type = "critical";
 122                                 };
 123                         };
 124                 };
 125
 126                 cpu1-thermal {
 127                         polling-delay-passive = <250>;
 128                         polling-delay = <1000>;
 129
 130                         thermal-sensors = <&tsens 8>;
 131                         coefficients = <1132 0>;
 132
 133                         trips {
 134                                 cpu_alert1: trip0 {
 135                                         temperature = <75000>;
 136                                         hysteresis = <2000>;
 137                                         type = "passive";
 138                                 };
 139                                 cpu_crit1: trip1 {
 140                                         temperature = <110000>;
 141                                         hysteresis = <2000>;
 142                                         type = "critical";
 143                                 };
 144                         };
 145                 };
 146
 147                 cpu2-thermal {
 148                         polling-delay-passive = <250>;
 149                         polling-delay = <1000>;
 150
 151                         thermal-sensors = <&tsens 9>;
 152                         coefficients = <1199 0>;
 153
 154                         trips {
 155                                 cpu_alert2: trip0 {
 156                                         temperature = <75000>;
 157                                         hysteresis = <2000>;
 158                                         type = "passive";
 159                                 };
 160                                 cpu_crit2: trip1 {
 161                                         temperature = <110000>;
 162                                         hysteresis = <2000>;
 163                                         type = "critical";
 164                                 };
 165                         };
 166                 };
 167
 168                 cpu3-thermal {
 169                         polling-delay-passive = <250>;
 170                         polling-delay = <1000>;
 171
 172                         thermal-sensors = <&tsens 10>;
 173                         coefficients = <1132 0>;
 174
 175                         trips {
 176                                 cpu_alert3: trip0 {
 177                                         temperature = <75000>;
 178                                         hysteresis = <2000>;
 179                                         type = "passive";
 180                                 };
 181                                 cpu_crit3: trip1 {
 182                                         temperature = <110000>;
 183                                         hysteresis = <2000>;
 184                                         type = "critical";
 185                                 };
 186                         };
 187                 };
 188         };
 189
 190         cpu-pmu {
 191                 compatible = "qcom,krait-pmu";
 192                 interrupts = <1 10 0x304>;
 193         };
 194
 195         clocks {
 196                 cxo_board: cxo_board {
 197                         compatible = "fixed-clock";
 198                         #clock-cells = <0>;
 199                         clock-frequency = <19200000>;
 200                 };
 201
 202                 pxo_board: pxo_board {
 203                         compatible = "fixed-clock";
 204                         #clock-cells = <0>;
 205                         clock-frequency = <27000000>;
 206                 };
 207
 208                 sleep_clk: sleep_clk {
 209                         compatible = "fixed-clock";
 210                         #clock-cells = <0>;
 211                         clock-frequency = <32768>;
 212                 };
 213         };
 214
 215         sfpb_mutex: hwmutex {
 216                 compatible = "qcom,sfpb-mutex";
 217                 syscon = <&sfpb_wrapper_mutex 0x604 0x4>;
 218                 #hwlock-cells = <1>;
 219         };
 220
 221         smem {
 222                 compatible = "qcom,smem";
 223                 memory-region = <&smem_region>;
 224
 225                 hwlocks = <&sfpb_mutex 3>;
 226         };
 227
 228         smd {
 229                 compatible = "qcom,smd";
 230
 231                 modem-edge {
 232                         interrupts = <0 37 IRQ_TYPE_EDGE_RISING>;
 233
 234                         qcom,ipc = <&l2cc 8 3>;
 235                         qcom,smd-edge = <0>;
 236
 237                         status = "disabled";
 238                 };
 239
 240                 q6-edge {
 241                         interrupts = <0 90 IRQ_TYPE_EDGE_RISING>;
 242
 243                         qcom,ipc = <&l2cc 8 15>;
 244                         qcom,smd-edge = <1>;
 245
 246                         status = "disabled";
 247                 };
 248
 249                 dsps-edge {
 250                         interrupts = <0 138 IRQ_TYPE_EDGE_RISING>;
 251
 252                         qcom,ipc = <&sps_sic_non_secure 0x4080 0>;
 253                         qcom,smd-edge = <3>;
 254
 255                         status = "disabled";
 256                 };
 257
 258                 riva-edge {
 259                         interrupts = <0 198 IRQ_TYPE_EDGE_RISING>;
 260
 261                         qcom,ipc = <&l2cc 8 25>;
 262                         qcom,smd-edge = <6>;
 263
 264                         status = "disabled";
 265                 };
 266         };
 267
 268         smsm {
 269                 compatible = "qcom,smsm";
 270
 271                 #address-cells = <1>;
 272                 #size-cells = <0>;
 273
 274                 qcom,ipc-1 = <&l2cc 8 4>;
 275                 qcom,ipc-2 = <&l2cc 8 14>;
 276                 qcom,ipc-3 = <&l2cc 8 23>;
 277                 qcom,ipc-4 = <&sps_sic_non_secure 0x4094 0>;
 278
 279                 apps_smsm: apps@0 {
 280                         reg = <0>;
 281                         #qcom,smem-state-cells = <1>;
 282                 };
 283
 284                 modem_smsm: modem@1 {
 285                         reg = <1>;
 286                         interrupts = <0 38 IRQ_TYPE_EDGE_RISING>;
 287
 288                         interrupt-controller;
 289                         #interrupt-cells = <2>;
 290                 };
 291
 292                 q6_smsm: q6@2 {
 293                         reg = <2>;
 294                         interrupts = <0 89 IRQ_TYPE_EDGE_RISING>;
 295
 296                         interrupt-controller;
 297                         #interrupt-cells = <2>;
 298                 };
 299
 300                 wcnss_smsm: wcnss@3 {
 301                         reg = <3>;
 302                         interrupts = <0 204 IRQ_TYPE_EDGE_RISING>;
 303
 304                         interrupt-controller;
 305                         #interrupt-cells = <2>;
 306                 };
 307
 308                 dsps_smsm: dsps@4 {
 309                         reg = <4>;
 310                         interrupts = <0 137 IRQ_TYPE_EDGE_RISING>;
 311
 312                         interrupt-controller;
 313                         #interrupt-cells = <2>;
 314                 };
 315         };
 316
 317         firmware {
 318                 scm {
 319                         compatible = "qcom,scm-apq8064", "qcom,scm";
 320
 321                         clocks = <&rpmcc RPM_DAYTONA_FABRIC_CLK>;
 322                         clock-names = "core";
 323                 };
 324         };
 325
 326
 327         /*
 328          * These channels from the ADC are simply hardware monitors.
 329          * That is why the ADC is referred to as "HKADC" - HouseKeeping
 330          * ADC.
 331          */
 332         iio-hwmon {
 333                 compatible = "iio-hwmon";
 334                 io-channels = <&xoadc 0x00 0x01>, /* Battery */
 335                             <&xoadc 0x00 0x02>, /* DC in (charger) */
 336                             <&xoadc 0x00 0x04>, /* VPH the main system voltage */
 337                             <&xoadc 0x00 0x0b>, /* Die temperature */
 338                             <&xoadc 0x00 0x0c>, /* Reference voltage 1.25V */
 339                             <&xoadc 0x00 0x0d>, /* Reference voltage 0.625V */
 340                             <&xoadc 0x00 0x0e>; /* Charger temperature */
 341         };
 342
 343         soc: soc {
 344                 #address-cells = <1>;
 345                 #size-cells = <1>;
 346                 ranges;
 347                 compatible = "simple-bus";
 348
 349                 tlmm_pinmux: pinctrl@800000 {
 350                         compatible = "qcom,apq8064-pinctrl";
 351                         reg = <0x800000 0x4000>;
 352
 353                         gpio-controller;
 354                         gpio-ranges = <&tlmm_pinmux 0 0 90>;
 355                         #gpio-cells = <2>;
 356                         interrupt-controller;
 357                         #interrupt-cells = <2>;
 358                         interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
 359
 360                         pinctrl-names = "default";
 361                         pinctrl-0 = <&ps_hold>;
 362                 };
 363
 364                 sfpb_wrapper_mutex: syscon@1200000 {
 365                         compatible = "syscon";
 366                         reg = <0x01200000 0x8000>;
 367                 };
 368
 369                 intc: interrupt-controller@2000000 {
 370                         compatible = "qcom,msm-qgic2";
 371                         interrupt-controller;
 372                         #interrupt-cells = <3>;
 373                         reg = <0x02000000 0x1000>,
 374                               <0x02002000 0x1000>;
 375                 };
 376
 377                 timer@200a000 {
 378                         compatible = "qcom,kpss-timer",
 379                                      "qcom,kpss-wdt-apq8064", "qcom,msm-timer";
 380                         interrupts = <1 1 0x301>,
 381                                      <1 2 0x301>,
 382                                      <1 3 0x301>;
 383                         reg = <0x0200a000 0x100>;
 384                         clock-frequency = <27000000>,
 385                                           <32768>;
 386                         cpu-offset = <0x80000>;
 387                 };
 388
 389                 acc0: clock-controller@2088000 {
 390                         compatible = "qcom,kpss-acc-v1";
 391                         reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
 392                 };
 393
 394                 acc1: clock-controller@2098000 {
 395                         compatible = "qcom,kpss-acc-v1";
 396                         reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
 397                 };
 398
 399                 acc2: clock-controller@20a8000 {
 400                         compatible = "qcom,kpss-acc-v1";
 401                         reg = <0x020a8000 0x1000>, <0x02008000 0x1000>;
 402                 };
 403
 404                 acc3: clock-controller@20b8000 {
 405                         compatible = "qcom,kpss-acc-v1";
 406                         reg = <0x020b8000 0x1000>, <0x02008000 0x1000>;
 407                 };
 408
 409                 saw0: power-controller@2089000 {
 410                         compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
 411                         reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
 412                         regulator;
 413                 };
 414
 415                 saw1: power-controller@2099000 {
 416                         compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
 417                         reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
 418                         regulator;
 419                 };
 420
 421                 saw2: power-controller@20a9000 {
 422                         compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
 423                         reg = <0x020a9000 0x1000>, <0x02009000 0x1000>;
 424                         regulator;
 425                 };
 426
 427                 saw3: power-controller@20b9000 {
 428                         compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
 429                         reg = <0x020b9000 0x1000>, <0x02009000 0x1000>;
 430                         regulator;
 431                 };
 432
 433                 sps_sic_non_secure: sps-sic-non-secure@12100000 {
 434                         compatible = "syscon";
 435                         reg = <0x12100000 0x10000>;
 436                 };
 437
 438                 gsbi1: gsbi@12440000 {
 439                         status = "disabled";
 440                         compatible = "qcom,gsbi-v1.0.0";
 441                         cell-index = <1>;
 442                         reg = <0x12440000 0x100>;
 443                         clocks = <&gcc GSBI1_H_CLK>;
 444                         clock-names = "iface";
 445                         #address-cells = <1>;
 446                         #size-cells = <1>;
 447                         ranges;
 448
 449                         syscon-tcsr = <&tcsr>;
 450
 451                         gsbi1_serial: serial@12450000 {
 452                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 453                                 reg = <0x12450000 0x100>,
 454                                       <0x12400000 0x03>;
 455                                 interrupts = <0 193 IRQ_TYPE_LEVEL_HIGH>;
 456                                 clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
 457                                 clock-names = "core", "iface";
 458                                 status = "disabled";
 459                         };
 460
 461                         gsbi1_i2c: i2c@12460000 {
 462                                 compatible = "qcom,i2c-qup-v1.1.1";
 463                                 pinctrl-0 = <&i2c1_pins>;
 464                                 pinctrl-1 = <&i2c1_pins_sleep>;
 465                                 pinctrl-names = "default", "sleep";
 466                                 reg = <0x12460000 0x1000>;
 467                                 interrupts = <0 194 IRQ_TYPE_LEVEL_HIGH>;
 468                                 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
 469                                 clock-names = "core", "iface";
 470                                 #address-cells = <1>;
 471                                 #size-cells = <0>;
 472                                 status = "disabled";
 473                         };
 474
 475                 };
 476
 477                 gsbi2: gsbi@12480000 {
 478                         status = "disabled";
 479                         compatible = "qcom,gsbi-v1.0.0";
 480                         cell-index = <2>;
 481                         reg = <0x12480000 0x100>;
 482                         clocks = <&gcc GSBI2_H_CLK>;
 483                         clock-names = "iface";
 484                         #address-cells = <1>;
 485                         #size-cells = <1>;
 486                         ranges;
 487
 488                         syscon-tcsr = <&tcsr>;
 489
 490                         gsbi2_i2c: i2c@124a0000 {
 491                                 compatible = "qcom,i2c-qup-v1.1.1";
 492                                 reg = <0x124a0000 0x1000>;
 493                                 pinctrl-0 = <&i2c2_pins>;
 494                                 pinctrl-1 = <&i2c2_pins_sleep>;
 495                                 pinctrl-names = "default", "sleep";
 496                                 interrupts = <0 196 IRQ_TYPE_LEVEL_HIGH>;
 497                                 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
 498                                 clock-names = "core", "iface";
 499                                 #address-cells = <1>;
 500                                 #size-cells = <0>;
 501                                 status = "disabled";
 502                         };
 503                 };
 504
 505                 gsbi3: gsbi@16200000 {
 506                         status = "disabled";
 507                         compatible = "qcom,gsbi-v1.0.0";
 508                         cell-index = <3>;
 509                         reg = <0x16200000 0x100>;
 510                         clocks = <&gcc GSBI3_H_CLK>;
 511                         clock-names = "iface";
 512                         #address-cells = <1>;
 513                         #size-cells = <1>;
 514                         ranges;
 515                         gsbi3_i2c: i2c@16280000 {
 516                                 compatible = "qcom,i2c-qup-v1.1.1";
 517                                 pinctrl-0 = <&i2c3_pins>;
 518                                 pinctrl-1 = <&i2c3_pins_sleep>;
 519                                 pinctrl-names = "default", "sleep";
 520                                 reg = <0x16280000 0x1000>;
 521                                 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
 522                                 clocks = <&gcc GSBI3_QUP_CLK>,
 523                                          <&gcc GSBI3_H_CLK>;
 524                                 clock-names = "core", "iface";
 525                                 #address-cells = <1>;
 526                                 #size-cells = <0>;
 527                                 status = "disabled";
 528                         };
 529                 };
 530
 531                 gsbi4: gsbi@16300000 {
 532                         status = "disabled";
 533                         compatible = "qcom,gsbi-v1.0.0";
 534                         cell-index = <4>;
 535                         reg = <0x16300000 0x03>;
 536                         clocks = <&gcc GSBI4_H_CLK>;
 537                         clock-names = "iface";
 538                         #address-cells = <1>;
 539                         #size-cells = <1>;
 540                         ranges;
 541
 542                         gsbi4_i2c: i2c@16380000 {
 543                                 compatible = "qcom,i2c-qup-v1.1.1";
 544                                 pinctrl-0 = <&i2c4_pins>;
 545                                 pinctrl-1 = <&i2c4_pins_sleep>;
 546                                 pinctrl-names = "default", "sleep";
 547                                 reg = <0x16380000 0x1000>;
 548                                 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
 549                                 clocks = <&gcc GSBI4_QUP_CLK>,
 550                                          <&gcc GSBI4_H_CLK>;
 551                                 clock-names = "core", "iface";
 552                                 status = "disabled";
 553                         };
 554                 };
 555
 556                 gsbi5: gsbi@1a200000 {
 557                         status = "disabled";
 558                         compatible = "qcom,gsbi-v1.0.0";
 559                         cell-index = <5>;
 560                         reg = <0x1a200000 0x03>;
 561                         clocks = <&gcc GSBI5_H_CLK>;
 562                         clock-names = "iface";
 563                         #address-cells = <1>;
 564                         #size-cells = <1>;
 565                         ranges;
 566
 567                         gsbi5_serial: serial@1a240000 {
 568                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 569                                 reg = <0x1a240000 0x100>,
 570                                       <0x1a200000 0x03>;
 571                                 interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>;
 572                                 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
 573                                 clock-names = "core", "iface";
 574                                 status = "disabled";
 575                         };
 576
 577                         gsbi5_spi: spi@1a280000 {
 578                                 compatible = "qcom,spi-qup-v1.1.1";
 579                                 reg = <0x1a280000 0x1000>;
 580                                 interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>;
 581                                 pinctrl-0 = <&spi5_default>;
 582                                 pinctrl-1 = <&spi5_sleep>;
 583                                 pinctrl-names = "default", "sleep";
 584                                 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
 585                                 clock-names = "core", "iface";
 586                                 status = "disabled";
 587                                 #address-cells = <1>;
 588                                 #size-cells = <0>;
 589                         };
 590                 };
 591
 592                 gsbi6: gsbi@16500000 {
 593                         status = "disabled";
 594                         compatible = "qcom,gsbi-v1.0.0";
 595                         cell-index = <6>;
 596                         reg = <0x16500000 0x03>;
 597                         clocks = <&gcc GSBI6_H_CLK>;
 598                         clock-names = "iface";
 599                         #address-cells = <1>;
 600                         #size-cells = <1>;
 601                         ranges;
 602
 603                         gsbi6_serial: serial@16540000 {
 604                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 605                                 reg = <0x16540000 0x100>,
 606                                       <0x16500000 0x03>;
 607                                 interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
 608                                 clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>;
 609                                 clock-names = "core", "iface";
 610                                 status = "disabled";
 611                         };
 612
 613                         gsbi6_i2c: i2c@16580000 {
 614                                 compatible = "qcom,i2c-qup-v1.1.1";
 615                                 pinctrl-0 = <&i2c6_pins>;
 616                                 pinctrl-1 = <&i2c6_pins_sleep>;
 617                                 pinctrl-names = "default", "sleep";
 618                                 reg = <0x16580000 0x1000>;
 619                                 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
 620                                 clocks = <&gcc GSBI6_QUP_CLK>,
 621                                          <&gcc GSBI6_H_CLK>;
 622                                 clock-names = "core", "iface";
 623                                 status = "disabled";
 624                         };
 625                 };
 626
 627                 gsbi7: gsbi@16600000 {
 628                         status = "disabled";
 629                         compatible = "qcom,gsbi-v1.0.0";
 630                         cell-index = <7>;
 631                         reg = <0x16600000 0x100>;
 632                         clocks = <&gcc GSBI7_H_CLK>;
 633                         clock-names = "iface";
 634                         #address-cells = <1>;
 635                         #size-cells = <1>;
 636                         ranges;
 637                         syscon-tcsr = <&tcsr>;
 638
 639                         gsbi7_serial: serial@16640000 {
 640                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 641                                 reg = <0x16640000 0x1000>,
 642                                       <0x16600000 0x1000>;
 643                                 interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>;
 644                                 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
 645                                 clock-names = "core", "iface";
 646                                 status = "disabled";
 647                         };
 648
 649                         gsbi7_i2c: i2c@16680000 {
 650                                 compatible = "qcom,i2c-qup-v1.1.1";
 651                                 pinctrl-0 = <&i2c7_pins>;
 652                                 pinctrl-1 = <&i2c7_pins_sleep>;
 653                                 pinctrl-names = "default", "sleep";
 654                                 reg = <0x16680000 0x1000>;
 655                                 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
 656                                 clocks = <&gcc GSBI7_QUP_CLK>,
 657                                          <&gcc GSBI7_H_CLK>;
 658                                 clock-names = "core", "iface";
 659                                 status = "disabled";
 660                         };
 661                 };
 662
 663                 rng@1a500000 {
 664                         compatible = "qcom,prng";
 665                         reg = <0x1a500000 0x200>;
 666                         clocks = <&gcc PRNG_CLK>;
 667                         clock-names = "core";
 668                 };
 669
 670                 ssbi@c00000 {
 671                         compatible = "qcom,ssbi";
 672                         reg = <0x00c00000 0x1000>;
 673                         qcom,controller-type = "pmic-arbiter";
 674
 675                         pm8821: pmic@1 {
 676                                 compatible = "qcom,pm8821";
 677                                 interrupt-parent = <&tlmm_pinmux>;
 678                                 interrupts = <76 IRQ_TYPE_LEVEL_LOW>;
 679                                 #interrupt-cells = <2>;
 680                                 interrupt-controller;
 681                                 #address-cells = <1>;
 682                                 #size-cells = <0>;
 683
 684                                 pm8821_mpps: mpps@50 {
 685                                         compatible = "qcom,pm8821-mpp", "qcom,ssbi-mpp";
 686                                         reg = <0x50>;
 687                                         interrupt-controller;
 688                                         #interrupt-cells = <2>;
 689                                         gpio-controller;
 690                                         #gpio-cells = <2>;
 691                                         gpio-ranges = <&pm8821_mpps 0 0 4>;
 692                                 };
 693                         };
 694                 };
 695
 696                 qcom,ssbi@500000 {
 697                         compatible = "qcom,ssbi";
 698                         reg = <0x00500000 0x1000>;
 699                         qcom,controller-type = "pmic-arbiter";
 700
 701                         pmicintc: pmic@0 {
 702                                 compatible = "qcom,pm8921";
 703                                 interrupt-parent = <&tlmm_pinmux>;
 704                                 interrupts = <74 8>;
 705                                 #interrupt-cells = <2>;
 706                                 interrupt-controller;
 707                                 #address-cells = <1>;
 708                                 #size-cells = <0>;
 709
 710                                 pm8921_gpio: gpio@150 {
 711
 712                                         compatible = "qcom,pm8921-gpio",
 713                                                      "qcom,ssbi-gpio";
 714                                         reg = <0x150>;
 715                                         interrupt-controller;
 716                                         #interrupt-cells = <2>;
 717                                         gpio-controller;
 718                                         gpio-ranges = <&pm8921_gpio 0 0 44>;
 719                                         #gpio-cells = <2>;
 720
 721                                 };
 722
 723                                 pm8921_mpps: mpps@50 {
 724                                         compatible = "qcom,pm8921-mpp",
 725                                                      "qcom,ssbi-mpp";
 726                                         reg = <0x50>;
 727                                         gpio-controller;
 728                                         #gpio-cells = <2>;
 729                                         gpio-ranges = <&pm8921_mpps 0 0 12>;
 730                                         interrupt-controller;
 731                                         #interrupt-cells = <2>;
 732                                 };
 733
 734                                 rtc@11d {
 735                                         compatible = "qcom,pm8921-rtc";
 736                                         interrupt-parent = <&pmicintc>;
 737                                         interrupts = <39 1>;
 738                                         reg = <0x11d>;
 739                                         allow-set-time;
 740                                 };
 741
 742                                 pwrkey@1c {
 743                                         compatible = "qcom,pm8921-pwrkey";
 744                                         reg = <0x1c>;
 745                                         interrupt-parent = <&pmicintc>;
 746                                         interrupts = <50 1>, <51 1>;
 747                                         debounce = <15625>;
 748                                         pull-up;
 749                                 };
 750
 751                                 xoadc: xoadc@197 {
 752                                         compatible = "qcom,pm8921-adc";
 753                                         reg = <0x197>;
 754                                         interrupts-extended = <&pmicintc 78 IRQ_TYPE_EDGE_RISING>;
 755                                         #address-cells = <2>;
 756                                         #size-cells = <0>;
 757                                         #io-channel-cells = <2>;
 758
 759                                         vcoin: adc-channel@0 {
 760                                                 reg = <0x00 0x00>;
 761                                         };
 762                                         vbat: adc-channel@1 {
 763                                                 reg = <0x00 0x01>;
 764                                         };
 765                                         dcin: adc-channel@2 {
 766                                                 reg = <0x00 0x02>;
 767                                         };
 768                                         vph_pwr: adc-channel@4 {
 769                                                 reg = <0x00 0x04>;
 770                                         };
 771                                         batt_therm: adc-channel@8 {
 772                                                 reg = <0x00 0x08>;
 773                                         };
 774                                         batt_id: adc-channel@9 {
 775                                                 reg = <0x00 0x09>;
 776                                         };
 777                                         usb_vbus: adc-channel@a {
 778                                                 reg = <0x00 0x0a>;
 779                                         };
 780                                         die_temp: adc-channel@b {
 781                                                 reg = <0x00 0x0b>;
 782                                         };
 783                                         ref_625mv: adc-channel@c {
 784                                                 reg = <0x00 0x0c>;
 785                                         };
 786                                         ref_1250mv: adc-channel@d {
 787                                                 reg = <0x00 0x0d>;
 788                                         };
 789                                         chg_temp: adc-channel@e {
 790                                                 reg = <0x00 0x0e>;
 791                                         };
 792                                         ref_muxoff: adc-channel@f {
 793                                                 reg = <0x00 0x0f>;
 794                                         };
 795                                 };
 796                         };
 797                 };
 798
 799                 qfprom: qfprom@700000 {
 800                         compatible = "qcom,apq8064-qfprom", "qcom,qfprom";
 801                         reg = <0x00700000 0x1000>;
 802                         #address-cells = <1>;
 803                         #size-cells = <1>;
 804                         ranges;
 805                         tsens_calib: calib@404 {
 806                                 reg = <0x404 0x10>;
 807                         };
 808                         tsens_backup: backup_calib@414 {
 809                                 reg = <0x414 0x10>;
 810                         };
 811                 };
 812
 813                 gcc: clock-controller@900000 {
 814                         compatible = "qcom,gcc-apq8064", "syscon";
 815                         reg = <0x00900000 0x4000>;
 816                         #clock-cells = <1>;
 817                         #power-domain-cells = <1>;
 818                         #reset-cells = <1>;
 819                         clocks = <&cxo_board>,
 820                                  <&pxo_board>,
 821                                  <&lcc PLL4>;
 822                         clock-names = "cxo", "pxo", "pll4";
 823
 824                         tsens: thermal-sensor {
 825                                 compatible = "qcom,msm8960-tsens";
 826
 827                                 nvmem-cells = <&tsens_calib>, <&tsens_backup>;
 828                                 nvmem-cell-names = "calib", "calib_backup";
 829                                 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
 830                                 interrupt-names = "uplow";
 831
 832                                 #qcom,sensors = <11>;
 833                                 #thermal-sensor-cells = <1>;
 834                         };
 835                 };
 836
 837                 lcc: clock-controller@28000000 {
 838                         compatible = "qcom,lcc-apq8064";
 839                         reg = <0x28000000 0x1000>;
 840                         #clock-cells = <1>;
 841                         #reset-cells = <1>;
 842                         clocks = <&pxo_board>,
 843                                  <&gcc PLL4_VOTE>,
 844                                  <0>,
 845                                  <0>, <0>,
 846                                  <0>, <0>,
 847                                  <0>;
 848                         clock-names = "pxo",
 849                                       "pll4_vote",
 850                                       "mi2s_codec_clk",
 851                                       "codec_i2s_mic_codec_clk",
 852                                       "spare_i2s_mic_codec_clk",
 853                                       "codec_i2s_spkr_codec_clk",
 854                                       "spare_i2s_spkr_codec_clk",
 855                                       "pcm_codec_clk";
 856                 };
 857
 858                 mmcc: clock-controller@4000000 {
 859                         compatible = "qcom,mmcc-apq8064";
 860                         reg = <0x4000000 0x1000>;
 861                         #clock-cells = <1>;
 862                         #power-domain-cells = <1>;
 863                         #reset-cells = <1>;
 864                         clocks = <&pxo_board>,
 865                                  <&gcc PLL3>,
 866                                  <&gcc PLL8_VOTE>,
 867                                  <&dsi0_phy 1>,
 868                                  <&dsi0_phy 0>,
 869                                  <0>,
 870                                  <0>,
 871                                  <0>;
 872                         clock-names = "pxo",
 873                                       "pll3",
 874                                       "pll8_vote",
 875                                       "dsi1pll",
 876                                       "dsi1pllbyte",
 877                                       "dsi2pll",
 878                                       "dsi2pllbyte",
 879                                       "hdmipll";
 880                 };
 881
 882                 l2cc: clock-controller@2011000 {
 883                         compatible = "qcom,kpss-gcc", "syscon";
 884                         reg = <0x2011000 0x1000>;
 885                 };
 886
 887                 rpm@108000 {
 888                         compatible = "qcom,rpm-apq8064";
 889                         reg = <0x108000 0x1000>;
 890                         qcom,ipc = <&l2cc 0x8 2>;
 891
 892                         interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
 893                                      <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
 894                                      <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
 895                         interrupt-names = "ack", "err", "wakeup";
 896
 897                         rpmcc: clock-controller {
 898                                 compatible = "qcom,rpmcc-apq8064", "qcom,rpmcc";
 899                                 #clock-cells = <1>;
 900                                 clocks = <&pxo_board>, <&cxo_board>;
 901                                 clock-names = "pxo", "cxo";
 902                         };
 903
 904                         regulators {
 905                                 compatible = "qcom,rpm-pm8921-regulators";
 906
 907                                 pm8921_s1: s1 {};
 908                                 pm8921_s2: s2 {};
 909                                 pm8921_s3: s3 {};
 910                                 pm8921_s4: s4 {};
 911                                 pm8921_s7: s7 {};
 912                                 pm8921_s8: s8 {};
 913
 914                                 pm8921_l1: l1 {};
 915                                 pm8921_l2: l2 {};
 916                                 pm8921_l3: l3 {};
 917                                 pm8921_l4: l4 {};
 918                                 pm8921_l5: l5 {};
 919                                 pm8921_l6: l6 {};
 920                                 pm8921_l7: l7 {};
 921                                 pm8921_l8: l8 {};
 922                                 pm8921_l9: l9 {};
 923                                 pm8921_l10: l10 {};
 924                                 pm8921_l11: l11 {};
 925                                 pm8921_l12: l12 {};
 926                                 pm8921_l14: l14 {};
 927                                 pm8921_l15: l15 {};
 928                                 pm8921_l16: l16 {};
 929                                 pm8921_l17: l17 {};
 930                                 pm8921_l18: l18 {};
 931                                 pm8921_l21: l21 {};
 932                                 pm8921_l22: l22 {};
 933                                 pm8921_l23: l23 {};
 934                                 pm8921_l24: l24 {};
 935                                 pm8921_l25: l25 {};
 936                                 pm8921_l26: l26 {};
 937                                 pm8921_l27: l27 {};
 938                                 pm8921_l28: l28 {};
 939                                 pm8921_l29: l29 {};
 940
 941                                 pm8921_lvs1: lvs1 {};
 942                                 pm8921_lvs2: lvs2 {};
 943                                 pm8921_lvs3: lvs3 {};
 944                                 pm8921_lvs4: lvs4 {};
 945                                 pm8921_lvs5: lvs5 {};
 946                                 pm8921_lvs6: lvs6 {};
 947                                 pm8921_lvs7: lvs7 {};
 948
 949                                 pm8921_usb_switch: usb-switch {};
 950
 951                                 pm8921_hdmi_switch: hdmi-switch {
 952                                         bias-pull-down;
 953                                 };
 954
 955                                 pm8921_ncp: ncp {};
 956                         };
 957                 };
 958
 959                 usb1: usb@12500000 {
 960                         compatible = "qcom,ci-hdrc";
 961                         reg = <0x12500000 0x200>,
 962                               <0x12500200 0x200>;
 963                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 964                         clocks = <&gcc USB_HS1_XCVR_CLK>, <&gcc USB_HS1_H_CLK>;
 965                         clock-names = "core", "iface";
 966                         assigned-clocks = <&gcc USB_HS1_XCVR_CLK>;
 967                         assigned-clock-rates = <60000000>;
 968                         resets = <&gcc USB_HS1_RESET>;
 969                         reset-names = "core";
 970                         phy_type = "ulpi";
 971                         ahb-burst-config = <0>;
 972                         phys = <&usb_hs1_phy>;
 973                         phy-names = "usb-phy";
 974                         status = "disabled";
 975                         #reset-cells = <1>;
 976
 977                         ulpi {
 978                                 usb_hs1_phy: phy {
 979                                         compatible = "qcom,usb-hs-phy-apq8064",
 980                                                      "qcom,usb-hs-phy";
 981                                         clocks = <&sleep_clk>, <&cxo_board>;
 982                                         clock-names = "sleep", "ref";
 983                                         resets = <&usb1 0>;
 984                                         reset-names = "por";
 985                                         #phy-cells = <0>;
 986                                 };
 987                         };
 988                 };
 989
 990                 usb3: usb@12520000 {
 991                         compatible = "qcom,ci-hdrc";
 992                         reg = <0x12520000 0x200>,
 993                               <0x12520200 0x200>;
 994                         interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
 995                         clocks = <&gcc USB_HS3_XCVR_CLK>, <&gcc USB_HS3_H_CLK>;
 996                         clock-names = "core", "iface";
 997                         assigned-clocks = <&gcc USB_HS3_XCVR_CLK>;
 998                         assigned-clock-rates = <60000000>;
 999                         resets = <&gcc USB_HS3_RESET>;
1000                         reset-names = "core";
1001                         phy_type = "ulpi";
1002                         ahb-burst-config = <0>;
1003                         phys = <&usb_hs3_phy>;
1004                         phy-names = "usb-phy";
1005                         status = "disabled";
1006                         #reset-cells = <1>;
1007
1008                         ulpi {
1009                                 usb_hs3_phy: phy {
1010                                         compatible = "qcom,usb-hs-phy-apq8064",
1011                                                      "qcom,usb-hs-phy";
1012                                         #phy-cells = <0>;
1013                                         clocks = <&sleep_clk>, <&cxo_board>;
1014                                         clock-names = "sleep", "ref";
1015                                         resets = <&usb3 0>;
1016                                         reset-names = "por";
1017                                 };
1018                         };
1019                 };
1020
1021                 usb4: usb@12530000 {
1022                         compatible = "qcom,ci-hdrc";
1023                         reg = <0x12530000 0x200>,
1024                               <0x12530200 0x200>;
1025                         interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
1026                         clocks = <&gcc USB_HS4_XCVR_CLK>, <&gcc USB_HS4_H_CLK>;
1027                         clock-names = "core", "iface";
1028                         assigned-clocks = <&gcc USB_HS4_XCVR_CLK>;
1029                         assigned-clock-rates = <60000000>;
1030                         resets = <&gcc USB_HS4_RESET>;
1031                         reset-names = "core";
1032                         phy_type = "ulpi";
1033                         ahb-burst-config = <0>;
1034                         phys = <&usb_hs4_phy>;
1035                         phy-names = "usb-phy";
1036                         status = "disabled";
1037                         #reset-cells = <1>;
1038
1039                         ulpi {
1040                                 usb_hs4_phy: phy {
1041                                         compatible = "qcom,usb-hs-phy-apq8064",
1042                                                      "qcom,usb-hs-phy";
1043                                         #phy-cells = <0>;
1044                                         clocks = <&sleep_clk>, <&cxo_board>;
1045                                         clock-names = "sleep", "ref";
1046                                         resets = <&usb4 0>;
1047                                         reset-names = "por";
1048                                 };
1049                         };
1050                 };
1051
1052                 sata_phy0: phy@1b400000 {
1053                         compatible = "qcom,apq8064-sata-phy";
1054                         status = "disabled";
1055                         reg = <0x1b400000 0x200>;
1056                         reg-names = "phy_mem";
1057                         clocks = <&gcc SATA_PHY_CFG_CLK>;
1058                         clock-names = "cfg";
1059                         #phy-cells = <0>;
1060                 };
1061
1062                 sata0: sata@29000000 {
1063                         compatible = "qcom,apq8064-ahci", "generic-ahci";
1064                         status   = "disabled";
1065                         reg      = <0x29000000 0x180>;
1066                         interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
1067
1068                         clocks = <&gcc SFAB_SATA_S_H_CLK>,
1069                                  <&gcc SATA_H_CLK>,
1070                                  <&gcc SATA_A_CLK>,
1071                                  <&gcc SATA_RXOOB_CLK>,
1072                                  <&gcc SATA_PMALIVE_CLK>;
1073                         clock-names = "slave_iface",
1074                                       "iface",
1075                                       "bus",
1076                                       "rxoob",
1077                                       "core_pmalive";
1078
1079                         assigned-clocks = <&gcc SATA_RXOOB_CLK>,
1080                                           <&gcc SATA_PMALIVE_CLK>;
1081                         assigned-clock-rates = <100000000>, <100000000>;
1082
1083                         phys = <&sata_phy0>;
1084                         phy-names = "sata-phy";
1085                         ports-implemented = <0x1>;
1086                 };
1087
1088                 /* Temporary fixed regulator */
1089                 sdcc1bam: dma-controller@12402000{
1090                         compatible = "qcom,bam-v1.3.0";
1091                         reg = <0x12402000 0x8000>;
1092                         interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
1093                         clocks = <&gcc SDC1_H_CLK>;
1094                         clock-names = "bam_clk";
1095                         #dma-cells = <1>;
1096                         qcom,ee = <0>;
1097                 };
1098
1099                 sdcc3bam: dma-controller@12182000{
1100                         compatible = "qcom,bam-v1.3.0";
1101                         reg = <0x12182000 0x8000>;
1102                         interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
1103                         clocks = <&gcc SDC3_H_CLK>;
1104                         clock-names = "bam_clk";
1105                         #dma-cells = <1>;
1106                         qcom,ee = <0>;
1107                 };
1108
1109                 sdcc4bam: dma-controller@121c2000{
1110                         compatible = "qcom,bam-v1.3.0";
1111                         reg = <0x121c2000 0x8000>;
1112                         interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
1113                         clocks = <&gcc SDC4_H_CLK>;
1114                         clock-names = "bam_clk";
1115                         #dma-cells = <1>;
1116                         qcom,ee = <0>;
1117                 };
1118
1119                 amba {
1120                         compatible = "simple-bus";
1121                         #address-cells = <1>;
1122                         #size-cells = <1>;
1123                         ranges;
1124                         sdcc1: mmc@12400000 {
1125                                 status = "disabled";
1126                                 compatible = "arm,pl18x", "arm,primecell";
1127                                 pinctrl-names = "default";
1128                                 pinctrl-0 = <&sdcc1_pins>;
1129                                 arm,primecell-periphid = <0x00051180>;
1130                                 reg = <0x12400000 0x2000>;
1131                                 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
1132                                 interrupt-names = "cmd_irq";
1133                                 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
1134                                 clock-names = "mclk", "apb_pclk";
1135                                 bus-width = <8>;
1136                                 max-frequency = <96000000>;
1137                                 non-removable;
1138                                 cap-sd-highspeed;
1139                                 cap-mmc-highspeed;
1140                                 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
1141                                 dma-names = "tx", "rx";
1142                         };
1143
1144                         sdcc3: mmc@12180000 {
1145                                 compatible = "arm,pl18x", "arm,primecell";
1146                                 arm,primecell-periphid = <0x00051180>;
1147                                 status = "disabled";
1148                                 reg = <0x12180000 0x2000>;
1149                                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1150                                 interrupt-names = "cmd_irq";
1151                                 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
1152                                 clock-names = "mclk", "apb_pclk";
1153                                 bus-width = <4>;
1154                                 cap-sd-highspeed;
1155                                 cap-mmc-highspeed;
1156                                 max-frequency = <192000000>;
1157                                 no-1-8-v;
1158                                 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
1159                                 dma-names = "tx", "rx";
1160                         };
1161
1162                         sdcc4: mmc@121c0000 {
1163                                 compatible = "arm,pl18x", "arm,primecell";
1164                                 arm,primecell-periphid = <0x00051180>;
1165                                 status = "disabled";
1166                                 reg = <0x121c0000 0x2000>;
1167                                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1168                                 interrupt-names = "cmd_irq";
1169                                 clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
1170                                 clock-names = "mclk", "apb_pclk";
1171                                 bus-width = <4>;
1172                                 cap-sd-highspeed;
1173                                 cap-mmc-highspeed;
1174                                 max-frequency = <48000000>;
1175                                 dmas = <&sdcc4bam 2>, <&sdcc4bam 1>;
1176                                 dma-names = "tx", "rx";
1177                                 pinctrl-names = "default";
1178                                 pinctrl-0 = <&sdc4_gpios>;
1179                         };
1180                 };
1181
1182                 tcsr: syscon@1a400000 {
1183                         compatible = "qcom,tcsr-apq8064", "syscon";
1184                         reg = <0x1a400000 0x100>;
1185                 };
1186
1187                 gpu: adreno-3xx@4300000 {
1188                         compatible = "qcom,adreno-320.2", "qcom,adreno";
1189                         reg = <0x04300000 0x20000>;
1190                         reg-names = "kgsl_3d0_reg_memory";
1191                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
1192                         interrupt-names = "kgsl_3d0_irq";
1193                         clock-names =
1194                             "core",
1195                             "iface",
1196                             "mem",
1197                             "mem_iface";
1198                         clocks =
1199                             <&mmcc GFX3D_CLK>,
1200                             <&mmcc GFX3D_AHB_CLK>,
1201                             <&mmcc GFX3D_AXI_CLK>,
1202                             <&mmcc MMSS_IMEM_AHB_CLK>;
1203
1204                         iommus = <&gfx3d 0
1205                                   &gfx3d 1
1206                                   &gfx3d 2
1207                                   &gfx3d 3
1208                                   &gfx3d 4
1209                                   &gfx3d 5
1210                                   &gfx3d 6
1211                                   &gfx3d 7
1212                                   &gfx3d 8
1213                                   &gfx3d 9
1214                                   &gfx3d 10
1215                                   &gfx3d 11
1216                                   &gfx3d 12
1217                                   &gfx3d 13
1218                                   &gfx3d 14
1219                                   &gfx3d 15
1220                                   &gfx3d 16
1221                                   &gfx3d 17
1222                                   &gfx3d 18
1223                                   &gfx3d 19
1224                                   &gfx3d 20
1225                                   &gfx3d 21
1226                                   &gfx3d 22
1227                                   &gfx3d 23
1228                                   &gfx3d 24
1229                                   &gfx3d 25
1230                                   &gfx3d 26
1231                                   &gfx3d 27
1232                                   &gfx3d 28
1233                                   &gfx3d 29
1234                                   &gfx3d 30
1235                                   &gfx3d 31
1236                                   &gfx3d1 0
1237                                   &gfx3d1 1
1238                                   &gfx3d1 2
1239                                   &gfx3d1 3
1240                                   &gfx3d1 4
1241                                   &gfx3d1 5
1242                                   &gfx3d1 6
1243                                   &gfx3d1 7
1244                                   &gfx3d1 8
1245                                   &gfx3d1 9
1246                                   &gfx3d1 10
1247                                   &gfx3d1 11
1248                                   &gfx3d1 12
1249                                   &gfx3d1 13
1250                                   &gfx3d1 14
1251                                   &gfx3d1 15
1252                                   &gfx3d1 16
1253                                   &gfx3d1 17
1254                                   &gfx3d1 18
1255                                   &gfx3d1 19
1256                                   &gfx3d1 20
1257                                   &gfx3d1 21
1258                                   &gfx3d1 22
1259                                   &gfx3d1 23
1260                                   &gfx3d1 24
1261                                   &gfx3d1 25
1262                                   &gfx3d1 26
1263                                   &gfx3d1 27
1264                                   &gfx3d1 28
1265                                   &gfx3d1 29
1266                                   &gfx3d1 30
1267                                   &gfx3d1 31>;
1268
1269                         operating-points-v2 = <&gpu_opp_table>;
1270
1271                         gpu_opp_table: opp-table {
1272                                 compatible = "operating-points-v2";
1273
1274                                 opp-450000000 {
1275                                         opp-hz = /bits/ 64 <450000000>;
1276                                 };
1277
1278                                 opp-27000000 {
1279                                         opp-hz = /bits/ 64 <27000000>;
1280                                 };
1281                         };
1282                 };
1283
1284                 mmss_sfpb: syscon@5700000 {
1285                         compatible = "syscon";
1286                         reg = <0x5700000 0x70>;
1287                 };
1288
1289                 dsi0: dsi@4700000 {
1290                         compatible = "qcom,mdss-dsi-ctrl";
1291                         label = "MDSS DSI CTRL->0";
1292                         #address-cells = <1>;
1293                         #size-cells = <0>;
1294                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1295                         reg = <0x04700000 0x200>;
1296                         reg-names = "dsi_ctrl";
1297
1298                         clocks = <&mmcc DSI_M_AHB_CLK>,
1299                                 <&mmcc DSI_S_AHB_CLK>,
1300                                 <&mmcc AMP_AHB_CLK>,
1301                                 <&mmcc DSI_CLK>,
1302                                 <&mmcc DSI1_BYTE_CLK>,
1303                                 <&mmcc DSI_PIXEL_CLK>,
1304                                 <&mmcc DSI1_ESC_CLK>;
1305                         clock-names = "iface", "bus", "core_mmss",
1306                                         "src", "byte", "pixel",
1307                                         "core";
1308
1309                         assigned-clocks = <&mmcc DSI1_BYTE_SRC>,
1310                                         <&mmcc DSI1_ESC_SRC>,
1311                                         <&mmcc DSI_SRC>,
1312                                         <&mmcc DSI_PIXEL_SRC>;
1313                         assigned-clock-parents = <&dsi0_phy 0>,
1314                                                 <&dsi0_phy 0>,
1315                                                 <&dsi0_phy 1>,
1316                                                 <&dsi0_phy 1>;
1317                         syscon-sfpb = <&mmss_sfpb>;
1318                         phys = <&dsi0_phy>;
1319                         phy-names = "dsi";
1320                         status = "disabled";
1321
1322                         ports {
1323                                 #address-cells = <1>;
1324                                 #size-cells = <0>;
1325
1326                                 port@0 {
1327                                         reg = <0>;
1328                                         dsi0_in: endpoint {
1329                                         };
1330                                 };
1331
1332                                 port@1 {
1333                                         reg = <1>;
1334                                         dsi0_out: endpoint {
1335                                         };
1336                                 };
1337                         };
1338                 };
1339
1340
1341                 dsi0_phy: dsi-phy@4700200 {
1342                         compatible = "qcom,dsi-phy-28nm-8960";
1343                         #clock-cells = <1>;
1344                         #phy-cells = <0>;
1345
1346                         reg = <0x04700200 0x100>,
1347                                 <0x04700300 0x200>,
1348                                 <0x04700500 0x5c>;
1349                         reg-names = "dsi_pll", "dsi_phy", "dsi_phy_regulator";
1350                         clock-names = "iface", "ref";
1351                         clocks = <&mmcc DSI_M_AHB_CLK>,
1352                                  <&pxo_board>;
1353                         status = "disabled";
1354                 };
1355
1356
1357                 mdp_port0: iommu@7500000 {
1358                         compatible = "qcom,apq8064-iommu";
1359                         #iommu-cells = <1>;
1360                         clock-names =
1361                             "smmu_pclk",
1362                             "iommu_clk";
1363                         clocks =
1364                             <&mmcc SMMU_AHB_CLK>,
1365                             <&mmcc MDP_AXI_CLK>;
1366                         reg = <0x07500000 0x100000>;
1367                         interrupts =
1368                             <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
1369                             <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
1370                         qcom,ncb = <2>;
1371                 };
1372
1373                 mdp_port1: iommu@7600000 {
1374                         compatible = "qcom,apq8064-iommu";
1375                         #iommu-cells = <1>;
1376                         clock-names =
1377                             "smmu_pclk",
1378                             "iommu_clk";
1379                         clocks =
1380                             <&mmcc SMMU_AHB_CLK>,
1381                             <&mmcc MDP_AXI_CLK>;
1382                         reg = <0x07600000 0x100000>;
1383                         interrupts =
1384                             <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
1385                             <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1386                         qcom,ncb = <2>;
1387                 };
1388
1389                 gfx3d: iommu@7c00000 {
1390                         compatible = "qcom,apq8064-iommu";
1391                         #iommu-cells = <1>;
1392                         clock-names =
1393                             "smmu_pclk",
1394                             "iommu_clk";
1395                         clocks =
1396                             <&mmcc SMMU_AHB_CLK>,
1397                             <&mmcc GFX3D_AXI_CLK>;
1398                         reg = <0x07c00000 0x100000>;
1399                         interrupts =
1400                             <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
1401                             <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1402                         qcom,ncb = <3>;
1403                 };
1404
1405                 gfx3d1: iommu@7d00000 {
1406                         compatible = "qcom,apq8064-iommu";
1407                         #iommu-cells = <1>;
1408                         clock-names =
1409                             "smmu_pclk",
1410                             "iommu_clk";
1411                         clocks =
1412                             <&mmcc SMMU_AHB_CLK>,
1413                             <&mmcc GFX3D_AXI_CLK>;
1414                         reg = <0x07d00000 0x100000>;
1415                         interrupts =
1416                             <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
1417                             <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
1418                         qcom,ncb = <3>;
1419                 };
1420
1421                 pcie: pci@1b500000 {
1422                         compatible = "qcom,pcie-apq8064";
1423                         reg = <0x1b500000 0x1000>,
1424                               <0x1b502000 0x80>,
1425                               <0x1b600000 0x100>,
1426                               <0x0ff00000 0x100000>;
1427                         reg-names = "dbi", "elbi", "parf", "config";
1428                         device_type = "pci";
1429                         linux,pci-domain = <0>;
1430                         bus-range = <0x00 0xff>;
1431                         num-lanes = <1>;
1432                         #address-cells = <3>;
1433                         #size-cells = <2>;
1434                         ranges = <0x81000000 0 0          0x0fe00000 0 0x00100000>, /* I/O */
1435                                  <0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* mem */
1436                         interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
1437                         interrupt-names = "msi";
1438                         #interrupt-cells = <1>;
1439                         interrupt-map-mask = <0 0 0 0x7>;
1440                         interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1441                                         <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1442                                         <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1443                                         <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1444                         clocks = <&gcc PCIE_A_CLK>,
1445                                  <&gcc PCIE_H_CLK>,
1446                                  <&gcc PCIE_PHY_REF_CLK>;
1447                         clock-names = "core", "iface", "phy";
1448                         resets = <&gcc PCIE_ACLK_RESET>,
1449                                  <&gcc PCIE_HCLK_RESET>,
1450                                  <&gcc PCIE_POR_RESET>,
1451                                  <&gcc PCIE_PCI_RESET>,
1452                                  <&gcc PCIE_PHY_RESET>;
1453                         reset-names = "axi", "ahb", "por", "pci", "phy";
1454                         status = "disabled";
1455                 };
1456
1457                 hdmi: hdmi-tx@4a00000 {
1458                         compatible = "qcom,hdmi-tx-8960";
1459                         pinctrl-names = "default";
1460                         pinctrl-0 = <&hdmi_pinctrl>;
1461                         reg = <0x04a00000 0x2f0>;
1462                         reg-names = "core_physical";
1463                         interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
1464                         clocks = <&mmcc HDMI_APP_CLK>,
1465                                  <&mmcc HDMI_M_AHB_CLK>,
1466                                  <&mmcc HDMI_S_AHB_CLK>;
1467                         clock-names = "core",
1468                                       "master_iface",
1469                                       "slave_iface";
1470
1471                         phys = <&hdmi_phy>;
1472
1473                         ports {
1474                                 #address-cells = <1>;
1475                                 #size-cells = <0>;
1476
1477                                 port@0 {
1478                                         reg = <0>;
1479                                         hdmi_in: endpoint {
1480                                         };
1481                                 };
1482
1483                                 port@1 {
1484                                         reg = <1>;
1485                                         hdmi_out: endpoint {
1486                                         };
1487                                 };
1488                         };
1489                 };
1490
1491                 hdmi_phy: hdmi-phy@4a00400 {
1492                         compatible = "qcom,hdmi-phy-8960";
1493                         reg = <0x4a00400 0x60>,
1494                               <0x4a00500 0x100>;
1495                         reg-names = "hdmi_phy",
1496                                     "hdmi_pll";
1497
1498                         clocks = <&mmcc HDMI_S_AHB_CLK>;
1499                         clock-names = "slave_iface";
1500                         #phy-cells = <0>;
1501                 };
1502
1503                 mdp: mdp@5100000 {
1504                         compatible = "qcom,mdp4";
1505                         reg = <0x05100000 0xf0000>;
1506                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1507                         clocks = <&mmcc MDP_CLK>,
1508                                  <&mmcc MDP_AHB_CLK>,
1509                                  <&mmcc MDP_AXI_CLK>,
1510                                  <&mmcc MDP_LUT_CLK>,
1511                                  <&mmcc HDMI_TV_CLK>,
1512                                  <&mmcc MDP_TV_CLK>;
1513                         clock-names = "core_clk",
1514                                       "iface_clk",
1515                                       "bus_clk",
1516                                       "lut_clk",
1517                                       "hdmi_clk",
1518                                       "tv_clk";
1519
1520                         iommus = <&mdp_port0 0
1521                                   &mdp_port0 2
1522                                   &mdp_port1 0
1523                                   &mdp_port1 2>;
1524
1525                         ports {
1526                                 #address-cells = <1>;
1527                                 #size-cells = <0>;
1528
1529                                 port@0 {
1530                                         reg = <0>;
1531                                         mdp_lvds_out: endpoint {
1532                                         };
1533                                 };
1534
1535                                 port@1 {
1536                                         reg = <1>;
1537                                         mdp_dsi1_out: endpoint {
1538                                         };
1539                                 };
1540
1541                                 port@2 {
1542                                         reg = <2>;
1543                                         mdp_dsi2_out: endpoint {
1544                                         };
1545                                 };
1546
1547                                 port@3 {
1548                                         reg = <3>;
1549                                         mdp_dtv_out: endpoint {
1550                                         };
1551                                 };
1552                         };
1553                 };
1554
1555                 riva: riva-pil@3204000 {
1556                         compatible = "qcom,riva-pil";
1557
1558                         reg = <0x03200800 0x1000>, <0x03202000 0x2000>, <0x03204000 0x100>;
1559                         reg-names = "ccu", "dxe", "pmu";
1560
1561                         interrupts-extended = <&intc GIC_SPI 199 IRQ_TYPE_EDGE_RISING>,
1562                                               <&wcnss_smsm 6 IRQ_TYPE_EDGE_RISING>;
1563                         interrupt-names = "wdog", "fatal";
1564
1565                         memory-region = <&wcnss_mem>;
1566
1567                         vddcx-supply = <&pm8921_s3>;
1568                         vddmx-supply = <&pm8921_l24>;
1569                         vddpx-supply = <&pm8921_s4>;
1570
1571                         status = "disabled";
1572
1573                         iris {
1574                                 compatible = "qcom,wcn3660";
1575
1576                                 clocks = <&cxo_board>;
1577                                 clock-names = "xo";
1578
1579                                 vddxo-supply = <&pm8921_l4>;
1580                                 vddrfa-supply = <&pm8921_s2>;
1581                                 vddpa-supply = <&pm8921_l10>;
1582                                 vdddig-supply = <&pm8921_lvs2>;
1583                         };
1584
1585                         smd-edge {
1586                                 interrupts = <GIC_SPI 198 IRQ_TYPE_EDGE_RISING>;
1587
1588                                 qcom,ipc = <&l2cc 8 25>;
1589                                 qcom,smd-edge = <6>;
1590
1591                                 label = "riva";
1592
1593                                 wcnss {
1594                                         compatible = "qcom,wcnss";
1595                                         qcom,smd-channels = "WCNSS_CTRL";
1596
1597                                         qcom,mmio = <&riva>;
1598
1599                                         bluetooth {
1600                                                 compatible = "qcom,wcnss-bt";
1601                                         };
1602
1603                                         wifi {
1604                                                 compatible = "qcom,wcnss-wlan";
1605
1606                                                 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
1607                                                              <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
1608                                                 interrupt-names = "tx", "rx";
1609
1610                                                 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
1611                                                 qcom,smem-state-names = "tx-enable", "tx-rings-empty";
1612                                         };
1613                                 };
1614                         };
1615                 };
1616
1617                 etb@1a01000 {
1618                         compatible = "arm,coresight-etb10", "arm,primecell";
1619                         reg = <0x1a01000 0x1000>;
1620
1621                         clocks = <&rpmcc RPM_QDSS_CLK>;
1622                         clock-names = "apb_pclk";
1623
1624                         in-ports {
1625                                 port {
1626                                         etb_in: endpoint {
1627                                                 remote-endpoint = <&replicator_out0>;
1628                                         };
1629                                 };
1630                         };
1631                 };
1632
1633                 tpiu@1a03000 {
1634                         compatible = "arm,coresight-tpiu", "arm,primecell";
1635                         reg = <0x1a03000 0x1000>;
1636
1637                         clocks = <&rpmcc RPM_QDSS_CLK>;
1638                         clock-names = "apb_pclk";
1639
1640                         in-ports {
1641                                 port {
1642                                         tpiu_in: endpoint {
1643                                                 remote-endpoint = <&replicator_out1>;
1644                                         };
1645                                 };
1646                         };
1647                 };
1648
1649                 replicator {
1650                         compatible = "arm,coresight-static-replicator";
1651
1652                         clocks = <&rpmcc RPM_QDSS_CLK>;
1653                         clock-names = "apb_pclk";
1654
1655                         out-ports {
1656                                 #address-cells = <1>;
1657                                 #size-cells = <0>;
1658
1659                                 port@0 {
1660                                         reg = <0>;
1661                                         replicator_out0: endpoint {
1662                                                 remote-endpoint = <&etb_in>;
1663                                         };
1664                                 };
1665                                 port@1 {
1666                                         reg = <1>;
1667                                         replicator_out1: endpoint {
1668                                                 remote-endpoint = <&tpiu_in>;
1669                                         };
1670                                 };
1671                         };
1672
1673                         in-ports {
1674                                 port {
1675                                         replicator_in: endpoint {
1676                                                 remote-endpoint = <&funnel_out>;
1677                                         };
1678                                 };
1679                         };
1680                 };
1681
1682                 funnel@1a04000 {
1683                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1684                         reg = <0x1a04000 0x1000>;
1685
1686                         clocks = <&rpmcc RPM_QDSS_CLK>;
1687                         clock-names = "apb_pclk";
1688
1689                         in-ports {
1690                                 #address-cells = <1>;
1691                                 #size-cells = <0>;
1692
1693                                 /*
1694                                  * Not described input ports:
1695                                  * 2 - connected to STM component
1696                                  * 3 - not-connected
1697                                  * 6 - not-connected
1698                                  * 7 - not-connected
1699                                  */
1700                                 port@0 {
1701                                         reg = <0>;
1702                                         funnel_in0: endpoint {
1703                                                 remote-endpoint = <&etm0_out>;
1704                                         };
1705                                 };
1706                                 port@1 {
1707                                         reg = <1>;
1708                                         funnel_in1: endpoint {
1709                                                 remote-endpoint = <&etm1_out>;
1710                                         };
1711                                 };
1712                                 port@4 {
1713                                         reg = <4>;
1714                                         funnel_in4: endpoint {
1715                                                 remote-endpoint = <&etm2_out>;
1716                                         };
1717                                 };
1718                                 port@5 {
1719                                         reg = <5>;
1720                                         funnel_in5: endpoint {
1721                                                 remote-endpoint = <&etm3_out>;
1722                                         };
1723                                 };
1724                         };
1725
1726                         out-ports {
1727                                 port {
1728                                         funnel_out: endpoint {
1729                                                 remote-endpoint = <&replicator_in>;
1730                                         };
1731                                 };
1732                         };
1733                 };
1734
1735                 etm@1a1c000 {
1736                         compatible = "arm,coresight-etm3x", "arm,primecell";
1737                         reg = <0x1a1c000 0x1000>;
1738
1739                         clocks = <&rpmcc RPM_QDSS_CLK>;
1740                         clock-names = "apb_pclk";
1741
1742                         cpu = <&CPU0>;
1743
1744                         out-ports {
1745                                 port {
1746                                         etm0_out: endpoint {
1747                                                 remote-endpoint = <&funnel_in0>;
1748                                         };
1749                                 };
1750                         };
1751                 };
1752
1753                 etm@1a1d000 {
1754                         compatible = "arm,coresight-etm3x", "arm,primecell";
1755                         reg = <0x1a1d000 0x1000>;
1756
1757                         clocks = <&rpmcc RPM_QDSS_CLK>;
1758                         clock-names = "apb_pclk";
1759
1760                         cpu = <&CPU1>;
1761
1762                         out-ports {
1763                                 port {
1764                                         etm1_out: endpoint {
1765                                                 remote-endpoint = <&funnel_in1>;
1766                                         };
1767                                 };
1768                         };
1769                 };
1770
1771                 etm@1a1e000 {
1772                         compatible = "arm,coresight-etm3x", "arm,primecell";
1773                         reg = <0x1a1e000 0x1000>;
1774
1775                         clocks = <&rpmcc RPM_QDSS_CLK>;
1776                         clock-names = "apb_pclk";
1777
1778                         cpu = <&CPU2>;
1779
1780                         out-ports {
1781                                 port {
1782                                         etm2_out: endpoint {
1783                                                 remote-endpoint = <&funnel_in4>;
1784                                         };
1785                                 };
1786                         };
1787                 };
1788
1789                 etm@1a1f000 {
1790                         compatible = "arm,coresight-etm3x", "arm,primecell";
1791                         reg = <0x1a1f000 0x1000>;
1792
1793                         clocks = <&rpmcc RPM_QDSS_CLK>;
1794                         clock-names = "apb_pclk";
1795
1796                         cpu = <&CPU3>;
1797
1798                         out-ports {
1799                                 port {
1800                                         etm3_out: endpoint {
1801                                                 remote-endpoint = <&funnel_in5>;
1802                                         };
1803                                 };
1804                         };
1805                 };
1806         };
1807 };
1808 #include "qcom-apq8064-pins.dtsi"