1 // SPDX-License-Identifier: GPL-2.0
2 /* The pxa3xx skeleton simply augments the 2xx version */
4 #include "dt-bindings/clock/pxa-clock.h"
7 model = "Marvell PXA27x familiy SoC";
8 compatible = "marvell,pxa27x";
11 pdma: dma-controller@40000000 {
12 compatible = "marvell,pdma-1.0";
13 reg = <0x40000000 0x10000>;
16 /* For backwards compatibility: */
24 pxairq: interrupt-controller@40d00000 {
25 marvell,intc-priority;
26 marvell,intc-nr-irqs = <34>;
29 pinctrl: pinctrl@40e00000 {
30 reg = <0x40e00054 0x20 0x40e0000c 0xc 0x40e0010c 4
32 compatible = "marvell,pxa27x-pinctrl";
36 compatible = "intel,pxa27x-gpio";
37 gpio-ranges = <&pinctrl 0 0 128>;
38 clocks = <&clks CLK_NONE>;
42 compatible = "marvell,pxa-ohci";
43 reg = <0x4c000000 0x10000>;
45 clocks = <&clks CLK_USBHOST>;
50 compatible = "marvell,pxa270-pwm", "marvell,pxa250-pwm";
51 reg = <0x40b00000 0x10>;
53 clocks = <&clks CLK_PWM0>;
57 compatible = "marvell,pxa270-pwm", "marvell,pxa250-pwm";
58 reg = <0x40b00010 0x10>;
60 clocks = <&clks CLK_PWM1>;
64 compatible = "marvell,pxa270-pwm", "marvell,pxa250-pwm";
65 reg = <0x40c00000 0x10>;
67 clocks = <&clks CLK_PWM0>;
71 compatible = "marvell,pxa270-pwm", "marvell,pxa250-pwm";
72 reg = <0x40c00010 0x10>;
74 clocks = <&clks CLK_PWM1>;
77 pwri2c: i2c@40f00180 {
78 compatible = "mrvl,pxa-i2c";
79 reg = <0x40f00180 0x24>;
81 clocks = <&clks CLK_PWRI2C>;
82 #address-cells = <0x1>;
87 pxa27x_udc: udc@40600000 {
88 compatible = "marvell,pxa270-udc";
89 reg = <0x40600000 0x10000>;
91 clocks = <&clks CLK_USB>;
95 keypad: keypad@41500000 {
96 compatible = "marvell,pxa27x-keypad";
97 reg = <0x41500000 0x4c>;
99 clocks = <&clks CLK_KEYPAD>;
103 pxa_camera: imaging@50000000 {
104 compatible = "marvell,pxa270-qci";
105 reg = <0x50000000 0x1000>;
107 dmas = <&pdma 68 0 /* Y channel */
108 &pdma 69 0 /* U channel */
109 &pdma 70 0>; /* V channel */
110 dma-names = "CI_Y", "CI_U", "CI_V";
112 clocks = <&clks CLK_CAMERA>;
113 clock-names = "ciclk";
114 clock-frequency = <5000000>;
115 clock-output-names = "qci_mclk";
121 clocks = <&clks CLK_OSC32k768>;
127 * The muxing of external clocks/internal dividers for osc* clock
128 * sources has been hidden under the carpet by now.
130 #address-cells = <1>;
134 clks: pxa2xx_clks@41300004 {
135 compatible = "marvell,pxa270-clocks";
142 compatible = "marvell,pxa-timer";
143 reg = <0x40a00000 0x20>;
145 clocks = <&clks CLK_OSTIMER>;
149 pxa270_opp_table: opp_table0 {
150 compatible = "operating-points-v2";
153 opp-hz = /bits/ 64 <104000000>;
154 opp-microvolt = <900000 900000 1705000>;
155 clock-latency-ns = <20>;
158 opp-hz = /bits/ 64 <156000000>;
159 opp-microvolt = <1000000 1000000 1705000>;
160 clock-latency-ns = <20>;
163 opp-hz = /bits/ 64 <208000000>;
164 opp-microvolt = <1180000 1180000 1705000>;
165 clock-latency-ns = <20>;
168 opp-hz = /bits/ 64 <312000000>;
169 opp-microvolt = <1250000 1250000 1705000>;
170 clock-latency-ns = <20>;
173 opp-hz = /bits/ 64 <416000000>;
174 opp-microvolt = <1350000 1350000 1705000>;
175 clock-latency-ns = <20>;
178 opp-hz = /bits/ 64 <520000000>;
179 opp-microvolt = <1450000 1450000 1705000>;
180 clock-latency-ns = <20>;
183 opp-hz = /bits/ 64 <624000000>;
184 opp-microvolt = <1550000 1550000 1705000>;
185 clock-latency-ns = <20>;