1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2011 Picochip, Jamie Iles
6 model = "Picochip picoXcell PC3X2";
7 compatible = "picochip,pc3x2";
16 compatible = "arm,arm1176jz-s";
18 clock-frequency = <400000000>;
19 d-cache-line-size = <32>;
20 d-cache-size = <32768>;
21 i-cache-line-size = <32>;
22 i-cache-size = <32768>;
32 compatible = "fixed-clock";
33 clock-outputs = "bus", "pclk";
34 clock-frequency = <200000000>;
35 ref-clock = <&ref_clk>, "ref";
40 compatible = "simple-bus";
43 ranges = <0 0x80000000 0x400000>;
46 compatible = "cadence,gem";
47 reg = <0x30000 0x10000>;
48 interrupt-parent = <&vic0>;
53 compatible = "snps,dw-dmac";
54 reg = <0x40000 0x10000>;
55 interrupt-parent = <&vic0>;
60 compatible = "snps,dw-dmac";
61 reg = <0x50000 0x10000>;
62 interrupt-parent = <&vic0>;
66 vic0: interrupt-controller@60000 {
67 compatible = "arm,pl192-vic";
69 reg = <0x60000 0x1000>;
70 #interrupt-cells = <1>;
73 vic1: interrupt-controller@64000 {
74 compatible = "arm,pl192-vic";
76 reg = <0x64000 0x1000>;
77 #interrupt-cells = <1>;
80 fuse: picoxcell-fuse@80000 {
81 compatible = "picoxcell,fuse-pc3x2";
82 reg = <0x80000 0x10000>;
85 ssi: picoxcell-spi@90000 {
86 compatible = "picoxcell,spi";
87 reg = <0x90000 0x10000>;
88 interrupt-parent = <&vic0>;
93 compatible = "picochip,spacc-ipsec";
94 reg = <0x100000 0x10000>;
95 interrupt-parent = <&vic0>;
97 ref-clock = <&pclk>, "ref";
101 compatible = "picochip,spacc-srtp";
102 reg = <0x140000 0x10000>;
103 interrupt-parent = <&vic0>;
107 l2_engine: spacc@180000 {
108 compatible = "picochip,spacc-l2";
109 reg = <0x180000 0x10000>;
110 interrupt-parent = <&vic0>;
112 ref-clock = <&pclk>, "ref";
116 compatible = "simple-bus";
117 #address-cells = <1>;
119 ranges = <0 0x200000 0x80000>;
122 compatible = "picochip,pc3x2-rtc";
123 clock-freq = <200000000>;
125 interrupt-parent = <&vic1>;
129 timer0: timer@10000 {
130 compatible = "picochip,pc3x2-timer";
131 interrupt-parent = <&vic0>;
133 clock-freq = <200000000>;
134 reg = <0x10000 0x14>;
137 timer1: timer@10014 {
138 compatible = "picochip,pc3x2-timer";
139 interrupt-parent = <&vic0>;
141 clock-freq = <200000000>;
142 reg = <0x10014 0x14>;
145 timer2: timer@10028 {
146 compatible = "picochip,pc3x2-timer";
147 interrupt-parent = <&vic0>;
149 clock-freq = <200000000>;
150 reg = <0x10028 0x14>;
153 timer3: timer@1003c {
154 compatible = "picochip,pc3x2-timer";
155 interrupt-parent = <&vic0>;
157 clock-freq = <200000000>;
158 reg = <0x1003c 0x14>;
162 compatible = "snps,dw-apb-gpio";
163 reg = <0x20000 0x1000>;
164 #address-cells = <1>;
168 banka: gpio-controller@0 {
169 compatible = "snps,dw-apb-gpio-bank";
172 gpio-generic,nr-gpio = <8>;
174 regoffset-dat = <0x50>;
175 regoffset-set = <0x00>;
176 regoffset-dirout = <0x04>;
179 bankb: gpio-controller@1 {
180 compatible = "snps,dw-apb-gpio-bank";
183 gpio-generic,nr-gpio = <8>;
185 regoffset-dat = <0x54>;
186 regoffset-set = <0x0c>;
187 regoffset-dirout = <0x10>;
192 compatible = "snps,dw-apb-uart";
193 reg = <0x30000 0x1000>;
194 interrupt-parent = <&vic1>;
196 clock-frequency = <3686400>;
202 compatible = "snps,dw-apb-uart";
203 reg = <0x40000 0x1000>;
204 interrupt-parent = <&vic1>;
206 clock-frequency = <3686400>;
211 wdog: watchdog@50000 {
212 compatible = "snps,dw-apb-wdg";
213 reg = <0x50000 0x10000>;
214 interrupt-parent = <&vic0>;
216 bus-clock = <&pclk>, "bus";
222 #address-cells = <1>;
224 compatible = "simple-bus";
228 compatible = "simple-bus";
229 #address-cells = <2>;
231 ranges = <0 0 0x40000000 0x08000000
232 1 0 0x48000000 0x08000000
233 2 0 0x50000000 0x08000000
234 3 0 0x58000000 0x08000000>;
238 compatible = "picochip,axi2pico-pc3x2";
239 reg = <0xc0000000 0x10000>;
240 interrupt-parent = <&vic0>;
241 interrupts = <13 14 15 16 17 18 19 20 21>;