arch/arm/boot/dts/ox810se.dtsi

   1 /*
   2  * ox810se.dtsi - Device tree file for Oxford Semiconductor OX810SE SoC
   3  *
   4  * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
   5  *
   6  * Licensed under GPLv2 or later
   7  */
   8
   9 /include/ "skeleton.dtsi"
  10
  11 / {
  12         compatible = "oxsemi,ox810se";
  13
  14         cpus {
  15                 #address-cells = <0>;
  16                 #size-cells = <0>;
  17
  18                 cpu {
  19                         device_type = "cpu";
  20                         compatible = "arm,arm926ej-s";
  21                         clocks = <&armclk>;
  22                 };
  23         };
  24
  25         memory {
  26                 /* Max 256MB @ 0x48000000 */
  27                 reg = <0x48000000 0x10000000>;
  28         };
  29
  30         clocks {
  31                 osc: oscillator {
  32                         compatible = "fixed-clock";
  33                         #clock-cells = <0>;
  34                         clock-frequency = <25000000>;
  35                 };
  36
  37                 gmacclk: gmacclk {
  38                         compatible = "fixed-clock";
  39                         #clock-cells = <0>;
  40                         clock-frequency = <125000000>;
  41                 };
  42
  43                 rpsclk: rpsclk {
  44                         compatible = "fixed-factor-clock";
  45                         #clock-cells = <0>;
  46                         clock-div = <1>;
  47                         clock-mult = <1>;
  48                         clocks = <&osc>;
  49                 };
  50
  51                 pll400: pll400 {
  52                         compatible = "fixed-clock";
  53                         #clock-cells = <0>;
  54                         clock-frequency = <733333333>;
  55                 };
  56
  57                 sysclk: sysclk {
  58                         compatible = "fixed-factor-clock";
  59                         #clock-cells = <0>;
  60                         clock-div = <4>;
  61                         clock-mult = <1>;
  62                         clocks = <&pll400>;
  63                 };
  64
  65                 armclk: armclk {
  66                         compatible = "fixed-factor-clock";
  67                         #clock-cells = <0>;
  68                         clock-div = <2>;
  69                         clock-mult = <1>;
  70                         clocks = <&pll400>;
  71                 };
  72         };
  73
  74         soc {
  75                 #address-cells = <1>;
  76                 #size-cells = <1>;
  77                 compatible = "simple-bus";
  78                 ranges;
  79                 interrupt-parent = <&intc>;
  80
  81                 apb-bridge@44000000 {
  82                         #address-cells = <1>;
  83                         #size-cells = <1>;
  84                         compatible = "simple-bus";
  85                         ranges = <0 0x44000000 0x1000000>;
  86
  87                         pinctrl: pinctrl {
  88                                 compatible = "oxsemi,ox810se-pinctrl";
  89
  90                                 /* Regmap for sys registers */
  91                                 oxsemi,sys-ctrl = <&sys>;
  92
  93                                 pinctrl_uart0: uart0 {
  94                                         uart0a {
  95                                                 pins = "gpio31";
  96                                                 function = "fct3";
  97                                         };
  98                                         uart0b {
  99                                                 pins = "gpio32";
 100                                                 function = "fct3";
 101                                         };
 102                                 };
 103
 104                                 pinctrl_uart0_modem: uart0_modem {
 105                                         uart0c {
 106                                                 pins = "gpio27";
 107                                                 function = "fct3";
 108                                         };
 109                                         uart0d {
 110                                                 pins = "gpio28";
 111                                                 function = "fct3";
 112                                         };
 113                                         uart0e {
 114                                                 pins = "gpio29";
 115                                                 function = "fct3";
 116                                         };
 117                                         uart0f {
 118                                                 pins = "gpio30";
 119                                                 function = "fct3";
 120                                         };
 121                                         uart0g {
 122                                                 pins = "gpio33";
 123                                                 function = "fct3";
 124                                         };
 125                                         uart0h {
 126                                                 pins = "gpio34";
 127                                                 function = "fct3";
 128                                         };
 129                                 };
 130
 131                                 pinctrl_uart1: uart1 {
 132                                         uart1a {
 133                                                 pins = "gpio20";
 134                                                 function = "fct3";
 135                                         };
 136                                         uart1b {
 137                                                 pins = "gpio22";
 138                                                 function = "fct3";
 139                                         };
 140                                 };
 141
 142                                 pinctrl_uart1_modem: uart1_modem {
 143                                         uart1c {
 144                                                 pins = "gpio8";
 145                                                 function = "fct3";
 146                                         };
 147                                         uart1d {
 148                                                 pins = "gpio9";
 149                                                 function = "fct3";
 150                                         };
 151                                         uart1e {
 152                                                 pins = "gpio23";
 153                                                 function = "fct3";
 154                                         };
 155                                         uart1f {
 156                                                 pins = "gpio24";
 157                                                 function = "fct3";
 158                                         };
 159                                         uart1g {
 160                                                 pins = "gpio25";
 161                                                 function = "fct3";
 162                                         };
 163                                         uart1h {
 164                                                 pins = "gpio26";
 165                                                 function = "fct3";
 166                                         };
 167                                 };
 168
 169                                 pinctrl_uart2: uart2 {
 170                                         uart2a {
 171                                                 pins = "gpio6";
 172                                                 function = "fct3";
 173                                         };
 174                                         uart2b {
 175                                                 pins = "gpio7";
 176                                                 function = "fct3";
 177                                         };
 178                                 };
 179
 180                                 pinctrl_uart2_modem: uart2_modem {
 181                                         uart2c {
 182                                                 pins = "gpio0";
 183                                                 function = "fct3";
 184                                         };
 185                                         uart2d {
 186                                                 pins = "gpio1";
 187                                                 function = "fct3";
 188                                         };
 189                                         uart2e {
 190                                                 pins = "gpio2";
 191                                                 function = "fct3";
 192                                         };
 193                                         uart2f {
 194                                                 pins = "gpio3";
 195                                                 function = "fct3";
 196                                         };
 197                                         uart2g {
 198                                                 pins = "gpio4";
 199                                                 function = "fct3";
 200                                         };
 201                                         uart2h {
 202                                                 pins = "gpio5";
 203                                                 function = "fct3";
 204                                         };
 205                                 };
 206                         };
 207
 208                         gpio0: gpio@000000 {
 209                                 compatible = "oxsemi,ox810se-gpio";
 210                                 reg = <0x000000 0x100000>;
 211                                 interrupts = <21>;
 212                                 #gpio-cells = <2>;
 213                                 gpio-controller;
 214                                 interrupt-controller;
 215                                 #interrupt-cells = <2>;
 216                                 ngpios = <32>;
 217                                 oxsemi,gpio-bank = <0>;
 218                                 gpio-ranges = <&pinctrl 0 0 32>;
 219                         };
 220
 221                         gpio1: gpio@100000 {
 222                                 compatible = "oxsemi,ox810se-gpio";
 223                                 reg = <0x100000 0x100000>;
 224                                 interrupts = <22>;
 225                                 #gpio-cells = <2>;
 226                                 gpio-controller;
 227                                 interrupt-controller;
 228                                 #interrupt-cells = <2>;
 229                                 ngpios = <3>;
 230                                 oxsemi,gpio-bank = <1>;
 231                                 gpio-ranges = <&pinctrl 0 32 3>;
 232                         };
 233
 234                         uart0: serial@200000 {
 235                                compatible = "ns16550a";
 236                                reg = <0x200000 0x100000>;
 237                                clocks = <&sysclk>;
 238                                interrupts = <23>;
 239                                reg-shift = <0>;
 240                                fifo-size = <16>;
 241                                reg-io-width = <1>;
 242                                current-speed = <115200>;
 243                                no-loopback-test;
 244                                status = "disabled";
 245                                resets = <&reset 17>;
 246                         };
 247
 248                         uart1: serial@300000 {
 249                                compatible = "ns16550a";
 250                                reg = <0x300000 0x100000>;
 251                                clocks = <&sysclk>;
 252                                interrupts = <24>;
 253                                reg-shift = <0>;
 254                                fifo-size = <16>;
 255                                reg-io-width = <1>;
 256                                current-speed = <115200>;
 257                                no-loopback-test;
 258                                status = "disabled";
 259                                resets = <&reset 18>;
 260                         };
 261
 262                         uart2: serial@900000 {
 263                                compatible = "ns16550a";
 264                                reg = <0x900000 0x100000>;
 265                                clocks = <&sysclk>;
 266                                interrupts = <29>;
 267                                reg-shift = <0>;
 268                                fifo-size = <16>;
 269                                reg-io-width = <1>;
 270                                current-speed = <115200>;
 271                                no-loopback-test;
 272                                status = "disabled";
 273                                resets = <&reset 22>;
 274                         };
 275
 276                         uart3: serial@a00000 {
 277                                compatible = "ns16550a";
 278                                reg = <0xa00000 0x100000>;
 279                                clocks = <&sysclk>;
 280                                interrupts = <30>;
 281                                reg-shift = <0>;
 282                                fifo-size = <16>;
 283                                reg-io-width = <1>;
 284                                current-speed = <115200>;
 285                                no-loopback-test;
 286                                status = "disabled";
 287                                resets = <&reset 23>;
 288                         };
 289                 };
 290
 291                 apb-bridge@45000000 {
 292                         #address-cells = <1>;
 293                         #size-cells = <1>;
 294                         compatible = "simple-bus";
 295                         ranges = <0 0x45000000 0x1000000>;
 296
 297                         sys: sys-ctrl@000000 {
 298                                 compatible = "oxsemi,ox810se-sys-ctrl", "syscon", "simple-mfd";
 299                                 reg = <0x000000 0x100000>;
 300
 301                                 reset: reset-controller {
 302                                         compatible = "oxsemi,ox810se-reset";
 303                                         #reset-cells = <1>;
 304                                 };
 305
 306                                 stdclk: stdclk {
 307                                         compatible = "oxsemi,ox810se-stdclk";
 308                                         #clock-cells = <1>;
 309                                 };
 310                         };
 311
 312                         rps@300000 {
 313                                 #address-cells = <1>;
 314                                 #size-cells = <1>;
 315                                 compatible = "simple-bus";
 316                                 ranges = <0 0x300000 0x100000>;
 317
 318                                 intc: interrupt-controller@0 {
 319                                         compatible = "oxsemi,ox810se-rps-irq";
 320                                         interrupt-controller;
 321                                         reg = <0 0x200>;
 322                                         #interrupt-cells = <1>;
 323                                         valid-mask = <0xFFFFFFFF>;
 324                                         clear-mask = <0>;
 325                                 };
 326
 327                                 timer0: timer@200 {
 328                                         compatible = "oxsemi,ox810se-rps-timer";
 329                                         reg = <0x200 0x40>;
 330                                         clocks = <&rpsclk>;
 331                                         interrupts = <4 5>;
 332                                 };
 333                         };
 334                 };
 335         };
 336 };