arch/arm/boot/dts/ox810se.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * ox810se.dtsi - Device tree file for Oxford Semiconductor OX810SE SoC
   4  *
   5  * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
   6  */
   7
   8 #include <dt-bindings/clock/oxsemi,ox810se.h>
   9 #include <dt-bindings/reset/oxsemi,ox810se.h>
  10
  11 / {
  12         #address-cells = <1>;
  13         #size-cells = <1>;
  14         compatible = "oxsemi,ox810se";
  15
  16         cpus {
  17                 #address-cells = <0>;
  18                 #size-cells = <0>;
  19
  20                 cpu {
  21                         device_type = "cpu";
  22                         compatible = "arm,arm926ej-s";
  23                         clocks = <&armclk>;
  24                 };
  25         };
  26
  27         memory {
  28                 device_type = "memory";
  29                 /* Max 256MB @ 0x48000000 */
  30                 reg = <0x48000000 0x10000000>;
  31         };
  32
  33         clocks {
  34                 osc: oscillator {
  35                         compatible = "fixed-clock";
  36                         #clock-cells = <0>;
  37                         clock-frequency = <25000000>;
  38                 };
  39
  40                 gmacclk: gmacclk {
  41                         compatible = "fixed-clock";
  42                         #clock-cells = <0>;
  43                         clock-frequency = <125000000>;
  44                 };
  45
  46                 rpsclk: rpsclk {
  47                         compatible = "fixed-factor-clock";
  48                         #clock-cells = <0>;
  49                         clock-div = <1>;
  50                         clock-mult = <1>;
  51                         clocks = <&osc>;
  52                 };
  53
  54                 pll400: pll400 {
  55                         compatible = "fixed-clock";
  56                         #clock-cells = <0>;
  57                         clock-frequency = <733333333>;
  58                 };
  59
  60                 sysclk: sysclk {
  61                         compatible = "fixed-factor-clock";
  62                         #clock-cells = <0>;
  63                         clock-div = <4>;
  64                         clock-mult = <1>;
  65                         clocks = <&pll400>;
  66                 };
  67
  68                 armclk: armclk {
  69                         compatible = "fixed-factor-clock";
  70                         #clock-cells = <0>;
  71                         clock-div = <2>;
  72                         clock-mult = <1>;
  73                         clocks = <&pll400>;
  74                 };
  75         };
  76
  77         soc {
  78                 #address-cells = <1>;
  79                 #size-cells = <1>;
  80                 compatible = "simple-bus";
  81                 ranges;
  82                 interrupt-parent = <&intc>;
  83
  84                 etha: ethernet@40400000 {
  85                         compatible = "oxsemi,ox810se-dwmac", "snps,dwmac";
  86                         reg = <0x40400000 0x2000>;
  87                         interrupts = <8>;
  88                         interrupt-names = "macirq";
  89                         mac-address = [000000000000]; /* Filled in by U-Boot */
  90                         phy-mode = "rgmii";
  91
  92                         clocks = <&stdclk 6>, <&gmacclk>;
  93                         clock-names = "gmac", "stmmaceth";
  94                         resets = <&reset 6>;
  95
  96                         /* Regmap for sys registers */
  97                         oxsemi,sys-ctrl = <&sys>;
  98
  99                         status = "disabled";
 100                 };
 101
 102                 apb-bridge@44000000 {
 103                         #address-cells = <1>;
 104                         #size-cells = <1>;
 105                         compatible = "simple-bus";
 106                         ranges = <0 0x44000000 0x1000000>;
 107
 108                         pinctrl: pinctrl {
 109                                 compatible = "oxsemi,ox810se-pinctrl";
 110
 111                                 /* Regmap for sys registers */
 112                                 oxsemi,sys-ctrl = <&sys>;
 113
 114                                 pinctrl_uart0: uart0 {
 115                                         uart0a {
 116                                                 pins = "gpio31";
 117                                                 function = "fct3";
 118                                         };
 119                                         uart0b {
 120                                                 pins = "gpio32";
 121                                                 function = "fct3";
 122                                         };
 123                                 };
 124
 125                                 pinctrl_uart0_modem: uart0_modem {
 126                                         uart0c {
 127                                                 pins = "gpio27";
 128                                                 function = "fct3";
 129                                         };
 130                                         uart0d {
 131                                                 pins = "gpio28";
 132                                                 function = "fct3";
 133                                         };
 134                                         uart0e {
 135                                                 pins = "gpio29";
 136                                                 function = "fct3";
 137                                         };
 138                                         uart0f {
 139                                                 pins = "gpio30";
 140                                                 function = "fct3";
 141                                         };
 142                                         uart0g {
 143                                                 pins = "gpio33";
 144                                                 function = "fct3";
 145                                         };
 146                                         uart0h {
 147                                                 pins = "gpio34";
 148                                                 function = "fct3";
 149                                         };
 150                                 };
 151
 152                                 pinctrl_uart1: uart1 {
 153                                         uart1a {
 154                                                 pins = "gpio20";
 155                                                 function = "fct3";
 156                                         };
 157                                         uart1b {
 158                                                 pins = "gpio22";
 159                                                 function = "fct3";
 160                                         };
 161                                 };
 162
 163                                 pinctrl_uart1_modem: uart1_modem {
 164                                         uart1c {
 165                                                 pins = "gpio8";
 166                                                 function = "fct3";
 167                                         };
 168                                         uart1d {
 169                                                 pins = "gpio9";
 170                                                 function = "fct3";
 171                                         };
 172                                         uart1e {
 173                                                 pins = "gpio23";
 174                                                 function = "fct3";
 175                                         };
 176                                         uart1f {
 177                                                 pins = "gpio24";
 178                                                 function = "fct3";
 179                                         };
 180                                         uart1g {
 181                                                 pins = "gpio25";
 182                                                 function = "fct3";
 183                                         };
 184                                         uart1h {
 185                                                 pins = "gpio26";
 186                                                 function = "fct3";
 187                                         };
 188                                 };
 189
 190                                 pinctrl_uart2: uart2 {
 191                                         uart2a {
 192                                                 pins = "gpio6";
 193                                                 function = "fct3";
 194                                         };
 195                                         uart2b {
 196                                                 pins = "gpio7";
 197                                                 function = "fct3";
 198                                         };
 199                                 };
 200
 201                                 pinctrl_uart2_modem: uart2_modem {
 202                                         uart2c {
 203                                                 pins = "gpio0";
 204                                                 function = "fct3";
 205                                         };
 206                                         uart2d {
 207                                                 pins = "gpio1";
 208                                                 function = "fct3";
 209                                         };
 210                                         uart2e {
 211                                                 pins = "gpio2";
 212                                                 function = "fct3";
 213                                         };
 214                                         uart2f {
 215                                                 pins = "gpio3";
 216                                                 function = "fct3";
 217                                         };
 218                                         uart2g {
 219                                                 pins = "gpio4";
 220                                                 function = "fct3";
 221                                         };
 222                                         uart2h {
 223                                                 pins = "gpio5";
 224                                                 function = "fct3";
 225                                         };
 226                                 };
 227                         };
 228
 229                         gpio0: gpio@0 {
 230                                 compatible = "oxsemi,ox810se-gpio";
 231                                 reg = <0x000000 0x100000>;
 232                                 interrupts = <21>;
 233                                 #gpio-cells = <2>;
 234                                 gpio-controller;
 235                                 interrupt-controller;
 236                                 #interrupt-cells = <2>;
 237                                 ngpios = <32>;
 238                                 oxsemi,gpio-bank = <0>;
 239                                 gpio-ranges = <&pinctrl 0 0 32>;
 240                         };
 241
 242                         gpio1: gpio@100000 {
 243                                 compatible = "oxsemi,ox810se-gpio";
 244                                 reg = <0x100000 0x100000>;
 245                                 interrupts = <22>;
 246                                 #gpio-cells = <2>;
 247                                 gpio-controller;
 248                                 interrupt-controller;
 249                                 #interrupt-cells = <2>;
 250                                 ngpios = <3>;
 251                                 oxsemi,gpio-bank = <1>;
 252                                 gpio-ranges = <&pinctrl 0 32 3>;
 253                         };
 254
 255                         uart0: serial@200000 {
 256                                compatible = "ns16550a";
 257                                reg = <0x200000 0x100000>;
 258                                clocks = <&sysclk>;
 259                                interrupts = <23>;
 260                                reg-shift = <0>;
 261                                fifo-size = <16>;
 262                                reg-io-width = <1>;
 263                                current-speed = <115200>;
 264                                no-loopback-test;
 265                                status = "disabled";
 266                                resets = <&reset RESET_UART1>;
 267                         };
 268
 269                         uart1: serial@300000 {
 270                                compatible = "ns16550a";
 271                                reg = <0x300000 0x100000>;
 272                                clocks = <&sysclk>;
 273                                interrupts = <24>;
 274                                reg-shift = <0>;
 275                                fifo-size = <16>;
 276                                reg-io-width = <1>;
 277                                current-speed = <115200>;
 278                                no-loopback-test;
 279                                status = "disabled";
 280                                resets = <&reset RESET_UART2>;
 281                         };
 282
 283                         uart2: serial@900000 {
 284                                compatible = "ns16550a";
 285                                reg = <0x900000 0x100000>;
 286                                clocks = <&sysclk>;
 287                                interrupts = <29>;
 288                                reg-shift = <0>;
 289                                fifo-size = <16>;
 290                                reg-io-width = <1>;
 291                                current-speed = <115200>;
 292                                no-loopback-test;
 293                                status = "disabled";
 294                                resets = <&reset RESET_UART3>;
 295                         };
 296
 297                         uart3: serial@a00000 {
 298                                compatible = "ns16550a";
 299                                reg = <0xa00000 0x100000>;
 300                                clocks = <&sysclk>;
 301                                interrupts = <30>;
 302                                reg-shift = <0>;
 303                                fifo-size = <16>;
 304                                reg-io-width = <1>;
 305                                current-speed = <115200>;
 306                                no-loopback-test;
 307                                status = "disabled";
 308                                resets = <&reset RESET_UART4>;
 309                         };
 310                 };
 311
 312                 apb-bridge@45000000 {
 313                         #address-cells = <1>;
 314                         #size-cells = <1>;
 315                         compatible = "simple-bus";
 316                         ranges = <0 0x45000000 0x1000000>;
 317
 318                         sys: sys-ctrl@0 {
 319                                 compatible = "oxsemi,ox810se-sys-ctrl", "syscon", "simple-mfd";
 320                                 reg = <0x000000 0x100000>;
 321
 322                                 reset: reset-controller {
 323                                         compatible = "oxsemi,ox810se-reset";
 324                                         #reset-cells = <1>;
 325                                 };
 326
 327                                 stdclk: stdclk {
 328                                         compatible = "oxsemi,ox810se-stdclk";
 329                                         #clock-cells = <1>;
 330                                 };
 331                         };
 332
 333                         rps@300000 {
 334                                 #address-cells = <1>;
 335                                 #size-cells = <1>;
 336                                 compatible = "simple-bus";
 337                                 ranges = <0 0x300000 0x100000>;
 338
 339                                 intc: interrupt-controller@0 {
 340                                         compatible = "oxsemi,ox810se-rps-irq";
 341                                         interrupt-controller;
 342                                         reg = <0 0x200>;
 343                                         #interrupt-cells = <1>;
 344                                         valid-mask = <0xffffffff>;
 345                                         clear-mask = <0xffffffff>;
 346                                 };
 347
 348                                 timer0: timer@200 {
 349                                         compatible = "oxsemi,ox810se-rps-timer";
 350                                         reg = <0x200 0x40>;
 351                                         clocks = <&rpsclk>;
 352                                         interrupts = <4 5>;
 353                                 };
 354                         };
 355                 };
 356         };
 357 };