1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * ox810se.dtsi - Device tree file for Oxford Semiconductor OX810SE SoC
5 * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
8 #include <dt-bindings/clock/oxsemi,ox810se.h>
9 #include <dt-bindings/reset/oxsemi,ox810se.h>
14 compatible = "oxsemi,ox810se";
22 compatible = "arm,arm926ej-s";
28 device_type = "memory";
29 /* Max 256MB @ 0x48000000 */
30 reg = <0x48000000 0x10000000>;
35 compatible = "fixed-clock";
37 clock-frequency = <25000000>;
41 compatible = "fixed-clock";
43 clock-frequency = <125000000>;
47 compatible = "fixed-factor-clock";
55 compatible = "fixed-clock";
57 clock-frequency = <733333333>;
61 compatible = "fixed-factor-clock";
69 compatible = "fixed-factor-clock";
80 compatible = "simple-bus";
82 interrupt-parent = <&intc>;
84 etha: ethernet@40400000 {
85 compatible = "oxsemi,ox810se-dwmac", "snps,dwmac";
86 reg = <0x40400000 0x2000>;
88 interrupt-names = "macirq";
89 mac-address = [000000000000]; /* Filled in by U-Boot */
92 clocks = <&stdclk 6>, <&gmacclk>;
93 clock-names = "gmac", "stmmaceth";
96 /* Regmap for sys registers */
97 oxsemi,sys-ctrl = <&sys>;
102 apb-bridge@44000000 {
103 #address-cells = <1>;
105 compatible = "simple-bus";
106 ranges = <0 0x44000000 0x1000000>;
109 compatible = "oxsemi,ox810se-pinctrl";
111 /* Regmap for sys registers */
112 oxsemi,sys-ctrl = <&sys>;
114 pinctrl_uart0: uart0 {
125 pinctrl_uart0_modem: uart0_modem {
152 pinctrl_uart1: uart1 {
163 pinctrl_uart1_modem: uart1_modem {
190 pinctrl_uart2: uart2 {
201 pinctrl_uart2_modem: uart2_modem {
230 compatible = "oxsemi,ox810se-gpio";
231 reg = <0x000000 0x100000>;
235 interrupt-controller;
236 #interrupt-cells = <2>;
238 oxsemi,gpio-bank = <0>;
239 gpio-ranges = <&pinctrl 0 0 32>;
243 compatible = "oxsemi,ox810se-gpio";
244 reg = <0x100000 0x100000>;
248 interrupt-controller;
249 #interrupt-cells = <2>;
251 oxsemi,gpio-bank = <1>;
252 gpio-ranges = <&pinctrl 0 32 3>;
255 uart0: serial@200000 {
256 compatible = "ns16550a";
257 reg = <0x200000 0x100000>;
263 current-speed = <115200>;
266 resets = <&reset RESET_UART1>;
269 uart1: serial@300000 {
270 compatible = "ns16550a";
271 reg = <0x300000 0x100000>;
277 current-speed = <115200>;
280 resets = <&reset RESET_UART2>;
283 uart2: serial@900000 {
284 compatible = "ns16550a";
285 reg = <0x900000 0x100000>;
291 current-speed = <115200>;
294 resets = <&reset RESET_UART3>;
297 uart3: serial@a00000 {
298 compatible = "ns16550a";
299 reg = <0xa00000 0x100000>;
305 current-speed = <115200>;
308 resets = <&reset RESET_UART4>;
312 apb-bridge@45000000 {
313 #address-cells = <1>;
315 compatible = "simple-bus";
316 ranges = <0 0x45000000 0x1000000>;
319 compatible = "oxsemi,ox810se-sys-ctrl", "syscon", "simple-mfd";
320 reg = <0x000000 0x100000>;
322 reset: reset-controller {
323 compatible = "oxsemi,ox810se-reset";
328 compatible = "oxsemi,ox810se-stdclk";
334 #address-cells = <1>;
336 compatible = "simple-bus";
337 ranges = <0 0x300000 0x100000>;
339 intc: interrupt-controller@0 {
340 compatible = "oxsemi,ox810se-rps-irq";
341 interrupt-controller;
343 #interrupt-cells = <1>;
344 valid-mask = <0xffffffff>;
345 clear-mask = <0xffffffff>;
349 compatible = "oxsemi,ox810se-rps-timer";