2 * Actions Semi S500 SoC
4 * Copyright (c) 2016-2017 Andreas Färber
6 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/owl-s500-powergate.h>
13 compatible = "actions,s500";
14 interrupt-parent = <&gic>;
30 compatible = "arm,cortex-a9";
32 enable-method = "actions,s500-smp";
37 compatible = "arm,cortex-a9";
39 enable-method = "actions,s500-smp";
44 compatible = "arm,cortex-a9";
46 enable-method = "actions,s500-smp";
47 power-domains = <&sps S500_PD_CPU2>;
52 compatible = "arm,cortex-a9";
54 enable-method = "actions,s500-smp";
55 power-domains = <&sps S500_PD_CPU3>;
60 compatible = "arm,cortex-a9-pmu";
61 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
62 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
63 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
64 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
65 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
69 compatible = "fixed-clock";
70 clock-frequency = <24000000>;
75 compatible = "simple-bus";
81 compatible = "arm,cortex-a9-scu";
82 reg = <0xb0020000 0x100>;
85 global_timer: timer@b0020200 {
86 compatible = "arm,cortex-a9-global-timer";
87 reg = <0xb0020200 0x100>;
88 interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
92 twd_timer: timer@b0020600 {
93 compatible = "arm,cortex-a9-twd-timer";
94 reg = <0xb0020600 0x20>;
95 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
99 twd_wdt: wdt@b0020620 {
100 compatible = "arm,cortex-a9-twd-wdt";
101 reg = <0xb0020620 0xe0>;
102 interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
106 gic: interrupt-controller@b0021000 {
107 compatible = "arm,cortex-a9-gic";
108 reg = <0xb0021000 0x1000>,
110 interrupt-controller;
111 #interrupt-cells = <3>;
114 l2: cache-controller@b0022000 {
115 compatible = "arm,pl310-cache";
116 reg = <0xb0022000 0x1000>;
119 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
120 arm,tag-latency = <3 3 2>;
121 arm,data-latency = <5 3 3>;
124 uart0: serial@b0120000 {
125 compatible = "actions,s500-uart", "actions,owl-uart";
126 reg = <0xb0120000 0x2000>;
127 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
131 uart1: serial@b0122000 {
132 compatible = "actions,s500-uart", "actions,owl-uart";
133 reg = <0xb0122000 0x2000>;
134 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
138 uart2: serial@b0124000 {
139 compatible = "actions,s500-uart", "actions,owl-uart";
140 reg = <0xb0124000 0x2000>;
141 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
145 uart3: serial@b0126000 {
146 compatible = "actions,s500-uart", "actions,owl-uart";
147 reg = <0xb0126000 0x2000>;
148 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
152 uart4: serial@b0128000 {
153 compatible = "actions,s500-uart", "actions,owl-uart";
154 reg = <0xb0128000 0x2000>;
155 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
159 uart5: serial@b012a000 {
160 compatible = "actions,s500-uart", "actions,owl-uart";
161 reg = <0xb012a000 0x2000>;
162 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
166 uart6: serial@b012c000 {
167 compatible = "actions,s500-uart", "actions,owl-uart";
168 reg = <0xb012c000 0x2000>;
169 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
173 timer: timer@b0168000 {
174 compatible = "actions,s500-timer";
175 reg = <0xb0168000 0x8000>;
176 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
177 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
178 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
179 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
180 interrupt-names = "2hz0", "2hz1", "timer0", "timer1";
183 sps: power-controller@b01b0100 {
184 compatible = "actions,s500-sps";
185 reg = <0xb01b0100 0x100>;
186 #power-domain-cells = <1>;