1 // SPDX-License-Identifier: GPL-2.0-only
2 // Copyright (C) 2012 Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
4 #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
9 model = "Marvell Orion5x SoC";
10 compatible = "marvell,orion5x";
11 interrupt-parent = <&intc>;
20 controller = <&mbusc>;
22 devbus_bootcs: devbus-bootcs {
23 compatible = "marvell,orion-devbus";
24 reg = <MBUS_ID(0xf0, 0x01) 0x1046C 0x4>;
25 ranges = <0 MBUS_ID(0x01, 0x0f) 0 0xffffffff>;
28 clocks = <&core_clk 0>;
32 devbus_cs0: devbus-cs0 {
33 compatible = "marvell,orion-devbus";
34 reg = <MBUS_ID(0xf0, 0x01) 0x1045C 0x4>;
35 ranges = <0 MBUS_ID(0x01, 0x1e) 0 0xffffffff>;
38 clocks = <&core_clk 0>;
42 devbus_cs1: devbus-cs1 {
43 compatible = "marvell,orion-devbus";
44 reg = <MBUS_ID(0xf0, 0x01) 0x10460 0x4>;
45 ranges = <0 MBUS_ID(0x01, 0x1d) 0 0xffffffff>;
48 clocks = <&core_clk 0>;
52 devbus_cs2: devbus-cs2 {
53 compatible = "marvell,orion-devbus";
54 reg = <MBUS_ID(0xf0, 0x01) 0x10464 0x4>;
55 ranges = <0 MBUS_ID(0x01, 0x1b) 0 0xffffffff>;
58 clocks = <&core_clk 0>;
63 compatible = "simple-bus";
66 ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
69 compatible = "marvell,orion-gpio";
75 #interrupt-cells = <2>;
76 interrupts = <6>, <7>, <8>, <9>;
80 compatible = "marvell,orion-spi";
89 compatible = "marvell,mv64xxx-i2c";
94 clocks = <&core_clk 0>;
99 compatible = "ns16550a";
100 reg = <0x12000 0x100>;
103 clocks = <&core_clk 0>;
107 uart1: serial@12100 {
108 compatible = "ns16550a";
109 reg = <0x12100 0x100>;
112 clocks = <&core_clk 0>;
116 bridge_intc: bridge-interrupt-ctrl@20110 {
117 compatible = "marvell,orion-bridge-intc";
118 interrupt-controller;
119 #interrupt-cells = <1>;
122 marvell,#interrupts = <4>;
125 intc: interrupt-controller@20200 {
126 compatible = "marvell,orion-intc";
127 interrupt-controller;
128 #interrupt-cells = <1>;
129 reg = <0x20200 0x08>;
133 compatible = "marvell,orion-timer";
134 reg = <0x20300 0x20>;
135 interrupt-parent = <&bridge_intc>;
136 interrupts = <1>, <2>;
137 clocks = <&core_clk 0>;
141 compatible = "marvell,orion-wdt";
142 reg = <0x20300 0x28>, <0x20108 0x4>;
143 interrupt-parent = <&bridge_intc>;
145 clocks = <&core_clk 0>;
150 compatible = "marvell,orion-ehci";
151 reg = <0x50000 0x1000>;
156 xor: dma-controller@60900 {
157 compatible = "marvell,orion-xor";
175 eth: ethernet-controller@72000 {
176 compatible = "marvell,orion-eth";
177 #address-cells = <1>;
179 reg = <0x72000 0x4000>;
180 marvell,tx-checksum-limit = <1600>;
183 ethport: ethernet-port@0 {
184 compatible = "marvell,orion-eth-port";
187 /* overwrite MAC address in bootloader */
188 local-mac-address = [00 00 00 00 00 00];
189 /* set phy-handle property in board file */
193 mdio: mdio-bus@72004 {
194 compatible = "marvell,orion-mdio";
195 #address-cells = <1>;
197 reg = <0x72004 0x84>;
201 /* add phy nodes in board file */
205 compatible = "marvell,orion-sata";
206 reg = <0x80000 0x5000>;
212 compatible = "marvell,orion-crypto";
213 reg = <0x90000 0x10000>;
216 marvell,crypto-srams = <&crypto_sram>;
217 marvell,crypto-sram-size = <0x800>;
222 compatible = "marvell,orion-ehci";
223 reg = <0xa0000 0x1000>;
229 crypto_sram: sa-sram {
230 compatible = "mmio-sram";
231 reg = <MBUS_ID(0x09, 0x00) 0x0 0x800>;
232 #address-cells = <1>;