1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for OMAP5 clock data
5 * Copyright (C) 2013 Texas Instruments, Inc.
8 pad_clks_src_ck: pad_clks_src_ck {
10 compatible = "fixed-clock";
11 clock-output-names = "pad_clks_src_ck";
12 clock-frequency = <12000000>;
15 pad_clks_ck: pad_clks_ck@108 {
17 compatible = "ti,gate-clock";
18 clock-output-names = "pad_clks_ck";
19 clocks = <&pad_clks_src_ck>;
24 secure_32k_clk_src_ck: secure_32k_clk_src_ck {
26 compatible = "fixed-clock";
27 clock-output-names = "secure_32k_clk_src_ck";
28 clock-frequency = <32768>;
31 slimbus_src_clk: slimbus_src_clk {
33 compatible = "fixed-clock";
34 clock-output-names = "slimbus_src_clk";
35 clock-frequency = <12000000>;
38 slimbus_clk: slimbus_clk@108 {
40 compatible = "ti,gate-clock";
41 clock-output-names = "slimbus_clk";
42 clocks = <&slimbus_src_clk>;
47 sys_32k_ck: sys_32k_ck {
49 compatible = "fixed-clock";
50 clock-output-names = "sys_32k_ck";
51 clock-frequency = <32768>;
54 virt_12000000_ck: virt_12000000_ck {
56 compatible = "fixed-clock";
57 clock-output-names = "virt_12000000_ck";
58 clock-frequency = <12000000>;
61 virt_13000000_ck: virt_13000000_ck {
63 compatible = "fixed-clock";
64 clock-output-names = "virt_13000000_ck";
65 clock-frequency = <13000000>;
68 virt_16800000_ck: virt_16800000_ck {
70 compatible = "fixed-clock";
71 clock-output-names = "virt_16800000_ck";
72 clock-frequency = <16800000>;
75 virt_19200000_ck: virt_19200000_ck {
77 compatible = "fixed-clock";
78 clock-output-names = "virt_19200000_ck";
79 clock-frequency = <19200000>;
82 virt_26000000_ck: virt_26000000_ck {
84 compatible = "fixed-clock";
85 clock-output-names = "virt_26000000_ck";
86 clock-frequency = <26000000>;
89 virt_27000000_ck: virt_27000000_ck {
91 compatible = "fixed-clock";
92 clock-output-names = "virt_27000000_ck";
93 clock-frequency = <27000000>;
96 virt_38400000_ck: virt_38400000_ck {
98 compatible = "fixed-clock";
99 clock-output-names = "virt_38400000_ck";
100 clock-frequency = <38400000>;
103 xclk60mhsp1_ck: xclk60mhsp1_ck {
105 compatible = "fixed-clock";
106 clock-output-names = "xclk60mhsp1_ck";
107 clock-frequency = <60000000>;
110 xclk60mhsp2_ck: xclk60mhsp2_ck {
112 compatible = "fixed-clock";
113 clock-output-names = "xclk60mhsp2_ck";
114 clock-frequency = <60000000>;
117 dpll_abe_ck: dpll_abe_ck@1e0 {
119 compatible = "ti,omap4-dpll-m4xen-clock";
120 clock-output-names = "dpll_abe_ck";
121 clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>;
122 reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>;
125 dpll_abe_x2_ck: dpll_abe_x2_ck {
127 compatible = "ti,omap4-dpll-x2-clock";
128 clock-output-names = "dpll_abe_x2_ck";
129 clocks = <&dpll_abe_ck>;
132 dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@1f0 {
134 compatible = "ti,divider-clock";
135 clock-output-names = "dpll_abe_m2x2_ck";
136 clocks = <&dpll_abe_x2_ck>;
139 ti,index-starts-at-one;
142 abe_24m_fclk: abe_24m_fclk {
144 compatible = "fixed-factor-clock";
145 clock-output-names = "abe_24m_fclk";
146 clocks = <&dpll_abe_m2x2_ck>;
151 abe_clk: abe_clk@108 {
153 compatible = "ti,divider-clock";
154 clock-output-names = "abe_clk";
155 clocks = <&dpll_abe_m2x2_ck>;
158 ti,index-power-of-two;
161 abe_iclk: abe_iclk@528 {
163 compatible = "ti,divider-clock";
164 clock-output-names = "abe_iclk";
165 clocks = <&aess_fclk>;
168 ti,dividers = <2>, <1>;
171 abe_lp_clk_div: abe_lp_clk_div {
173 compatible = "fixed-factor-clock";
174 clock-output-names = "abe_lp_clk_div";
175 clocks = <&dpll_abe_m2x2_ck>;
180 dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@1f4 {
182 compatible = "ti,divider-clock";
183 clock-output-names = "dpll_abe_m3x2_ck";
184 clocks = <&dpll_abe_x2_ck>;
187 ti,index-starts-at-one;
190 dpll_core_byp_mux: dpll_core_byp_mux@12c {
192 compatible = "ti,mux-clock";
193 clock-output-names = "dpll_core_byp_mux";
194 clocks = <&sys_clkin>, <&dpll_abe_m3x2_ck>;
199 dpll_core_ck: dpll_core_ck@120 {
201 compatible = "ti,omap4-dpll-core-clock";
202 clock-output-names = "dpll_core_ck";
203 clocks = <&sys_clkin>, <&dpll_core_byp_mux>;
204 reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>;
207 dpll_core_x2_ck: dpll_core_x2_ck {
209 compatible = "ti,omap4-dpll-x2-clock";
210 clock-output-names = "dpll_core_x2_ck";
211 clocks = <&dpll_core_ck>;
214 dpll_core_h21x2_ck: dpll_core_h21x2_ck@150 {
216 compatible = "ti,divider-clock";
217 clock-output-names = "dpll_core_h21x2_ck";
218 clocks = <&dpll_core_x2_ck>;
221 ti,index-starts-at-one;
226 compatible = "fixed-factor-clock";
227 clock-output-names = "c2c_fclk";
228 clocks = <&dpll_core_h21x2_ck>;
235 compatible = "fixed-factor-clock";
236 clock-output-names = "c2c_iclk";
237 clocks = <&c2c_fclk>;
242 dpll_core_h11x2_ck: dpll_core_h11x2_ck@138 {
244 compatible = "ti,divider-clock";
245 clock-output-names = "dpll_core_h11x2_ck";
246 clocks = <&dpll_core_x2_ck>;
249 ti,index-starts-at-one;
252 dpll_core_h12x2_ck: dpll_core_h12x2_ck@13c {
254 compatible = "ti,divider-clock";
255 clock-output-names = "dpll_core_h12x2_ck";
256 clocks = <&dpll_core_x2_ck>;
259 ti,index-starts-at-one;
262 dpll_core_h13x2_ck: dpll_core_h13x2_ck@140 {
264 compatible = "ti,divider-clock";
265 clock-output-names = "dpll_core_h13x2_ck";
266 clocks = <&dpll_core_x2_ck>;
269 ti,index-starts-at-one;
272 dpll_core_h14x2_ck: dpll_core_h14x2_ck@144 {
274 compatible = "ti,divider-clock";
275 clock-output-names = "dpll_core_h14x2_ck";
276 clocks = <&dpll_core_x2_ck>;
279 ti,index-starts-at-one;
282 dpll_core_h22x2_ck: dpll_core_h22x2_ck@154 {
284 compatible = "ti,divider-clock";
285 clock-output-names = "dpll_core_h22x2_ck";
286 clocks = <&dpll_core_x2_ck>;
289 ti,index-starts-at-one;
292 dpll_core_h23x2_ck: dpll_core_h23x2_ck@158 {
294 compatible = "ti,divider-clock";
295 clock-output-names = "dpll_core_h23x2_ck";
296 clocks = <&dpll_core_x2_ck>;
299 ti,index-starts-at-one;
302 dpll_core_h24x2_ck: dpll_core_h24x2_ck@15c {
304 compatible = "ti,divider-clock";
305 clock-output-names = "dpll_core_h24x2_ck";
306 clocks = <&dpll_core_x2_ck>;
309 ti,index-starts-at-one;
312 dpll_core_m2_ck: dpll_core_m2_ck@130 {
314 compatible = "ti,divider-clock";
315 clock-output-names = "dpll_core_m2_ck";
316 clocks = <&dpll_core_ck>;
319 ti,index-starts-at-one;
322 dpll_core_m3x2_ck: dpll_core_m3x2_ck@134 {
324 compatible = "ti,divider-clock";
325 clock-output-names = "dpll_core_m3x2_ck";
326 clocks = <&dpll_core_x2_ck>;
329 ti,index-starts-at-one;
332 iva_dpll_hs_clk_div: iva_dpll_hs_clk_div {
334 compatible = "fixed-factor-clock";
335 clock-output-names = "iva_dpll_hs_clk_div";
336 clocks = <&dpll_core_h12x2_ck>;
341 dpll_iva_byp_mux: dpll_iva_byp_mux@1ac {
343 compatible = "ti,mux-clock";
344 clock-output-names = "dpll_iva_byp_mux";
345 clocks = <&sys_clkin>, <&iva_dpll_hs_clk_div>;
350 dpll_iva_ck: dpll_iva_ck@1a0 {
352 compatible = "ti,omap4-dpll-clock";
353 clock-output-names = "dpll_iva_ck";
354 clocks = <&sys_clkin>, <&dpll_iva_byp_mux>;
355 reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;
356 assigned-clocks = <&dpll_iva_ck>;
357 assigned-clock-rates = <1165000000>;
360 dpll_iva_x2_ck: dpll_iva_x2_ck {
362 compatible = "ti,omap4-dpll-x2-clock";
363 clock-output-names = "dpll_iva_x2_ck";
364 clocks = <&dpll_iva_ck>;
367 dpll_iva_h11x2_ck: dpll_iva_h11x2_ck@1b8 {
369 compatible = "ti,divider-clock";
370 clock-output-names = "dpll_iva_h11x2_ck";
371 clocks = <&dpll_iva_x2_ck>;
374 ti,index-starts-at-one;
375 assigned-clocks = <&dpll_iva_h11x2_ck>;
376 assigned-clock-rates = <465920000>;
379 dpll_iva_h12x2_ck: dpll_iva_h12x2_ck@1bc {
381 compatible = "ti,divider-clock";
382 clock-output-names = "dpll_iva_h12x2_ck";
383 clocks = <&dpll_iva_x2_ck>;
386 ti,index-starts-at-one;
387 assigned-clocks = <&dpll_iva_h12x2_ck>;
388 assigned-clock-rates = <388300000>;
391 mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div {
393 compatible = "fixed-factor-clock";
394 clock-output-names = "mpu_dpll_hs_clk_div";
395 clocks = <&dpll_core_h12x2_ck>;
400 dpll_mpu_ck: dpll_mpu_ck@160 {
402 compatible = "ti,omap5-mpu-dpll-clock";
403 clock-output-names = "dpll_mpu_ck";
404 clocks = <&sys_clkin>, <&mpu_dpll_hs_clk_div>;
405 reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>;
408 dpll_mpu_m2_ck: dpll_mpu_m2_ck@170 {
410 compatible = "ti,divider-clock";
411 clock-output-names = "dpll_mpu_m2_ck";
412 clocks = <&dpll_mpu_ck>;
415 ti,index-starts-at-one;
418 per_dpll_hs_clk_div: per_dpll_hs_clk_div {
420 compatible = "fixed-factor-clock";
421 clock-output-names = "per_dpll_hs_clk_div";
422 clocks = <&dpll_abe_m3x2_ck>;
427 usb_dpll_hs_clk_div: usb_dpll_hs_clk_div {
429 compatible = "fixed-factor-clock";
430 clock-output-names = "usb_dpll_hs_clk_div";
431 clocks = <&dpll_abe_m3x2_ck>;
436 l3_iclk_div: l3_iclk_div@100 {
438 compatible = "ti,divider-clock";
439 clock-output-names = "l3_iclk_div";
443 clocks = <&dpll_core_h12x2_ck>;
444 ti,index-power-of-two;
447 gpu_l3_iclk: gpu_l3_iclk {
449 compatible = "fixed-factor-clock";
450 clock-output-names = "gpu_l3_iclk";
451 clocks = <&l3_iclk_div>;
456 l4_root_clk_div: l4_root_clk_div@100 {
458 compatible = "ti,divider-clock";
459 clock-output-names = "l4_root_clk_div";
463 clocks = <&l3_iclk_div>;
464 ti,index-power-of-two;
467 slimbus1_slimbus_clk: slimbus1_slimbus_clk@560 {
469 compatible = "ti,gate-clock";
470 clock-output-names = "slimbus1_slimbus_clk";
471 clocks = <&slimbus_clk>;
476 aess_fclk: aess_fclk@528 {
478 compatible = "ti,divider-clock";
479 clock-output-names = "aess_fclk";
486 mcasp_sync_mux_ck: mcasp_sync_mux_ck@540 {
488 compatible = "ti,mux-clock";
489 clock-output-names = "mcasp_sync_mux_ck";
490 clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
495 mcasp_gfclk: mcasp_gfclk@540 {
497 compatible = "ti,mux-clock";
498 clock-output-names = "mcasp_gfclk";
499 clocks = <&mcasp_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
506 compatible = "fixed-clock";
507 clock-output-names = "dummy_ck";
508 clock-frequency = <0>;
512 sys_clkin: sys_clkin@110 {
514 compatible = "ti,mux-clock";
515 clock-output-names = "sys_clkin";
516 clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
518 ti,index-starts-at-one;
521 abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux@108 {
523 compatible = "ti,mux-clock";
524 clock-output-names = "abe_dpll_bypass_clk_mux";
525 clocks = <&sys_clkin>, <&sys_32k_ck>;
529 abe_dpll_clk_mux: abe_dpll_clk_mux@10c {
531 compatible = "ti,mux-clock";
532 clock-output-names = "abe_dpll_clk_mux";
533 clocks = <&sys_clkin>, <&sys_32k_ck>;
537 custefuse_sys_gfclk_div: custefuse_sys_gfclk_div {
539 compatible = "fixed-factor-clock";
540 clock-output-names = "custefuse_sys_gfclk_div";
541 clocks = <&sys_clkin>;
546 dss_syc_gfclk_div: dss_syc_gfclk_div {
548 compatible = "fixed-factor-clock";
549 clock-output-names = "dss_syc_gfclk_div";
550 clocks = <&sys_clkin>;
555 wkupaon_iclk_mux: wkupaon_iclk_mux@108 {
557 compatible = "ti,mux-clock";
558 clock-output-names = "wkupaon_iclk_mux";
559 clocks = <&sys_clkin>, <&abe_lp_clk_div>;
563 l3instr_ts_gclk_div: l3instr_ts_gclk_div {
565 compatible = "fixed-factor-clock";
566 clock-output-names = "l3instr_ts_gclk_div";
567 clocks = <&wkupaon_iclk_mux>;
575 dpll_per_byp_mux: dpll_per_byp_mux@14c {
577 compatible = "ti,mux-clock";
578 clock-output-names = "dpll_per_byp_mux";
579 clocks = <&sys_clkin>, <&per_dpll_hs_clk_div>;
584 dpll_per_ck: dpll_per_ck@140 {
586 compatible = "ti,omap4-dpll-clock";
587 clock-output-names = "dpll_per_ck";
588 clocks = <&sys_clkin>, <&dpll_per_byp_mux>;
589 reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>;
592 dpll_per_x2_ck: dpll_per_x2_ck {
594 compatible = "ti,omap4-dpll-x2-clock";
595 clock-output-names = "dpll_per_x2_ck";
596 clocks = <&dpll_per_ck>;
599 dpll_per_h11x2_ck: dpll_per_h11x2_ck@158 {
601 compatible = "ti,divider-clock";
602 clock-output-names = "dpll_per_h11x2_ck";
603 clocks = <&dpll_per_x2_ck>;
606 ti,index-starts-at-one;
609 dpll_per_h12x2_ck: dpll_per_h12x2_ck@15c {
611 compatible = "ti,divider-clock";
612 clock-output-names = "dpll_per_h12x2_ck";
613 clocks = <&dpll_per_x2_ck>;
616 ti,index-starts-at-one;
619 dpll_per_h14x2_ck: dpll_per_h14x2_ck@164 {
621 compatible = "ti,divider-clock";
622 clock-output-names = "dpll_per_h14x2_ck";
623 clocks = <&dpll_per_x2_ck>;
626 ti,index-starts-at-one;
629 dpll_per_m2_ck: dpll_per_m2_ck@150 {
631 compatible = "ti,divider-clock";
632 clock-output-names = "dpll_per_m2_ck";
633 clocks = <&dpll_per_ck>;
636 ti,index-starts-at-one;
639 dpll_per_m2x2_ck: dpll_per_m2x2_ck@150 {
641 compatible = "ti,divider-clock";
642 clock-output-names = "dpll_per_m2x2_ck";
643 clocks = <&dpll_per_x2_ck>;
646 ti,index-starts-at-one;
649 dpll_per_m3x2_ck: dpll_per_m3x2_ck@154 {
651 compatible = "ti,divider-clock";
652 clock-output-names = "dpll_per_m3x2_ck";
653 clocks = <&dpll_per_x2_ck>;
656 ti,index-starts-at-one;
659 dpll_unipro1_ck: dpll_unipro1_ck@200 {
661 compatible = "ti,omap4-dpll-clock";
662 clock-output-names = "dpll_unipro1_ck";
663 clocks = <&sys_clkin>, <&sys_clkin>;
664 reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>;
667 dpll_unipro1_clkdcoldo: dpll_unipro1_clkdcoldo {
669 compatible = "fixed-factor-clock";
670 clock-output-names = "dpll_unipro1_clkdcoldo";
671 clocks = <&dpll_unipro1_ck>;
676 dpll_unipro1_m2_ck: dpll_unipro1_m2_ck@210 {
678 compatible = "ti,divider-clock";
679 clock-output-names = "dpll_unipro1_m2_ck";
680 clocks = <&dpll_unipro1_ck>;
683 ti,index-starts-at-one;
686 dpll_unipro2_ck: dpll_unipro2_ck@1c0 {
688 compatible = "ti,omap4-dpll-clock";
689 clock-output-names = "dpll_unipro2_ck";
690 clocks = <&sys_clkin>, <&sys_clkin>;
691 reg = <0x01c0>, <0x01c4>, <0x01cc>, <0x01c8>;
694 dpll_unipro2_clkdcoldo: dpll_unipro2_clkdcoldo {
696 compatible = "fixed-factor-clock";
697 clock-output-names = "dpll_unipro2_clkdcoldo";
698 clocks = <&dpll_unipro2_ck>;
703 dpll_unipro2_m2_ck: dpll_unipro2_m2_ck@1d0 {
705 compatible = "ti,divider-clock";
706 clock-output-names = "dpll_unipro2_m2_ck";
707 clocks = <&dpll_unipro2_ck>;
710 ti,index-starts-at-one;
713 dpll_usb_byp_mux: dpll_usb_byp_mux@18c {
715 compatible = "ti,mux-clock";
716 clock-output-names = "dpll_usb_byp_mux";
717 clocks = <&sys_clkin>, <&usb_dpll_hs_clk_div>;
722 dpll_usb_ck: dpll_usb_ck@180 {
724 compatible = "ti,omap4-dpll-j-type-clock";
725 clock-output-names = "dpll_usb_ck";
726 clocks = <&sys_clkin>, <&dpll_usb_byp_mux>;
727 reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>;
730 dpll_usb_clkdcoldo: dpll_usb_clkdcoldo {
732 compatible = "fixed-factor-clock";
733 clock-output-names = "dpll_usb_clkdcoldo";
734 clocks = <&dpll_usb_ck>;
739 dpll_usb_m2_ck: dpll_usb_m2_ck@190 {
741 compatible = "ti,divider-clock";
742 clock-output-names = "dpll_usb_m2_ck";
743 clocks = <&dpll_usb_ck>;
746 ti,index-starts-at-one;
749 func_128m_clk: func_128m_clk {
751 compatible = "fixed-factor-clock";
752 clock-output-names = "func_128m_clk";
753 clocks = <&dpll_per_h11x2_ck>;
758 func_12m_fclk: func_12m_fclk {
760 compatible = "fixed-factor-clock";
761 clock-output-names = "func_12m_fclk";
762 clocks = <&dpll_per_m2x2_ck>;
767 func_24m_clk: func_24m_clk {
769 compatible = "fixed-factor-clock";
770 clock-output-names = "func_24m_clk";
771 clocks = <&dpll_per_m2_ck>;
776 func_48m_fclk: func_48m_fclk {
778 compatible = "fixed-factor-clock";
779 clock-output-names = "func_48m_fclk";
780 clocks = <&dpll_per_m2x2_ck>;
785 func_96m_fclk: func_96m_fclk {
787 compatible = "fixed-factor-clock";
788 clock-output-names = "func_96m_fclk";
789 clocks = <&dpll_per_m2x2_ck>;
794 l3init_60m_fclk: l3init_60m_fclk@104 {
796 compatible = "ti,divider-clock";
797 clock-output-names = "l3init_60m_fclk";
798 clocks = <&dpll_usb_m2_ck>;
800 ti,dividers = <1>, <8>;
803 iss_ctrlclk: iss_ctrlclk@1320 {
805 compatible = "ti,gate-clock";
806 clock-output-names = "iss_ctrlclk";
807 clocks = <&func_96m_fclk>;
812 lli_txphy_clk: lli_txphy_clk@f20 {
814 compatible = "ti,gate-clock";
815 clock-output-names = "lli_txphy_clk";
816 clocks = <&dpll_unipro1_clkdcoldo>;
821 lli_txphy_ls_clk: lli_txphy_ls_clk@f20 {
823 compatible = "ti,gate-clock";
824 clock-output-names = "lli_txphy_ls_clk";
825 clocks = <&dpll_unipro1_m2_ck>;
830 usb_phy_cm_clk32k: usb_phy_cm_clk32k@640 {
832 compatible = "ti,gate-clock";
833 clock-output-names = "usb_phy_cm_clk32k";
834 clocks = <&sys_32k_ck>;
839 fdif_fclk: fdif_fclk@1328 {
841 compatible = "ti,divider-clock";
842 clock-output-names = "fdif_fclk";
843 clocks = <&dpll_per_h11x2_ck>;
849 gpu_core_gclk_mux: gpu_core_gclk_mux@1520 {
851 compatible = "ti,mux-clock";
852 clock-output-names = "gpu_core_gclk_mux";
853 clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>;
858 gpu_hyd_gclk_mux: gpu_hyd_gclk_mux@1520 {
860 compatible = "ti,mux-clock";
861 clock-output-names = "gpu_hyd_gclk_mux";
862 clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>;
867 hsi_fclk: hsi_fclk@1638 {
869 compatible = "ti,divider-clock";
870 clock-output-names = "hsi_fclk";
871 clocks = <&dpll_per_m2x2_ck>;
878 &cm_core_clockdomains {
879 l3init_clkdm: l3init_clkdm {
880 compatible = "ti,clockdomain";
881 clock-output-names = "l3init_clkdm";
882 clocks = <&dpll_usb_ck>;
887 auxclk0_src_gate_ck: auxclk0_src_gate_ck@310 {
889 compatible = "ti,composite-no-wait-gate-clock";
890 clock-output-names = "auxclk0_src_gate_ck";
891 clocks = <&dpll_core_m3x2_ck>;
896 auxclk0_src_mux_ck: auxclk0_src_mux_ck@310 {
898 compatible = "ti,composite-mux-clock";
899 clock-output-names = "auxclk0_src_mux_ck";
900 clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
905 auxclk0_src_ck: auxclk0_src_ck {
907 compatible = "ti,composite-clock";
908 clock-output-names = "auxclk0_src_ck";
909 clocks = <&auxclk0_src_gate_ck>, <&auxclk0_src_mux_ck>;
912 auxclk0_ck: auxclk0_ck@310 {
914 compatible = "ti,divider-clock";
915 clock-output-names = "auxclk0_ck";
916 clocks = <&auxclk0_src_ck>;
922 auxclk1_src_gate_ck: auxclk1_src_gate_ck@314 {
924 compatible = "ti,composite-no-wait-gate-clock";
925 clock-output-names = "auxclk1_src_gate_ck";
926 clocks = <&dpll_core_m3x2_ck>;
931 auxclk1_src_mux_ck: auxclk1_src_mux_ck@314 {
933 compatible = "ti,composite-mux-clock";
934 clock-output-names = "auxclk1_src_mux_ck";
935 clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
940 auxclk1_src_ck: auxclk1_src_ck {
942 compatible = "ti,composite-clock";
943 clock-output-names = "auxclk1_src_ck";
944 clocks = <&auxclk1_src_gate_ck>, <&auxclk1_src_mux_ck>;
947 auxclk1_ck: auxclk1_ck@314 {
949 compatible = "ti,divider-clock";
950 clock-output-names = "auxclk1_ck";
951 clocks = <&auxclk1_src_ck>;
957 auxclk2_src_gate_ck: auxclk2_src_gate_ck@318 {
959 compatible = "ti,composite-no-wait-gate-clock";
960 clock-output-names = "auxclk2_src_gate_ck";
961 clocks = <&dpll_core_m3x2_ck>;
966 auxclk2_src_mux_ck: auxclk2_src_mux_ck@318 {
968 compatible = "ti,composite-mux-clock";
969 clock-output-names = "auxclk2_src_mux_ck";
970 clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
975 auxclk2_src_ck: auxclk2_src_ck {
977 compatible = "ti,composite-clock";
978 clock-output-names = "auxclk2_src_ck";
979 clocks = <&auxclk2_src_gate_ck>, <&auxclk2_src_mux_ck>;
982 auxclk2_ck: auxclk2_ck@318 {
984 compatible = "ti,divider-clock";
985 clock-output-names = "auxclk2_ck";
986 clocks = <&auxclk2_src_ck>;
992 auxclk3_src_gate_ck: auxclk3_src_gate_ck@31c {
994 compatible = "ti,composite-no-wait-gate-clock";
995 clock-output-names = "auxclk3_src_gate_ck";
996 clocks = <&dpll_core_m3x2_ck>;
1001 auxclk3_src_mux_ck: auxclk3_src_mux_ck@31c {
1003 compatible = "ti,composite-mux-clock";
1004 clock-output-names = "auxclk3_src_mux_ck";
1005 clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
1010 auxclk3_src_ck: auxclk3_src_ck {
1012 compatible = "ti,composite-clock";
1013 clock-output-names = "auxclk3_src_ck";
1014 clocks = <&auxclk3_src_gate_ck>, <&auxclk3_src_mux_ck>;
1017 auxclk3_ck: auxclk3_ck@31c {
1019 compatible = "ti,divider-clock";
1020 clock-output-names = "auxclk3_ck";
1021 clocks = <&auxclk3_src_ck>;
1022 ti,bit-shift = <16>;
1027 auxclk4_src_gate_ck: auxclk4_src_gate_ck@320 {
1029 compatible = "ti,composite-no-wait-gate-clock";
1030 clock-output-names = "auxclk4_src_gate_ck";
1031 clocks = <&dpll_core_m3x2_ck>;
1036 auxclk4_src_mux_ck: auxclk4_src_mux_ck@320 {
1038 compatible = "ti,composite-mux-clock";
1039 clock-output-names = "auxclk4_src_mux_ck";
1040 clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
1045 auxclk4_src_ck: auxclk4_src_ck {
1047 compatible = "ti,composite-clock";
1048 clock-output-names = "auxclk4_src_ck";
1049 clocks = <&auxclk4_src_gate_ck>, <&auxclk4_src_mux_ck>;
1052 auxclk4_ck: auxclk4_ck@320 {
1054 compatible = "ti,divider-clock";
1055 clock-output-names = "auxclk4_ck";
1056 clocks = <&auxclk4_src_ck>;
1057 ti,bit-shift = <16>;
1062 auxclkreq0_ck: auxclkreq0_ck@210 {
1064 compatible = "ti,mux-clock";
1065 clock-output-names = "auxclkreq0_ck";
1066 clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
1071 auxclkreq1_ck: auxclkreq1_ck@214 {
1073 compatible = "ti,mux-clock";
1074 clock-output-names = "auxclkreq1_ck";
1075 clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
1080 auxclkreq2_ck: auxclkreq2_ck@218 {
1082 compatible = "ti,mux-clock";
1083 clock-output-names = "auxclkreq2_ck";
1084 clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
1089 auxclkreq3_ck: auxclkreq3_ck@21c {
1091 compatible = "ti,mux-clock";
1092 clock-output-names = "auxclkreq3_ck";
1093 clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
1100 mpu_cm: mpu_cm@300 {
1101 compatible = "ti,omap4-cm";
1102 clock-output-names = "mpu_cm";
1103 reg = <0x300 0x100>;
1104 #address-cells = <1>;
1106 ranges = <0 0x300 0x100>;
1108 mpu_clkctrl: clk@20 {
1109 compatible = "ti,clkctrl";
1110 clock-output-names = "mpu_clkctrl";
1116 dsp_cm: dsp_cm@400 {
1117 compatible = "ti,omap4-cm";
1118 clock-output-names = "dsp_cm";
1119 reg = <0x400 0x100>;
1120 #address-cells = <1>;
1122 ranges = <0 0x400 0x100>;
1124 dsp_clkctrl: clk@20 {
1125 compatible = "ti,clkctrl";
1126 clock-output-names = "dsp_clkctrl";
1132 abe_cm: abe_cm@500 {
1133 compatible = "ti,omap4-cm";
1134 clock-output-names = "abe_cm";
1135 reg = <0x500 0x100>;
1136 #address-cells = <1>;
1138 ranges = <0 0x500 0x100>;
1140 abe_clkctrl: clk@20 {
1141 compatible = "ti,clkctrl";
1142 clock-output-names = "abe_clkctrl";
1151 l3main1_cm: l3main1_cm@700 {
1152 compatible = "ti,omap4-cm";
1153 clock-output-names = "l3main1_cm";
1154 reg = <0x700 0x100>;
1155 #address-cells = <1>;
1157 ranges = <0 0x700 0x100>;
1159 l3main1_clkctrl: clk@20 {
1160 compatible = "ti,clkctrl";
1161 clock-output-names = "l3main1_clkctrl";
1167 l3main2_cm: l3main2_cm@800 {
1168 compatible = "ti,omap4-cm";
1169 clock-output-names = "l3main2_cm";
1170 reg = <0x800 0x100>;
1171 #address-cells = <1>;
1173 ranges = <0 0x800 0x100>;
1175 l3main2_clkctrl: clk@20 {
1176 compatible = "ti,clkctrl";
1177 clock-output-names = "l3main2_clkctrl";
1183 ipu_cm: ipu_cm@900 {
1184 compatible = "ti,omap4-cm";
1185 clock-output-names = "ipu_cm";
1186 reg = <0x900 0x100>;
1187 #address-cells = <1>;
1189 ranges = <0 0x900 0x100>;
1191 ipu_clkctrl: clk@20 {
1192 compatible = "ti,clkctrl";
1193 clock-output-names = "ipu_clkctrl";
1199 dma_cm: dma_cm@a00 {
1200 compatible = "ti,omap4-cm";
1201 clock-output-names = "dma_cm";
1202 reg = <0xa00 0x100>;
1203 #address-cells = <1>;
1205 ranges = <0 0xa00 0x100>;
1207 dma_clkctrl: clk@20 {
1208 compatible = "ti,clkctrl";
1209 clock-output-names = "dma_clkctrl";
1215 emif_cm: emif_cm@b00 {
1216 compatible = "ti,omap4-cm";
1217 clock-output-names = "emif_cm";
1218 reg = <0xb00 0x100>;
1219 #address-cells = <1>;
1221 ranges = <0 0xb00 0x100>;
1223 emif_clkctrl: clk@20 {
1224 compatible = "ti,clkctrl";
1225 clock-output-names = "emif_clkctrl";
1231 l4cfg_cm: l4cfg_cm@d00 {
1232 compatible = "ti,omap4-cm";
1233 clock-output-names = "l4cfg_cm";
1234 reg = <0xd00 0x100>;
1235 #address-cells = <1>;
1237 ranges = <0 0xd00 0x100>;
1239 l4cfg_clkctrl: clk@20 {
1240 compatible = "ti,clkctrl";
1241 clock-output-names = "l4cfg_clkctrl";
1247 l3instr_cm: l3instr_cm@e00 {
1248 compatible = "ti,omap4-cm";
1249 clock-output-names = "l3instr_cm";
1250 reg = <0xe00 0x100>;
1251 #address-cells = <1>;
1253 ranges = <0 0xe00 0x100>;
1255 l3instr_clkctrl: clk@20 {
1256 compatible = "ti,clkctrl";
1257 clock-output-names = "l3instr_clkctrl";
1263 l4per_cm: clock@1000 {
1264 compatible = "ti,omap4-cm";
1265 clock-output-names = "l4per_cm";
1266 reg = <0x1000 0x200>;
1267 #address-cells = <1>;
1269 ranges = <0 0x1000 0x200>;
1271 l4per_clkctrl: clock@20 {
1272 compatible = "ti,clkctrl";
1273 clock-output-names = "l4per_clkctrl";
1278 l4sec_clkctrl: clock@1a0 {
1279 compatible = "ti,clkctrl";
1280 clock-output-names = "l4sec_clkctrl";
1286 dss_cm: dss_cm@1400 {
1287 compatible = "ti,omap4-cm";
1288 clock-output-names = "dss_cm";
1289 reg = <0x1400 0x100>;
1290 #address-cells = <1>;
1292 ranges = <0 0x1400 0x100>;
1294 dss_clkctrl: clk@20 {
1295 compatible = "ti,clkctrl";
1296 clock-output-names = "dss_clkctrl";
1302 gpu_cm: gpu_cm@1500 {
1303 compatible = "ti,omap4-cm";
1304 clock-output-names = "gpu_cm";
1305 reg = <0x1500 0x100>;
1306 #address-cells = <1>;
1308 ranges = <0 0x1500 0x100>;
1310 gpu_clkctrl: clk@20 {
1311 compatible = "ti,clkctrl";
1312 clock-output-names = "gpu_clkctrl";
1318 l3init_cm: l3init_cm@1600 {
1319 compatible = "ti,omap4-cm";
1320 clock-output-names = "l3init_cm";
1321 reg = <0x1600 0x100>;
1322 #address-cells = <1>;
1324 ranges = <0 0x1600 0x100>;
1326 l3init_clkctrl: clk@20 {
1327 compatible = "ti,clkctrl";
1328 clock-output-names = "l3init_clkctrl";
1336 wkupaon_cm: wkupaon_cm@1900 {
1337 compatible = "ti,omap4-cm";
1338 clock-output-names = "wkupaon_cm";
1339 reg = <0x1900 0x100>;
1340 #address-cells = <1>;
1342 ranges = <0 0x1900 0x100>;
1344 wkupaon_clkctrl: clk@20 {
1345 compatible = "ti,clkctrl";
1346 clock-output-names = "wkupaon_clkctrl";
1353 &scm_wkup_pad_conf_clocks {
1354 fref_xtal_ck: fref_xtal_ck {
1356 compatible = "ti,gate-clock";
1357 clock-output-names = "fref_xtal_ck";
1358 clocks = <&sys_clkin>;
1359 ti,bit-shift = <28>;