1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
5 * Based on "omap4.dtsi"
8 #include <dt-bindings/bus/ti-sysc.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/pinctrl/omap.h>
12 #include <dt-bindings/clock/omap5.h>
18 compatible = "ti,omap5";
19 interrupt-parent = <&wakeupgen>;
47 compatible = "arm,cortex-a15";
56 clocks = <&dpll_mpu_ck>;
59 clock-latency = <300000>; /* From omap-cpufreq driver */
62 #cooling-cells = <2>; /* min followed by max */
66 compatible = "arm,cortex-a15";
75 clocks = <&dpll_mpu_ck>;
78 clock-latency = <300000>; /* From omap-cpufreq driver */
81 #cooling-cells = <2>; /* min followed by max */
86 #include "omap4-cpu-thermal.dtsi"
87 #include "omap5-gpu-thermal.dtsi"
88 #include "omap5-core-thermal.dtsi"
92 compatible = "arm,armv7-timer";
93 /* PPI secure/nonsecure IRQ */
94 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
95 <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
96 <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
97 <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>;
98 interrupt-parent = <&gic>;
102 compatible = "arm,cortex-a15-pmu";
103 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
104 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
107 gic: interrupt-controller@48211000 {
108 compatible = "arm,cortex-a15-gic";
109 interrupt-controller;
110 #interrupt-cells = <3>;
111 reg = <0 0x48211000 0 0x1000>,
112 <0 0x48212000 0 0x2000>,
113 <0 0x48214000 0 0x2000>,
114 <0 0x48216000 0 0x2000>;
115 interrupt-parent = <&gic>;
118 wakeupgen: interrupt-controller@48281000 {
119 compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
120 interrupt-controller;
121 #interrupt-cells = <3>;
122 reg = <0 0x48281000 0 0x1000>;
123 interrupt-parent = <&gic>;
127 * The soc node represents the soc top level view. It is used for IPs
128 * that are not memory mapped in the MPU view or for the MPU itself.
131 compatible = "ti,omap-infra";
133 compatible = "ti,omap4-mpu";
140 * XXX: Use a flat representation of the OMAP3 interconnect.
141 * The real OMAP interconnect network is quite complex.
142 * Since it will not bring real advantage to represent that in DT for
143 * the moment, just use a fake OCP bus entry to represent the whole bus
147 compatible = "ti,omap5-l3-noc", "simple-bus";
148 #address-cells = <1>;
150 ranges = <0 0 0 0xc0000000>;
151 dma-ranges = <0x80000000 0x0 0x80000000 0x80000000>;
152 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
153 reg = <0 0x44000000 0 0x2000>,
154 <0 0x44800000 0 0x3000>,
155 <0 0x45000000 0 0x4000>;
156 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
157 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
159 l4_wkup: interconnect@4ae00000 {
162 l4_cfg: interconnect@4a000000 {
165 l4_per: interconnect@48000000 {
168 l4_abe: interconnect@40100000 {
171 ocmcram: ocmcram@40300000 {
172 compatible = "mmio-sram";
173 reg = <0x40300000 0x20000>; /* 128k */
176 gpmc: gpmc@50000000 {
177 compatible = "ti,omap4430-gpmc";
178 reg = <0x50000000 0x1000>;
179 #address-cells = <2>;
181 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
185 gpmc,num-waitpins = <4>;
187 clocks = <&l3_iclk_div>;
189 interrupt-controller;
190 #interrupt-cells = <2>;
195 mmu_dsp: mmu@4a066000 {
196 compatible = "ti,omap4-iommu";
197 reg = <0x4a066000 0x100>;
198 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
199 ti,hwmods = "mmu_dsp";
203 mmu_ipu: mmu@55082000 {
204 compatible = "ti,omap4-iommu";
205 reg = <0x55082000 0x100>;
206 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
207 ti,hwmods = "mmu_ipu";
209 ti,iommu-bus-err-back;
213 compatible = "ti,omap5-dmm";
214 reg = <0x4e000000 0x800>;
215 interrupts = <0 113 0x4>;
219 emif1: emif@4c000000 {
220 compatible = "ti,emif-4d5";
223 phy-type = <2>; /* DDR PHY type: Intelli PHY */
224 reg = <0x4c000000 0x400>;
225 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
226 hw-caps-read-idle-ctrl;
227 hw-caps-ll-interface;
231 emif2: emif@4d000000 {
232 compatible = "ti,emif-4d5";
235 phy-type = <2>; /* DDR PHY type: Intelli PHY */
236 reg = <0x4d000000 0x400>;
237 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
238 hw-caps-read-idle-ctrl;
239 hw-caps-ll-interface;
243 bandgap: bandgap@4a0021e0 {
244 reg = <0x4a0021e0 0xc
248 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
249 compatible = "ti,omap5430-bandgap";
251 #thermal-sensor-cells = <1>;
255 sata: sata@4a141100 {
256 compatible = "snps,dwc-ahci";
257 reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
258 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
260 phy-names = "sata-phy";
261 clocks = <&l3init_clkctrl OMAP5_SATA_CLKCTRL 8>;
263 ports-implemented = <0x1>;
266 target-module@56000000 {
267 compatible = "ti,sysc-omap4", "ti,sysc";
268 reg = <0x5600fe00 0x4>,
270 reg-names = "rev", "sysc";
271 ti,sysc-midle = <SYSC_IDLE_FORCE>,
274 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
277 clocks = <&gpu_clkctrl OMAP5_GPU_CLKCTRL 0>;
279 #address-cells = <1>;
281 ranges = <0 0x56000000 0x2000000>;
284 * Closed source PowerVR driver, no child device
285 * binding or driver in mainline
290 compatible = "ti,omap5-dss";
291 reg = <0x58000000 0x80>;
293 ti,hwmods = "dss_core";
294 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
296 #address-cells = <1>;
301 compatible = "ti,omap5-dispc";
302 reg = <0x58001000 0x1000>;
303 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
304 ti,hwmods = "dss_dispc";
305 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
309 rfbi: encoder@58002000 {
310 compatible = "ti,omap5-rfbi";
311 reg = <0x58002000 0x100>;
313 ti,hwmods = "dss_rfbi";
314 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>, <&l3_iclk_div>;
315 clock-names = "fck", "ick";
318 dsi1: encoder@58004000 {
319 compatible = "ti,omap5-dsi";
320 reg = <0x58004000 0x200>,
323 reg-names = "proto", "phy", "pll";
324 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
326 ti,hwmods = "dss_dsi1";
327 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>,
328 <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
329 clock-names = "fck", "sys_clk";
332 dsi2: encoder@58005000 {
333 compatible = "ti,omap5-dsi";
334 reg = <0x58009000 0x200>,
337 reg-names = "proto", "phy", "pll";
338 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
340 ti,hwmods = "dss_dsi2";
341 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>,
342 <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
343 clock-names = "fck", "sys_clk";
346 hdmi: encoder@58060000 {
347 compatible = "ti,omap5-hdmi";
348 reg = <0x58040000 0x200>,
351 <0x58060000 0x19000>;
352 reg-names = "wp", "pll", "phy", "core";
353 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
355 ti,hwmods = "dss_hdmi";
356 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>,
357 <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
358 clock-names = "fck", "sys_clk";
360 dma-names = "audio_tx";
364 abb_mpu: regulator-abb-mpu {
365 compatible = "ti,abb-v2";
366 regulator-name = "abb_mpu";
367 #address-cells = <0>;
369 clocks = <&sys_clkin>;
370 ti,settling-time = <50>;
371 ti,clock-cycles = <16>;
373 reg = <0x4ae07cdc 0x8>, <0x4ae06014 0x4>,
374 <0x4a0021c4 0x8>, <0x4ae0c318 0x4>;
375 reg-names = "base-address", "int-address",
376 "efuse-address", "ldo-address";
377 ti,tranxdone-status-mask = <0x80>;
378 /* LDOVBBMPU_MUX_CTRL */
379 ti,ldovbb-override-mask = <0x400>;
380 /* LDOVBBMPU_VSET_OUT */
381 ti,ldovbb-vset-mask = <0x1F>;
384 * NOTE: only FBB mode used but actual vset will
385 * determine final biasing
388 /*uV ABB efuse rbb_m fbb_m vset_m*/
389 1060000 0 0x0 0 0x02000000 0x01F00000
390 1250000 0 0x4 0 0x02000000 0x01F00000
394 abb_mm: regulator-abb-mm {
395 compatible = "ti,abb-v2";
396 regulator-name = "abb_mm";
397 #address-cells = <0>;
399 clocks = <&sys_clkin>;
400 ti,settling-time = <50>;
401 ti,clock-cycles = <16>;
403 reg = <0x4ae07ce4 0x8>, <0x4ae06010 0x4>,
404 <0x4a0021a4 0x8>, <0x4ae0c314 0x4>;
405 reg-names = "base-address", "int-address",
406 "efuse-address", "ldo-address";
407 ti,tranxdone-status-mask = <0x80000000>;
408 /* LDOVBBMM_MUX_CTRL */
409 ti,ldovbb-override-mask = <0x400>;
410 /* LDOVBBMM_VSET_OUT */
411 ti,ldovbb-vset-mask = <0x1F>;
414 * NOTE: only FBB mode used but actual vset will
415 * determine final biasing
418 /*uV ABB efuse rbb_m fbb_m vset_m*/
419 1025000 0 0x0 0 0x02000000 0x01F00000
420 1120000 0 0x4 0 0x02000000 0x01F00000
427 polling-delay = <500>; /* milliseconds */
428 coefficients = <65 (-1791)>;
431 #include "omap5-l4.dtsi"
432 #include "omap54xx-clocks.dtsi"
435 coefficients = <117 (-2992)>;
439 coefficients = <0 2000>;
442 #include "omap5-l4-abe.dtsi"
443 #include "omap54xx-clocks.dtsi"