arch/arm/boot/dts/omap5.dtsi

   1 /*
   2  * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  * Based on "omap4.dtsi"
   8  */
   9
  10 #include <dt-bindings/gpio/gpio.h>
  11 #include <dt-bindings/interrupt-controller/arm-gic.h>
  12 #include <dt-bindings/pinctrl/omap.h>
  13 #include <dt-bindings/clock/omap5.h>
  14
  15 / {
  16         #address-cells = <2>;
  17         #size-cells = <2>;
  18
  19         compatible = "ti,omap5";
  20         interrupt-parent = <&wakeupgen>;
  21         chosen { };
  22
  23         aliases {
  24                 i2c0 = &i2c1;
  25                 i2c1 = &i2c2;
  26                 i2c2 = &i2c3;
  27                 i2c3 = &i2c4;
  28                 i2c4 = &i2c5;
  29                 mmc0 = &mmc1;
  30                 mmc1 = &mmc2;
  31                 mmc2 = &mmc3;
  32                 mmc3 = &mmc4;
  33                 mmc4 = &mmc5;
  34                 serial0 = &uart1;
  35                 serial1 = &uart2;
  36                 serial2 = &uart3;
  37                 serial3 = &uart4;
  38                 serial4 = &uart5;
  39                 serial5 = &uart6;
  40         };
  41
  42         cpus {
  43                 #address-cells = <1>;
  44                 #size-cells = <0>;
  45
  46                 cpu0: cpu@0 {
  47                         device_type = "cpu";
  48                         compatible = "arm,cortex-a15";
  49                         reg = <0x0>;
  50
  51                         operating-points = <
  52                                 /* kHz    uV */
  53                                 1000000 1060000
  54                                 1500000 1250000
  55                         >;
  56
  57                         clocks = <&dpll_mpu_ck>;
  58                         clock-names = "cpu";
  59
  60                         clock-latency = <300000>; /* From omap-cpufreq driver */
  61
  62                         /* cooling options */
  63                         #cooling-cells = <2>; /* min followed by max */
  64                 };
  65                 cpu@1 {
  66                         device_type = "cpu";
  67                         compatible = "arm,cortex-a15";
  68                         reg = <0x1>;
  69
  70                         operating-points = <
  71                                 /* kHz    uV */
  72                                 1000000 1060000
  73                                 1500000 1250000
  74                         >;
  75
  76                         clocks = <&dpll_mpu_ck>;
  77                         clock-names = "cpu";
  78
  79                         clock-latency = <300000>; /* From omap-cpufreq driver */
  80
  81                         /* cooling options */
  82                         #cooling-cells = <2>; /* min followed by max */
  83                 };
  84         };
  85
  86         thermal-zones {
  87                 #include "omap4-cpu-thermal.dtsi"
  88                 #include "omap5-gpu-thermal.dtsi"
  89                 #include "omap5-core-thermal.dtsi"
  90         };
  91
  92         timer {
  93                 compatible = "arm,armv7-timer";
  94                 /* PPI secure/nonsecure IRQ */
  95                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
  96                              <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
  97                              <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
  98                              <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>;
  99                 interrupt-parent = <&gic>;
 100         };
 101
 102         pmu {
 103                 compatible = "arm,cortex-a15-pmu";
 104                 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
 105                              <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
 106         };
 107
 108         gic: interrupt-controller@48211000 {
 109                 compatible = "arm,cortex-a15-gic";
 110                 interrupt-controller;
 111                 #interrupt-cells = <3>;
 112                 reg = <0 0x48211000 0 0x1000>,
 113                       <0 0x48212000 0 0x2000>,
 114                       <0 0x48214000 0 0x2000>,
 115                       <0 0x48216000 0 0x2000>;
 116                 interrupt-parent = <&gic>;
 117         };
 118
 119         wakeupgen: interrupt-controller@48281000 {
 120                 compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
 121                 interrupt-controller;
 122                 #interrupt-cells = <3>;
 123                 reg = <0 0x48281000 0 0x1000>;
 124                 interrupt-parent = <&gic>;
 125         };
 126
 127         /*
 128          * The soc node represents the soc top level view. It is used for IPs
 129          * that are not memory mapped in the MPU view or for the MPU itself.
 130          */
 131         soc {
 132                 compatible = "ti,omap-infra";
 133                 mpu {
 134                         compatible = "ti,omap4-mpu";
 135                         ti,hwmods = "mpu";
 136                         sram = <&ocmcram>;
 137                 };
 138         };
 139
 140         /*
 141          * XXX: Use a flat representation of the OMAP3 interconnect.
 142          * The real OMAP interconnect network is quite complex.
 143          * Since it will not bring real advantage to represent that in DT for
 144          * the moment, just use a fake OCP bus entry to represent the whole bus
 145          * hierarchy.
 146          */
 147         ocp {
 148                 compatible = "ti,omap5-l3-noc", "simple-bus";
 149                 #address-cells = <1>;
 150                 #size-cells = <1>;
 151                 ranges = <0 0 0 0xc0000000>;
 152                 dma-ranges = <0x80000000 0x0 0x80000000 0x80000000>;
 153                 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
 154                 reg = <0 0x44000000 0 0x2000>,
 155                       <0 0x44800000 0 0x3000>,
 156                       <0 0x45000000 0 0x4000>;
 157                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
 158                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 159
 160                 l4_cfg: l4@4a000000 {
 161                         compatible = "ti,omap5-l4-cfg", "simple-bus";
 162                         #address-cells = <1>;
 163                         #size-cells = <1>;
 164                         ranges = <0 0x4a000000 0x22a000>;
 165
 166                         scm_core: scm@2000 {
 167                                 compatible = "ti,omap5-scm-core", "simple-bus";
 168                                 reg = <0x2000 0x1000>;
 169                                 #address-cells = <1>;
 170                                 #size-cells = <1>;
 171                                 ranges = <0 0x2000 0x800>;
 172
 173                                 scm_conf: scm_conf@0 {
 174                                         compatible = "syscon";
 175                                         reg = <0x0 0x800>;
 176                                         #address-cells = <1>;
 177                                         #size-cells = <1>;
 178                                 };
 179                         };
 180
 181                         scm_padconf_core: scm@2800 {
 182                                 compatible = "ti,omap5-scm-padconf-core",
 183                                              "simple-bus";
 184                                 #address-cells = <1>;
 185                                 #size-cells = <1>;
 186                                 ranges = <0 0x2800 0x800>;
 187
 188                                 omap5_pmx_core: pinmux@40 {
 189                                         compatible = "ti,omap5-padconf",
 190                                                      "pinctrl-single";
 191                                         reg = <0x40 0x01b6>;
 192                                         #address-cells = <1>;
 193                                         #size-cells = <0>;
 194                                         #pinctrl-cells = <1>;
 195                                         #interrupt-cells = <1>;
 196                                         interrupt-controller;
 197                                         pinctrl-single,register-width = <16>;
 198                                         pinctrl-single,function-mask = <0x7fff>;
 199                                 };
 200
 201                                 omap5_padconf_global: omap5_padconf_global@5a0 {
 202                                         compatible = "syscon",
 203                                                      "simple-bus";
 204                                         reg = <0x5a0 0xec>;
 205                                         #address-cells = <1>;
 206                                         #size-cells = <1>;
 207                                         ranges = <0 0x5a0 0xec>;
 208
 209                                         pbias_regulator: pbias_regulator@60 {
 210                                                 compatible = "ti,pbias-omap5", "ti,pbias-omap";
 211                                                 reg = <0x60 0x4>;
 212                                                 syscon = <&omap5_padconf_global>;
 213                                                 pbias_mmc_reg: pbias_mmc_omap5 {
 214                                                         regulator-name = "pbias_mmc_omap5";
 215                                                         regulator-min-microvolt = <1800000>;
 216                                                         regulator-max-microvolt = <3300000>;
 217                                                 };
 218                                         };
 219                                 };
 220                         };
 221
 222                         cm_core_aon: cm_core_aon@4000 {
 223                                 compatible = "ti,omap5-cm-core-aon",
 224                                              "simple-bus";
 225                                 reg = <0x4000 0x2000>;
 226                                 #address-cells = <1>;
 227                                 #size-cells = <1>;
 228                                 ranges = <0 0x4000 0x2000>;
 229
 230                                 cm_core_aon_clocks: clocks {
 231                                         #address-cells = <1>;
 232                                         #size-cells = <0>;
 233                                 };
 234
 235                                 cm_core_aon_clockdomains: clockdomains {
 236                                 };
 237                         };
 238
 239                         cm_core: cm_core@8000 {
 240                                 compatible = "ti,omap5-cm-core", "simple-bus";
 241                                 reg = <0x8000 0x3000>;
 242                                 #address-cells = <1>;
 243                                 #size-cells = <1>;
 244                                 ranges = <0 0x8000 0x3000>;
 245
 246                                 cm_core_clocks: clocks {
 247                                         #address-cells = <1>;
 248                                         #size-cells = <0>;
 249                                 };
 250
 251                                 cm_core_clockdomains: clockdomains {
 252                                 };
 253                         };
 254                 };
 255
 256                 l4_wkup: l4@4ae00000 {
 257                         compatible = "ti,omap5-l4-wkup", "simple-bus";
 258                         #address-cells = <1>;
 259                         #size-cells = <1>;
 260                         ranges = <0 0x4ae00000 0x2b000>;
 261
 262                         counter32k: counter@4000 {
 263                                 compatible = "ti,omap-counter32k";
 264                                 reg = <0x4000 0x40>;
 265                                 ti,hwmods = "counter_32k";
 266                         };
 267
 268                         prm: prm@6000 {
 269                                 compatible = "ti,omap5-prm", "simple-bus";
 270                                 reg = <0x6000 0x3000>;
 271                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 272                                 #address-cells = <1>;
 273                                 #size-cells = <1>;
 274                                 ranges = <0 0x6000 0x3000>;
 275
 276                                 prm_clocks: clocks {
 277                                         #address-cells = <1>;
 278                                         #size-cells = <0>;
 279                                 };
 280
 281                                 prm_clockdomains: clockdomains {
 282                                 };
 283                         };
 284
 285                         scrm: scrm@a000 {
 286                                 compatible = "ti,omap5-scrm";
 287                                 reg = <0xa000 0x2000>;
 288
 289                                 scrm_clocks: clocks {
 290                                         #address-cells = <1>;
 291                                         #size-cells = <0>;
 292                                 };
 293
 294                                 scrm_clockdomains: clockdomains {
 295                                 };
 296                         };
 297
 298                         omap5_pmx_wkup: pinmux@c840 {
 299                                 compatible = "ti,omap5-padconf",
 300                                              "pinctrl-single";
 301                                 reg = <0xc840 0x003c>;
 302                                 #address-cells = <1>;
 303                                 #size-cells = <0>;
 304                                 #pinctrl-cells = <1>;
 305                                 #interrupt-cells = <1>;
 306                                 interrupt-controller;
 307                                 pinctrl-single,register-width = <16>;
 308                                 pinctrl-single,function-mask = <0x7fff>;
 309                         };
 310
 311                         omap5_scm_wkup_pad_conf: omap5_scm_wkup_pad_conf@cda0 {
 312                                 compatible = "ti,omap5-scm-wkup-pad-conf",
 313                                              "simple-bus";
 314                                 reg = <0xcda0 0x60>;
 315                                 #address-cells = <1>;
 316                                 #size-cells = <1>;
 317                                 ranges = <0 0xcda0 0x60>;
 318
 319                                 scm_wkup_pad_conf: scm_conf@0 {
 320                                         compatible = "syscon", "simple-bus";
 321                                         reg = <0x0 0x60>;
 322                                         #address-cells = <1>;
 323                                         #size-cells = <1>;
 324                                         ranges = <0 0x0 0x60>;
 325
 326                                         scm_wkup_pad_conf_clocks: clocks@0 {
 327                                                 #address-cells = <1>;
 328                                                 #size-cells = <0>;
 329                                         };
 330                                 };
 331                         };
 332                 };
 333
 334                 ocmcram: ocmcram@40300000 {
 335                         compatible = "mmio-sram";
 336                         reg = <0x40300000 0x20000>; /* 128k */
 337                 };
 338
 339                 sdma: dma-controller@4a056000 {
 340                         compatible = "ti,omap4430-sdma";
 341                         reg = <0x4a056000 0x1000>;
 342                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
 343                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 344                                      <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
 345                                      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 346                         #dma-cells = <1>;
 347                         dma-channels = <32>;
 348                         dma-requests = <127>;
 349                         ti,hwmods = "dma_system";
 350                 };
 351
 352                 gpio1: gpio@4ae10000 {
 353                         compatible = "ti,omap4-gpio";
 354                         reg = <0x4ae10000 0x200>;
 355                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 356                         ti,hwmods = "gpio1";
 357                         ti,gpio-always-on;
 358                         gpio-controller;
 359                         #gpio-cells = <2>;
 360                         interrupt-controller;
 361                         #interrupt-cells = <2>;
 362                 };
 363
 364                 gpio2: gpio@48055000 {
 365                         compatible = "ti,omap4-gpio";
 366                         reg = <0x48055000 0x200>;
 367                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 368                         ti,hwmods = "gpio2";
 369                         gpio-controller;
 370                         #gpio-cells = <2>;
 371                         interrupt-controller;
 372                         #interrupt-cells = <2>;
 373                 };
 374
 375                 gpio3: gpio@48057000 {
 376                         compatible = "ti,omap4-gpio";
 377                         reg = <0x48057000 0x200>;
 378                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 379                         ti,hwmods = "gpio3";
 380                         gpio-controller;
 381                         #gpio-cells = <2>;
 382                         interrupt-controller;
 383                         #interrupt-cells = <2>;
 384                 };
 385
 386                 gpio4: gpio@48059000 {
 387                         compatible = "ti,omap4-gpio";
 388                         reg = <0x48059000 0x200>;
 389                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 390                         ti,hwmods = "gpio4";
 391                         gpio-controller;
 392                         #gpio-cells = <2>;
 393                         interrupt-controller;
 394                         #interrupt-cells = <2>;
 395                 };
 396
 397                 gpio5: gpio@4805b000 {
 398                         compatible = "ti,omap4-gpio";
 399                         reg = <0x4805b000 0x200>;
 400                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 401                         ti,hwmods = "gpio5";
 402                         gpio-controller;
 403                         #gpio-cells = <2>;
 404                         interrupt-controller;
 405                         #interrupt-cells = <2>;
 406                 };
 407
 408                 gpio6: gpio@4805d000 {
 409                         compatible = "ti,omap4-gpio";
 410                         reg = <0x4805d000 0x200>;
 411                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 412                         ti,hwmods = "gpio6";
 413                         gpio-controller;
 414                         #gpio-cells = <2>;
 415                         interrupt-controller;
 416                         #interrupt-cells = <2>;
 417                 };
 418
 419                 gpio7: gpio@48051000 {
 420                         compatible = "ti,omap4-gpio";
 421                         reg = <0x48051000 0x200>;
 422                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 423                         ti,hwmods = "gpio7";
 424                         gpio-controller;
 425                         #gpio-cells = <2>;
 426                         interrupt-controller;
 427                         #interrupt-cells = <2>;
 428                 };
 429
 430                 gpio8: gpio@48053000 {
 431                         compatible = "ti,omap4-gpio";
 432                         reg = <0x48053000 0x200>;
 433                         interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 434                         ti,hwmods = "gpio8";
 435                         gpio-controller;
 436                         #gpio-cells = <2>;
 437                         interrupt-controller;
 438                         #interrupt-cells = <2>;
 439                 };
 440
 441                 gpmc: gpmc@50000000 {
 442                         compatible = "ti,omap4430-gpmc";
 443                         reg = <0x50000000 0x1000>;
 444                         #address-cells = <2>;
 445                         #size-cells = <1>;
 446                         interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 447                         dmas = <&sdma 4>;
 448                         dma-names = "rxtx";
 449                         gpmc,num-cs = <8>;
 450                         gpmc,num-waitpins = <4>;
 451                         ti,hwmods = "gpmc";
 452                         clocks = <&l3_iclk_div>;
 453                         clock-names = "fck";
 454                         interrupt-controller;
 455                         #interrupt-cells = <2>;
 456                         gpio-controller;
 457                         #gpio-cells = <2>;
 458                 };
 459
 460                 i2c1: i2c@48070000 {
 461                         compatible = "ti,omap4-i2c";
 462                         reg = <0x48070000 0x100>;
 463                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 464                         #address-cells = <1>;
 465                         #size-cells = <0>;
 466                         ti,hwmods = "i2c1";
 467                 };
 468
 469                 i2c2: i2c@48072000 {
 470                         compatible = "ti,omap4-i2c";
 471                         reg = <0x48072000 0x100>;
 472                         interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 473                         #address-cells = <1>;
 474                         #size-cells = <0>;
 475                         ti,hwmods = "i2c2";
 476                 };
 477
 478                 i2c3: i2c@48060000 {
 479                         compatible = "ti,omap4-i2c";
 480                         reg = <0x48060000 0x100>;
 481                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 482                         #address-cells = <1>;
 483                         #size-cells = <0>;
 484                         ti,hwmods = "i2c3";
 485                 };
 486
 487                 i2c4: i2c@4807a000 {
 488                         compatible = "ti,omap4-i2c";
 489                         reg = <0x4807a000 0x100>;
 490                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 491                         #address-cells = <1>;
 492                         #size-cells = <0>;
 493                         ti,hwmods = "i2c4";
 494                 };
 495
 496                 i2c5: i2c@4807c000 {
 497                         compatible = "ti,omap4-i2c";
 498                         reg = <0x4807c000 0x100>;
 499                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 500                         #address-cells = <1>;
 501                         #size-cells = <0>;
 502                         ti,hwmods = "i2c5";
 503                 };
 504
 505                 hwspinlock: spinlock@4a0f6000 {
 506                         compatible = "ti,omap4-hwspinlock";
 507                         reg = <0x4a0f6000 0x1000>;
 508                         ti,hwmods = "spinlock";
 509                         #hwlock-cells = <1>;
 510                 };
 511
 512                 mcspi1: spi@48098000 {
 513                         compatible = "ti,omap4-mcspi";
 514                         reg = <0x48098000 0x200>;
 515                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 516                         #address-cells = <1>;
 517                         #size-cells = <0>;
 518                         ti,hwmods = "mcspi1";
 519                         ti,spi-num-cs = <4>;
 520                         dmas = <&sdma 35>,
 521                                <&sdma 36>,
 522                                <&sdma 37>,
 523                                <&sdma 38>,
 524                                <&sdma 39>,
 525                                <&sdma 40>,
 526                                <&sdma 41>,
 527                                <&sdma 42>;
 528                         dma-names = "tx0", "rx0", "tx1", "rx1",
 529                                     "tx2", "rx2", "tx3", "rx3";
 530                 };
 531
 532                 mcspi2: spi@4809a000 {
 533                         compatible = "ti,omap4-mcspi";
 534                         reg = <0x4809a000 0x200>;
 535                         interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 536                         #address-cells = <1>;
 537                         #size-cells = <0>;
 538                         ti,hwmods = "mcspi2";
 539                         ti,spi-num-cs = <2>;
 540                         dmas = <&sdma 43>,
 541                                <&sdma 44>,
 542                                <&sdma 45>,
 543                                <&sdma 46>;
 544                         dma-names = "tx0", "rx0", "tx1", "rx1";
 545                 };
 546
 547                 mcspi3: spi@480b8000 {
 548                         compatible = "ti,omap4-mcspi";
 549                         reg = <0x480b8000 0x200>;
 550                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 551                         #address-cells = <1>;
 552                         #size-cells = <0>;
 553                         ti,hwmods = "mcspi3";
 554                         ti,spi-num-cs = <2>;
 555                         dmas = <&sdma 15>, <&sdma 16>;
 556                         dma-names = "tx0", "rx0";
 557                 };
 558
 559                 mcspi4: spi@480ba000 {
 560                         compatible = "ti,omap4-mcspi";
 561                         reg = <0x480ba000 0x200>;
 562                         interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 563                         #address-cells = <1>;
 564                         #size-cells = <0>;
 565                         ti,hwmods = "mcspi4";
 566                         ti,spi-num-cs = <1>;
 567                         dmas = <&sdma 70>, <&sdma 71>;
 568                         dma-names = "tx0", "rx0";
 569                 };
 570
 571                 uart1: serial@4806a000 {
 572                         compatible = "ti,omap4-uart";
 573                         reg = <0x4806a000 0x100>;
 574                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 575                         ti,hwmods = "uart1";
 576                         clock-frequency = <48000000>;
 577                 };
 578
 579                 uart2: serial@4806c000 {
 580                         compatible = "ti,omap4-uart";
 581                         reg = <0x4806c000 0x100>;
 582                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 583                         ti,hwmods = "uart2";
 584                         clock-frequency = <48000000>;
 585                 };
 586
 587                 uart3: serial@48020000 {
 588                         compatible = "ti,omap4-uart";
 589                         reg = <0x48020000 0x100>;
 590                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 591                         ti,hwmods = "uart3";
 592                         clock-frequency = <48000000>;
 593                 };
 594
 595                 uart4: serial@4806e000 {
 596                         compatible = "ti,omap4-uart";
 597                         reg = <0x4806e000 0x100>;
 598                         interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 599                         ti,hwmods = "uart4";
 600                         clock-frequency = <48000000>;
 601                 };
 602
 603                 uart5: serial@48066000 {
 604                         compatible = "ti,omap4-uart";
 605                         reg = <0x48066000 0x100>;
 606                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 607                         ti,hwmods = "uart5";
 608                         clock-frequency = <48000000>;
 609                 };
 610
 611                 uart6: serial@48068000 {
 612                         compatible = "ti,omap4-uart";
 613                         reg = <0x48068000 0x100>;
 614                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 615                         ti,hwmods = "uart6";
 616                         clock-frequency = <48000000>;
 617                 };
 618
 619                 mmc1: mmc@4809c000 {
 620                         compatible = "ti,omap4-hsmmc";
 621                         reg = <0x4809c000 0x400>;
 622                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 623                         ti,hwmods = "mmc1";
 624                         ti,dual-volt;
 625                         ti,needs-special-reset;
 626                         dmas = <&sdma 61>, <&sdma 62>;
 627                         dma-names = "tx", "rx";
 628                         pbias-supply = <&pbias_mmc_reg>;
 629                 };
 630
 631                 mmc2: mmc@480b4000 {
 632                         compatible = "ti,omap4-hsmmc";
 633                         reg = <0x480b4000 0x400>;
 634                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 635                         ti,hwmods = "mmc2";
 636                         ti,needs-special-reset;
 637                         dmas = <&sdma 47>, <&sdma 48>;
 638                         dma-names = "tx", "rx";
 639                 };
 640
 641                 mmc3: mmc@480ad000 {
 642                         compatible = "ti,omap4-hsmmc";
 643                         reg = <0x480ad000 0x400>;
 644                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 645                         ti,hwmods = "mmc3";
 646                         ti,needs-special-reset;
 647                         dmas = <&sdma 77>, <&sdma 78>;
 648                         dma-names = "tx", "rx";
 649                 };
 650
 651                 mmc4: mmc@480d1000 {
 652                         compatible = "ti,omap4-hsmmc";
 653                         reg = <0x480d1000 0x400>;
 654                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 655                         ti,hwmods = "mmc4";
 656                         ti,needs-special-reset;
 657                         dmas = <&sdma 57>, <&sdma 58>;
 658                         dma-names = "tx", "rx";
 659                 };
 660
 661                 mmc5: mmc@480d5000 {
 662                         compatible = "ti,omap4-hsmmc";
 663                         reg = <0x480d5000 0x400>;
 664                         interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 665                         ti,hwmods = "mmc5";
 666                         ti,needs-special-reset;
 667                         dmas = <&sdma 59>, <&sdma 60>;
 668                         dma-names = "tx", "rx";
 669                 };
 670
 671                 mmu_dsp: mmu@4a066000 {
 672                         compatible = "ti,omap4-iommu";
 673                         reg = <0x4a066000 0x100>;
 674                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 675                         ti,hwmods = "mmu_dsp";
 676                         #iommu-cells = <0>;
 677                 };
 678
 679                 mmu_ipu: mmu@55082000 {
 680                         compatible = "ti,omap4-iommu";
 681                         reg = <0x55082000 0x100>;
 682                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 683                         ti,hwmods = "mmu_ipu";
 684                         #iommu-cells = <0>;
 685                         ti,iommu-bus-err-back;
 686                 };
 687
 688                 keypad: keypad@4ae1c000 {
 689                         compatible = "ti,omap4-keypad";
 690                         reg = <0x4ae1c000 0x400>;
 691                         ti,hwmods = "kbd";
 692                 };
 693
 694                 mcpdm: mcpdm@40132000 {
 695                         compatible = "ti,omap4-mcpdm";
 696                         reg = <0x40132000 0x7f>, /* MPU private access */
 697                               <0x49032000 0x7f>; /* L3 Interconnect */
 698                         reg-names = "mpu", "dma";
 699                         interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
 700                         ti,hwmods = "mcpdm";
 701                         dmas = <&sdma 65>,
 702                                <&sdma 66>;
 703                         dma-names = "up_link", "dn_link";
 704                         status = "disabled";
 705                 };
 706
 707                 dmic: dmic@4012e000 {
 708                         compatible = "ti,omap4-dmic";
 709                         reg = <0x4012e000 0x7f>, /* MPU private access */
 710                               <0x4902e000 0x7f>; /* L3 Interconnect */
 711                         reg-names = "mpu", "dma";
 712                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 713                         ti,hwmods = "dmic";
 714                         dmas = <&sdma 67>;
 715                         dma-names = "up_link";
 716                         status = "disabled";
 717                 };
 718
 719                 mcbsp1: mcbsp@40122000 {
 720                         compatible = "ti,omap4-mcbsp";
 721                         reg = <0x40122000 0xff>, /* MPU private access */
 722                               <0x49022000 0xff>; /* L3 Interconnect */
 723                         reg-names = "mpu", "dma";
 724                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 725                         interrupt-names = "common";
 726                         ti,buffer-size = <128>;
 727                         ti,hwmods = "mcbsp1";
 728                         dmas = <&sdma 33>,
 729                                <&sdma 34>;
 730                         dma-names = "tx", "rx";
 731                         status = "disabled";
 732                 };
 733
 734                 mcbsp2: mcbsp@40124000 {
 735                         compatible = "ti,omap4-mcbsp";
 736                         reg = <0x40124000 0xff>, /* MPU private access */
 737                               <0x49024000 0xff>; /* L3 Interconnect */
 738                         reg-names = "mpu", "dma";
 739                         interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 740                         interrupt-names = "common";
 741                         ti,buffer-size = <128>;
 742                         ti,hwmods = "mcbsp2";
 743                         dmas = <&sdma 17>,
 744                                <&sdma 18>;
 745                         dma-names = "tx", "rx";
 746                         status = "disabled";
 747                 };
 748
 749                 mcbsp3: mcbsp@40126000 {
 750                         compatible = "ti,omap4-mcbsp";
 751                         reg = <0x40126000 0xff>, /* MPU private access */
 752                               <0x49026000 0xff>; /* L3 Interconnect */
 753                         reg-names = "mpu", "dma";
 754                         interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 755                         interrupt-names = "common";
 756                         ti,buffer-size = <128>;
 757                         ti,hwmods = "mcbsp3";
 758                         dmas = <&sdma 19>,
 759                                <&sdma 20>;
 760                         dma-names = "tx", "rx";
 761                         status = "disabled";
 762                 };
 763
 764                 mailbox: mailbox@4a0f4000 {
 765                         compatible = "ti,omap4-mailbox";
 766                         reg = <0x4a0f4000 0x200>;
 767                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 768                         ti,hwmods = "mailbox";
 769                         #mbox-cells = <1>;
 770                         ti,mbox-num-users = <3>;
 771                         ti,mbox-num-fifos = <8>;
 772                         mbox_ipu: mbox_ipu {
 773                                 ti,mbox-tx = <0 0 0>;
 774                                 ti,mbox-rx = <1 0 0>;
 775                         };
 776                         mbox_dsp: mbox_dsp {
 777                                 ti,mbox-tx = <3 0 0>;
 778                                 ti,mbox-rx = <2 0 0>;
 779                         };
 780                 };
 781
 782                 timer1: timer@4ae18000 {
 783                         compatible = "ti,omap5430-timer";
 784                         reg = <0x4ae18000 0x80>;
 785                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 786                         ti,hwmods = "timer1";
 787                         ti,timer-alwon;
 788                         clocks = <&wkupaon_clkctrl OMAP5_TIMER1_CLKCTRL 24>;
 789                         clock-names = "fck";
 790                 };
 791
 792                 timer2: timer@48032000 {
 793                         compatible = "ti,omap5430-timer";
 794                         reg = <0x48032000 0x80>;
 795                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 796                         ti,hwmods = "timer2";
 797                 };
 798
 799                 timer3: timer@48034000 {
 800                         compatible = "ti,omap5430-timer";
 801                         reg = <0x48034000 0x80>;
 802                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 803                         ti,hwmods = "timer3";
 804                 };
 805
 806                 timer4: timer@48036000 {
 807                         compatible = "ti,omap5430-timer";
 808                         reg = <0x48036000 0x80>;
 809                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 810                         ti,hwmods = "timer4";
 811                 };
 812
 813                 timer5: timer@40138000 {
 814                         compatible = "ti,omap5430-timer";
 815                         reg = <0x40138000 0x80>,
 816                               <0x49038000 0x80>;
 817                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 818                         ti,hwmods = "timer5";
 819                         ti,timer-dsp;
 820                         ti,timer-pwm;
 821                 };
 822
 823                 timer6: timer@4013a000 {
 824                         compatible = "ti,omap5430-timer";
 825                         reg = <0x4013a000 0x80>,
 826                               <0x4903a000 0x80>;
 827                         interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 828                         ti,hwmods = "timer6";
 829                         ti,timer-dsp;
 830                         ti,timer-pwm;
 831                 };
 832
 833                 timer7: timer@4013c000 {
 834                         compatible = "ti,omap5430-timer";
 835                         reg = <0x4013c000 0x80>,
 836                               <0x4903c000 0x80>;
 837                         interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 838                         ti,hwmods = "timer7";
 839                         ti,timer-dsp;
 840                 };
 841
 842                 timer8: timer@4013e000 {
 843                         compatible = "ti,omap5430-timer";
 844                         reg = <0x4013e000 0x80>,
 845                               <0x4903e000 0x80>;
 846                         interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 847                         ti,hwmods = "timer8";
 848                         ti,timer-dsp;
 849                         ti,timer-pwm;
 850                 };
 851
 852                 timer9: timer@4803e000 {
 853                         compatible = "ti,omap5430-timer";
 854                         reg = <0x4803e000 0x80>;
 855                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 856                         ti,hwmods = "timer9";
 857                         ti,timer-pwm;
 858                 };
 859
 860                 timer10: timer@48086000 {
 861                         compatible = "ti,omap5430-timer";
 862                         reg = <0x48086000 0x80>;
 863                         interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 864                         ti,hwmods = "timer10";
 865                         ti,timer-pwm;
 866                 };
 867
 868                 timer11: timer@48088000 {
 869                         compatible = "ti,omap5430-timer";
 870                         reg = <0x48088000 0x80>;
 871                         interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 872                         ti,hwmods = "timer11";
 873                         ti,timer-pwm;
 874                 };
 875
 876                 wdt2: wdt@4ae14000 {
 877                         compatible = "ti,omap5-wdt", "ti,omap3-wdt";
 878                         reg = <0x4ae14000 0x80>;
 879                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 880                         ti,hwmods = "wd_timer2";
 881                 };
 882
 883                 dmm@4e000000 {
 884                         compatible = "ti,omap5-dmm";
 885                         reg = <0x4e000000 0x800>;
 886                         interrupts = <0 113 0x4>;
 887                         ti,hwmods = "dmm";
 888                 };
 889
 890                 emif1: emif@4c000000 {
 891                         compatible      = "ti,emif-4d5";
 892                         ti,hwmods       = "emif1";
 893                         ti,no-idle-on-init;
 894                         phy-type        = <2>; /* DDR PHY type: Intelli PHY */
 895                         reg = <0x4c000000 0x400>;
 896                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 897                         hw-caps-read-idle-ctrl;
 898                         hw-caps-ll-interface;
 899                         hw-caps-temp-alert;
 900                 };
 901
 902                 emif2: emif@4d000000 {
 903                         compatible      = "ti,emif-4d5";
 904                         ti,hwmods       = "emif2";
 905                         ti,no-idle-on-init;
 906                         phy-type        = <2>; /* DDR PHY type: Intelli PHY */
 907                         reg = <0x4d000000 0x400>;
 908                         interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 909                         hw-caps-read-idle-ctrl;
 910                         hw-caps-ll-interface;
 911                         hw-caps-temp-alert;
 912                 };
 913
 914                 usb3: omap_dwc3@4a020000 {
 915                         compatible = "ti,dwc3";
 916                         ti,hwmods = "usb_otg_ss";
 917                         reg = <0x4a020000 0x10000>;
 918                         interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 919                         #address-cells = <1>;
 920                         #size-cells = <1>;
 921                         utmi-mode = <2>;
 922                         ranges;
 923                         dwc3: dwc3@4a030000 {
 924                                 compatible = "snps,dwc3";
 925                                 reg = <0x4a030000 0x10000>;
 926                                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
 927                                              <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
 928                                              <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 929                                 interrupt-names = "peripheral",
 930                                                   "host",
 931                                                   "otg";
 932                                 phys = <&usb2_phy>, <&usb3_phy>;
 933                                 phy-names = "usb2-phy", "usb3-phy";
 934                                 dr_mode = "peripheral";
 935                         };
 936                 };
 937
 938                 ocp2scp@4a080000 {
 939                         compatible = "ti,omap-ocp2scp";
 940                         #address-cells = <1>;
 941                         #size-cells = <1>;
 942                         reg = <0x4a080000 0x20>;
 943                         ranges;
 944                         ti,hwmods = "ocp2scp1";
 945                         usb2_phy: usb2phy@4a084000 {
 946                                 compatible = "ti,omap-usb2";
 947                                 reg = <0x4a084000 0x7c>;
 948                                 syscon-phy-power = <&scm_conf 0x300>;
 949                                 clocks = <&usb_phy_cm_clk32k>,
 950                                          <&l3init_clkctrl OMAP5_USB_OTG_SS_CLKCTRL 8>;
 951                                 clock-names = "wkupclk", "refclk";
 952                                 #phy-cells = <0>;
 953                         };
 954
 955                         usb3_phy: usb3phy@4a084400 {
 956                                 compatible = "ti,omap-usb3";
 957                                 reg = <0x4a084400 0x80>,
 958                                       <0x4a084800 0x64>,
 959                                       <0x4a084c00 0x40>;
 960                                 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
 961                                 syscon-phy-power = <&scm_conf 0x370>;
 962                                 clocks = <&usb_phy_cm_clk32k>,
 963                                          <&sys_clkin>,
 964                                          <&l3init_clkctrl OMAP5_USB_OTG_SS_CLKCTRL 8>;
 965                                 clock-names =   "wkupclk",
 966                                                 "sysclk",
 967                                                 "refclk";
 968                                 #phy-cells = <0>;
 969                         };
 970                 };
 971
 972                 usbhstll: usbhstll@4a062000 {
 973                         compatible = "ti,usbhs-tll";
 974                         reg = <0x4a062000 0x1000>;
 975                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 976                         ti,hwmods = "usb_tll_hs";
 977                 };
 978
 979                 usbhshost: usbhshost@4a064000 {
 980                         compatible = "ti,usbhs-host";
 981                         reg = <0x4a064000 0x800>;
 982                         ti,hwmods = "usb_host_hs";
 983                         #address-cells = <1>;
 984                         #size-cells = <1>;
 985                         ranges;
 986                         clocks = <&l3init_60m_fclk>,
 987                                  <&xclk60mhsp1_ck>,
 988                                  <&xclk60mhsp2_ck>;
 989                         clock-names = "refclk_60m_int",
 990                                       "refclk_60m_ext_p1",
 991                                       "refclk_60m_ext_p2";
 992
 993                         usbhsohci: ohci@4a064800 {
 994                                 compatible = "ti,ohci-omap3";
 995                                 reg = <0x4a064800 0x400>;
 996                                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 997                                 remote-wakeup-connected;
 998                         };
 999
1000                         usbhsehci: ehci@4a064c00 {
1001                                 compatible = "ti,ehci-omap";
1002                                 reg = <0x4a064c00 0x400>;
1003                                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
1004                         };
1005                 };
1006
1007                 bandgap: bandgap@4a0021e0 {
1008                         reg = <0x4a0021e0 0xc
1009                                0x4a00232c 0xc
1010                                0x4a002380 0x2c
1011                                0x4a0023C0 0x3c>;
1012                         interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
1013                         compatible = "ti,omap5430-bandgap";
1014
1015                         #thermal-sensor-cells = <1>;
1016                 };
1017
1018                 /* OCP2SCP3 */
1019                 ocp2scp@4a090000 {
1020                         compatible = "ti,omap-ocp2scp";
1021                         #address-cells = <1>;
1022                         #size-cells = <1>;
1023                         reg = <0x4a090000 0x20>;
1024                         ranges;
1025                         ti,hwmods = "ocp2scp3";
1026                         sata_phy: phy@4a096000 {
1027                                 compatible = "ti,phy-pipe3-sata";
1028                                 reg = <0x4A096000 0x80>, /* phy_rx */
1029                                       <0x4A096400 0x64>, /* phy_tx */
1030                                       <0x4A096800 0x40>; /* pll_ctrl */
1031                                 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
1032                                 syscon-phy-power = <&scm_conf 0x374>;
1033                                 clocks = <&sys_clkin>,
1034                                          <&l3init_clkctrl OMAP5_SATA_CLKCTRL 8>;
1035                                 clock-names = "sysclk", "refclk";
1036                                 #phy-cells = <0>;
1037                         };
1038                 };
1039
1040                 sata: sata@4a141100 {
1041                         compatible = "snps,dwc-ahci";
1042                         reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
1043                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
1044                         phys = <&sata_phy>;
1045                         phy-names = "sata-phy";
1046                         clocks = <&l3init_clkctrl OMAP5_SATA_CLKCTRL 8>;
1047                         ti,hwmods = "sata";
1048                         ports-implemented = <0x1>;
1049                 };
1050
1051                 dss: dss@58000000 {
1052                         compatible = "ti,omap5-dss";
1053                         reg = <0x58000000 0x80>;
1054                         status = "disabled";
1055                         ti,hwmods = "dss_core";
1056                         clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
1057                         clock-names = "fck";
1058                         #address-cells = <1>;
1059                         #size-cells = <1>;
1060                         ranges;
1061
1062                         dispc@58001000 {
1063                                 compatible = "ti,omap5-dispc";
1064                                 reg = <0x58001000 0x1000>;
1065                                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1066                                 ti,hwmods = "dss_dispc";
1067                                 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
1068                                 clock-names = "fck";
1069                         };
1070
1071                         rfbi: encoder@58002000  {
1072                                 compatible = "ti,omap5-rfbi";
1073                                 reg = <0x58002000 0x100>;
1074                                 status = "disabled";
1075                                 ti,hwmods = "dss_rfbi";
1076                                 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>, <&l3_iclk_div>;
1077                                 clock-names = "fck", "ick";
1078                         };
1079
1080                         dsi1: encoder@58004000 {
1081                                 compatible = "ti,omap5-dsi";
1082                                 reg = <0x58004000 0x200>,
1083                                       <0x58004200 0x40>,
1084                                       <0x58004300 0x40>;
1085                                 reg-names = "proto", "phy", "pll";
1086                                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1087                                 status = "disabled";
1088                                 ti,hwmods = "dss_dsi1";
1089                                 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>,
1090                                          <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
1091                                 clock-names = "fck", "sys_clk";
1092                         };
1093
1094                         dsi2: encoder@58005000 {
1095                                 compatible = "ti,omap5-dsi";
1096                                 reg = <0x58009000 0x200>,
1097                                       <0x58009200 0x40>,
1098                                       <0x58009300 0x40>;
1099                                 reg-names = "proto", "phy", "pll";
1100                                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
1101                                 status = "disabled";
1102                                 ti,hwmods = "dss_dsi2";
1103                                 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>,
1104                                          <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
1105                                 clock-names = "fck", "sys_clk";
1106                         };
1107
1108                         hdmi: encoder@58060000 {
1109                                 compatible = "ti,omap5-hdmi";
1110                                 reg = <0x58040000 0x200>,
1111                                       <0x58040200 0x80>,
1112                                       <0x58040300 0x80>,
1113                                       <0x58060000 0x19000>;
1114                                 reg-names = "wp", "pll", "phy", "core";
1115                                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1116                                 status = "disabled";
1117                                 ti,hwmods = "dss_hdmi";
1118                                 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>,
1119                                          <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
1120                                 clock-names = "fck", "sys_clk";
1121                                 dmas = <&sdma 76>;
1122                                 dma-names = "audio_tx";
1123                         };
1124                 };
1125
1126                 abb_mpu: regulator-abb-mpu {
1127                         compatible = "ti,abb-v2";
1128                         regulator-name = "abb_mpu";
1129                         #address-cells = <0>;
1130                         #size-cells = <0>;
1131                         clocks = <&sys_clkin>;
1132                         ti,settling-time = <50>;
1133                         ti,clock-cycles = <16>;
1134
1135                         reg = <0x4ae07cdc 0x8>, <0x4ae06014 0x4>,
1136                               <0x4a0021c4 0x8>, <0x4ae0c318 0x4>;
1137                         reg-names = "base-address", "int-address",
1138                                     "efuse-address", "ldo-address";
1139                         ti,tranxdone-status-mask = <0x80>;
1140                         /* LDOVBBMPU_MUX_CTRL */
1141                         ti,ldovbb-override-mask = <0x400>;
1142                         /* LDOVBBMPU_VSET_OUT */
1143                         ti,ldovbb-vset-mask = <0x1F>;
1144
1145                         /*
1146                          * NOTE: only FBB mode used but actual vset will
1147                          * determine final biasing
1148                          */
1149                         ti,abb_info = <
1150                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
1151                         1060000         0       0x0     0 0x02000000 0x01F00000
1152                         1250000         0       0x4     0 0x02000000 0x01F00000
1153                         >;
1154                 };
1155
1156                 abb_mm: regulator-abb-mm {
1157                         compatible = "ti,abb-v2";
1158                         regulator-name = "abb_mm";
1159                         #address-cells = <0>;
1160                         #size-cells = <0>;
1161                         clocks = <&sys_clkin>;
1162                         ti,settling-time = <50>;
1163                         ti,clock-cycles = <16>;
1164
1165                         reg = <0x4ae07ce4 0x8>, <0x4ae06010 0x4>,
1166                               <0x4a0021a4 0x8>, <0x4ae0c314 0x4>;
1167                         reg-names = "base-address", "int-address",
1168                                     "efuse-address", "ldo-address";
1169                         ti,tranxdone-status-mask = <0x80000000>;
1170                         /* LDOVBBMM_MUX_CTRL */
1171                         ti,ldovbb-override-mask = <0x400>;
1172                         /* LDOVBBMM_VSET_OUT */
1173                         ti,ldovbb-vset-mask = <0x1F>;
1174
1175                         /*
1176                          * NOTE: only FBB mode used but actual vset will
1177                          * determine final biasing
1178                          */
1179                         ti,abb_info = <
1180                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
1181                         1025000         0       0x0     0 0x02000000 0x01F00000
1182                         1120000         0       0x4     0 0x02000000 0x01F00000
1183                         >;
1184                 };
1185         };
1186 };
1187
1188 &cpu_thermal {
1189         polling-delay = <500>; /* milliseconds */
1190         coefficients = <65 (-1791)>;
1191 };
1192
1193 #include "omap54xx-clocks.dtsi"
1194
1195 &gpu_thermal {
1196         coefficients = <117 (-2992)>;
1197 };
1198
1199 &core_thermal {
1200         coefficients = <0 2000>;
1201 };