2 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 * Based on "omap4.dtsi"
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/pinctrl/omap.h>
18 compatible = "ti,omap5";
19 interrupt-parent = <&wakeupgen>;
47 compatible = "arm,cortex-a15";
56 clocks = <&dpll_mpu_ck>;
59 clock-latency = <300000>; /* From omap-cpufreq driver */
62 cooling-min-level = <0>;
63 cooling-max-level = <2>;
64 #cooling-cells = <2>; /* min followed by max */
68 compatible = "arm,cortex-a15";
74 #include "omap4-cpu-thermal.dtsi"
75 #include "omap5-gpu-thermal.dtsi"
76 #include "omap5-core-thermal.dtsi"
80 compatible = "arm,armv7-timer";
81 /* PPI secure/nonsecure IRQ */
82 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
83 <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
84 <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
85 <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>;
86 interrupt-parent = <&gic>;
90 compatible = "arm,cortex-a15-pmu";
91 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
92 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
95 gic: interrupt-controller@48211000 {
96 compatible = "arm,cortex-a15-gic";
98 #interrupt-cells = <3>;
99 reg = <0 0x48211000 0 0x1000>,
100 <0 0x48212000 0 0x2000>,
101 <0 0x48214000 0 0x2000>,
102 <0 0x48216000 0 0x2000>;
103 interrupt-parent = <&gic>;
106 wakeupgen: interrupt-controller@48281000 {
107 compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
108 interrupt-controller;
109 #interrupt-cells = <3>;
110 reg = <0 0x48281000 0 0x1000>;
111 interrupt-parent = <&gic>;
115 * The soc node represents the soc top level view. It is used for IPs
116 * that are not memory mapped in the MPU view or for the MPU itself.
119 compatible = "ti,omap-infra";
121 compatible = "ti,omap4-mpu";
128 * XXX: Use a flat representation of the OMAP3 interconnect.
129 * The real OMAP interconnect network is quite complex.
130 * Since it will not bring real advantage to represent that in DT for
131 * the moment, just use a fake OCP bus entry to represent the whole bus
135 compatible = "ti,omap5-l3-noc", "simple-bus";
136 #address-cells = <1>;
138 ranges = <0 0 0 0xc0000000>;
139 dma-ranges = <0x80000000 0x0 0x80000000 0x80000000>;
140 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
141 reg = <0 0x44000000 0 0x2000>,
142 <0 0x44800000 0 0x3000>,
143 <0 0x45000000 0 0x4000>;
144 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
145 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
147 l4_cfg: l4@4a000000 {
148 compatible = "ti,omap5-l4-cfg", "simple-bus";
149 #address-cells = <1>;
151 ranges = <0 0x4a000000 0x22a000>;
154 compatible = "ti,omap5-scm-core", "simple-bus";
155 reg = <0x2000 0x1000>;
156 #address-cells = <1>;
158 ranges = <0 0x2000 0x800>;
160 scm_conf: scm_conf@0 {
161 compatible = "syscon";
163 #address-cells = <1>;
168 scm_padconf_core: scm@2800 {
169 compatible = "ti,omap5-scm-padconf-core",
171 #address-cells = <1>;
173 ranges = <0 0x2800 0x800>;
175 omap5_pmx_core: pinmux@40 {
176 compatible = "ti,omap5-padconf",
179 #address-cells = <1>;
181 #pinctrl-cells = <1>;
182 #interrupt-cells = <1>;
183 interrupt-controller;
184 pinctrl-single,register-width = <16>;
185 pinctrl-single,function-mask = <0x7fff>;
188 omap5_padconf_global: omap5_padconf_global@5a0 {
189 compatible = "syscon",
192 #address-cells = <1>;
194 ranges = <0 0x5a0 0xec>;
196 pbias_regulator: pbias_regulator@60 {
197 compatible = "ti,pbias-omap5", "ti,pbias-omap";
199 syscon = <&omap5_padconf_global>;
200 pbias_mmc_reg: pbias_mmc_omap5 {
201 regulator-name = "pbias_mmc_omap5";
202 regulator-min-microvolt = <1800000>;
203 regulator-max-microvolt = <3000000>;
209 cm_core_aon: cm_core_aon@4000 {
210 compatible = "ti,omap5-cm-core-aon";
211 reg = <0x4000 0x2000>;
213 cm_core_aon_clocks: clocks {
214 #address-cells = <1>;
218 cm_core_aon_clockdomains: clockdomains {
222 cm_core: cm_core@8000 {
223 compatible = "ti,omap5-cm-core";
224 reg = <0x8000 0x3000>;
226 cm_core_clocks: clocks {
227 #address-cells = <1>;
231 cm_core_clockdomains: clockdomains {
236 l4_wkup: l4@4ae00000 {
237 compatible = "ti,omap5-l4-wkup", "simple-bus";
238 #address-cells = <1>;
240 ranges = <0 0x4ae00000 0x2b000>;
242 counter32k: counter@4000 {
243 compatible = "ti,omap-counter32k";
245 ti,hwmods = "counter_32k";
249 compatible = "ti,omap5-prm";
250 reg = <0x6000 0x3000>;
251 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
254 #address-cells = <1>;
258 prm_clockdomains: clockdomains {
263 compatible = "ti,omap5-scrm";
264 reg = <0xa000 0x2000>;
266 scrm_clocks: clocks {
267 #address-cells = <1>;
271 scrm_clockdomains: clockdomains {
275 omap5_pmx_wkup: pinmux@c840 {
276 compatible = "ti,omap5-padconf",
278 reg = <0xc840 0x003c>;
279 #address-cells = <1>;
281 #pinctrl-cells = <1>;
282 #interrupt-cells = <1>;
283 interrupt-controller;
284 pinctrl-single,register-width = <16>;
285 pinctrl-single,function-mask = <0x7fff>;
289 ocmcram: ocmcram@40300000 {
290 compatible = "mmio-sram";
291 reg = <0x40300000 0x20000>; /* 128k */
294 sdma: dma-controller@4a056000 {
295 compatible = "ti,omap4430-sdma";
296 reg = <0x4a056000 0x1000>;
297 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
298 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
299 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
300 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
303 dma-requests = <127>;
306 gpio1: gpio@4ae10000 {
307 compatible = "ti,omap4-gpio";
308 reg = <0x4ae10000 0x200>;
309 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
314 interrupt-controller;
315 #interrupt-cells = <2>;
318 gpio2: gpio@48055000 {
319 compatible = "ti,omap4-gpio";
320 reg = <0x48055000 0x200>;
321 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
325 interrupt-controller;
326 #interrupt-cells = <2>;
329 gpio3: gpio@48057000 {
330 compatible = "ti,omap4-gpio";
331 reg = <0x48057000 0x200>;
332 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
336 interrupt-controller;
337 #interrupt-cells = <2>;
340 gpio4: gpio@48059000 {
341 compatible = "ti,omap4-gpio";
342 reg = <0x48059000 0x200>;
343 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
347 interrupt-controller;
348 #interrupt-cells = <2>;
351 gpio5: gpio@4805b000 {
352 compatible = "ti,omap4-gpio";
353 reg = <0x4805b000 0x200>;
354 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
358 interrupt-controller;
359 #interrupt-cells = <2>;
362 gpio6: gpio@4805d000 {
363 compatible = "ti,omap4-gpio";
364 reg = <0x4805d000 0x200>;
365 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
369 interrupt-controller;
370 #interrupt-cells = <2>;
373 gpio7: gpio@48051000 {
374 compatible = "ti,omap4-gpio";
375 reg = <0x48051000 0x200>;
376 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
380 interrupt-controller;
381 #interrupt-cells = <2>;
384 gpio8: gpio@48053000 {
385 compatible = "ti,omap4-gpio";
386 reg = <0x48053000 0x200>;
387 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
391 interrupt-controller;
392 #interrupt-cells = <2>;
395 gpmc: gpmc@50000000 {
396 compatible = "ti,omap4430-gpmc";
397 reg = <0x50000000 0x1000>;
398 #address-cells = <2>;
400 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
404 gpmc,num-waitpins = <4>;
406 clocks = <&l3_iclk_div>;
408 interrupt-controller;
409 #interrupt-cells = <2>;
415 compatible = "ti,omap4-i2c";
416 reg = <0x48070000 0x100>;
417 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
418 #address-cells = <1>;
424 compatible = "ti,omap4-i2c";
425 reg = <0x48072000 0x100>;
426 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
427 #address-cells = <1>;
433 compatible = "ti,omap4-i2c";
434 reg = <0x48060000 0x100>;
435 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
436 #address-cells = <1>;
442 compatible = "ti,omap4-i2c";
443 reg = <0x4807a000 0x100>;
444 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
445 #address-cells = <1>;
451 compatible = "ti,omap4-i2c";
452 reg = <0x4807c000 0x100>;
453 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
454 #address-cells = <1>;
459 hwspinlock: spinlock@4a0f6000 {
460 compatible = "ti,omap4-hwspinlock";
461 reg = <0x4a0f6000 0x1000>;
462 ti,hwmods = "spinlock";
466 mcspi1: spi@48098000 {
467 compatible = "ti,omap4-mcspi";
468 reg = <0x48098000 0x200>;
469 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
470 #address-cells = <1>;
472 ti,hwmods = "mcspi1";
482 dma-names = "tx0", "rx0", "tx1", "rx1",
483 "tx2", "rx2", "tx3", "rx3";
486 mcspi2: spi@4809a000 {
487 compatible = "ti,omap4-mcspi";
488 reg = <0x4809a000 0x200>;
489 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
490 #address-cells = <1>;
492 ti,hwmods = "mcspi2";
498 dma-names = "tx0", "rx0", "tx1", "rx1";
501 mcspi3: spi@480b8000 {
502 compatible = "ti,omap4-mcspi";
503 reg = <0x480b8000 0x200>;
504 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
505 #address-cells = <1>;
507 ti,hwmods = "mcspi3";
509 dmas = <&sdma 15>, <&sdma 16>;
510 dma-names = "tx0", "rx0";
513 mcspi4: spi@480ba000 {
514 compatible = "ti,omap4-mcspi";
515 reg = <0x480ba000 0x200>;
516 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
517 #address-cells = <1>;
519 ti,hwmods = "mcspi4";
521 dmas = <&sdma 70>, <&sdma 71>;
522 dma-names = "tx0", "rx0";
525 uart1: serial@4806a000 {
526 compatible = "ti,omap4-uart";
527 reg = <0x4806a000 0x100>;
528 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
530 clock-frequency = <48000000>;
533 uart2: serial@4806c000 {
534 compatible = "ti,omap4-uart";
535 reg = <0x4806c000 0x100>;
536 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
538 clock-frequency = <48000000>;
541 uart3: serial@48020000 {
542 compatible = "ti,omap4-uart";
543 reg = <0x48020000 0x100>;
544 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
546 clock-frequency = <48000000>;
549 uart4: serial@4806e000 {
550 compatible = "ti,omap4-uart";
551 reg = <0x4806e000 0x100>;
552 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
554 clock-frequency = <48000000>;
557 uart5: serial@48066000 {
558 compatible = "ti,omap4-uart";
559 reg = <0x48066000 0x100>;
560 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
562 clock-frequency = <48000000>;
565 uart6: serial@48068000 {
566 compatible = "ti,omap4-uart";
567 reg = <0x48068000 0x100>;
568 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
570 clock-frequency = <48000000>;
574 compatible = "ti,omap4-hsmmc";
575 reg = <0x4809c000 0x400>;
576 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
579 ti,needs-special-reset;
580 dmas = <&sdma 61>, <&sdma 62>;
581 dma-names = "tx", "rx";
582 pbias-supply = <&pbias_mmc_reg>;
586 compatible = "ti,omap4-hsmmc";
587 reg = <0x480b4000 0x400>;
588 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
590 ti,needs-special-reset;
591 dmas = <&sdma 47>, <&sdma 48>;
592 dma-names = "tx", "rx";
596 compatible = "ti,omap4-hsmmc";
597 reg = <0x480ad000 0x400>;
598 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
600 ti,needs-special-reset;
601 dmas = <&sdma 77>, <&sdma 78>;
602 dma-names = "tx", "rx";
606 compatible = "ti,omap4-hsmmc";
607 reg = <0x480d1000 0x400>;
608 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
610 ti,needs-special-reset;
611 dmas = <&sdma 57>, <&sdma 58>;
612 dma-names = "tx", "rx";
616 compatible = "ti,omap4-hsmmc";
617 reg = <0x480d5000 0x400>;
618 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
620 ti,needs-special-reset;
621 dmas = <&sdma 59>, <&sdma 60>;
622 dma-names = "tx", "rx";
625 mmu_dsp: mmu@4a066000 {
626 compatible = "ti,omap4-iommu";
627 reg = <0x4a066000 0x100>;
628 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
629 ti,hwmods = "mmu_dsp";
633 mmu_ipu: mmu@55082000 {
634 compatible = "ti,omap4-iommu";
635 reg = <0x55082000 0x100>;
636 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
637 ti,hwmods = "mmu_ipu";
639 ti,iommu-bus-err-back;
642 keypad: keypad@4ae1c000 {
643 compatible = "ti,omap4-keypad";
644 reg = <0x4ae1c000 0x400>;
648 mcpdm: mcpdm@40132000 {
649 compatible = "ti,omap4-mcpdm";
650 reg = <0x40132000 0x7f>, /* MPU private access */
651 <0x49032000 0x7f>; /* L3 Interconnect */
652 reg-names = "mpu", "dma";
653 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
657 dma-names = "up_link", "dn_link";
661 dmic: dmic@4012e000 {
662 compatible = "ti,omap4-dmic";
663 reg = <0x4012e000 0x7f>, /* MPU private access */
664 <0x4902e000 0x7f>; /* L3 Interconnect */
665 reg-names = "mpu", "dma";
666 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
669 dma-names = "up_link";
673 mcbsp1: mcbsp@40122000 {
674 compatible = "ti,omap4-mcbsp";
675 reg = <0x40122000 0xff>, /* MPU private access */
676 <0x49022000 0xff>; /* L3 Interconnect */
677 reg-names = "mpu", "dma";
678 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
679 interrupt-names = "common";
680 ti,buffer-size = <128>;
681 ti,hwmods = "mcbsp1";
684 dma-names = "tx", "rx";
688 mcbsp2: mcbsp@40124000 {
689 compatible = "ti,omap4-mcbsp";
690 reg = <0x40124000 0xff>, /* MPU private access */
691 <0x49024000 0xff>; /* L3 Interconnect */
692 reg-names = "mpu", "dma";
693 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
694 interrupt-names = "common";
695 ti,buffer-size = <128>;
696 ti,hwmods = "mcbsp2";
699 dma-names = "tx", "rx";
703 mcbsp3: mcbsp@40126000 {
704 compatible = "ti,omap4-mcbsp";
705 reg = <0x40126000 0xff>, /* MPU private access */
706 <0x49026000 0xff>; /* L3 Interconnect */
707 reg-names = "mpu", "dma";
708 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
709 interrupt-names = "common";
710 ti,buffer-size = <128>;
711 ti,hwmods = "mcbsp3";
714 dma-names = "tx", "rx";
718 mailbox: mailbox@4a0f4000 {
719 compatible = "ti,omap4-mailbox";
720 reg = <0x4a0f4000 0x200>;
721 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
722 ti,hwmods = "mailbox";
724 ti,mbox-num-users = <3>;
725 ti,mbox-num-fifos = <8>;
727 ti,mbox-tx = <0 0 0>;
728 ti,mbox-rx = <1 0 0>;
731 ti,mbox-tx = <3 0 0>;
732 ti,mbox-rx = <2 0 0>;
736 timer1: timer@4ae18000 {
737 compatible = "ti,omap5430-timer";
738 reg = <0x4ae18000 0x80>;
739 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
740 ti,hwmods = "timer1";
744 timer2: timer@48032000 {
745 compatible = "ti,omap5430-timer";
746 reg = <0x48032000 0x80>;
747 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
748 ti,hwmods = "timer2";
751 timer3: timer@48034000 {
752 compatible = "ti,omap5430-timer";
753 reg = <0x48034000 0x80>;
754 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
755 ti,hwmods = "timer3";
758 timer4: timer@48036000 {
759 compatible = "ti,omap5430-timer";
760 reg = <0x48036000 0x80>;
761 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
762 ti,hwmods = "timer4";
765 timer5: timer@40138000 {
766 compatible = "ti,omap5430-timer";
767 reg = <0x40138000 0x80>,
769 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
770 ti,hwmods = "timer5";
775 timer6: timer@4013a000 {
776 compatible = "ti,omap5430-timer";
777 reg = <0x4013a000 0x80>,
779 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
780 ti,hwmods = "timer6";
785 timer7: timer@4013c000 {
786 compatible = "ti,omap5430-timer";
787 reg = <0x4013c000 0x80>,
789 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
790 ti,hwmods = "timer7";
794 timer8: timer@4013e000 {
795 compatible = "ti,omap5430-timer";
796 reg = <0x4013e000 0x80>,
798 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
799 ti,hwmods = "timer8";
804 timer9: timer@4803e000 {
805 compatible = "ti,omap5430-timer";
806 reg = <0x4803e000 0x80>;
807 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
808 ti,hwmods = "timer9";
812 timer10: timer@48086000 {
813 compatible = "ti,omap5430-timer";
814 reg = <0x48086000 0x80>;
815 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
816 ti,hwmods = "timer10";
820 timer11: timer@48088000 {
821 compatible = "ti,omap5430-timer";
822 reg = <0x48088000 0x80>;
823 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
824 ti,hwmods = "timer11";
829 compatible = "ti,omap5-wdt", "ti,omap3-wdt";
830 reg = <0x4ae14000 0x80>;
831 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
832 ti,hwmods = "wd_timer2";
836 compatible = "ti,omap5-dmm";
837 reg = <0x4e000000 0x800>;
838 interrupts = <0 113 0x4>;
842 emif1: emif@4c000000 {
843 compatible = "ti,emif-4d5";
846 phy-type = <2>; /* DDR PHY type: Intelli PHY */
847 reg = <0x4c000000 0x400>;
848 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
849 hw-caps-read-idle-ctrl;
850 hw-caps-ll-interface;
854 emif2: emif@4d000000 {
855 compatible = "ti,emif-4d5";
858 phy-type = <2>; /* DDR PHY type: Intelli PHY */
859 reg = <0x4d000000 0x400>;
860 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
861 hw-caps-read-idle-ctrl;
862 hw-caps-ll-interface;
866 usb3: omap_dwc3@4a020000 {
867 compatible = "ti,dwc3";
868 ti,hwmods = "usb_otg_ss";
869 reg = <0x4a020000 0x10000>;
870 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
871 #address-cells = <1>;
875 dwc3: dwc3@4a030000 {
876 compatible = "snps,dwc3";
877 reg = <0x4a030000 0x10000>;
878 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
879 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
880 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
881 interrupt-names = "peripheral",
884 phys = <&usb2_phy>, <&usb3_phy>;
885 phy-names = "usb2-phy", "usb3-phy";
886 dr_mode = "peripheral";
891 compatible = "ti,omap-ocp2scp";
892 #address-cells = <1>;
894 reg = <0x4a080000 0x20>;
896 ti,hwmods = "ocp2scp1";
897 usb2_phy: usb2phy@4a084000 {
898 compatible = "ti,omap-usb2";
899 reg = <0x4a084000 0x7c>;
900 syscon-phy-power = <&scm_conf 0x300>;
901 clocks = <&usb_phy_cm_clk32k>, <&usb_otg_ss_refclk960m>;
902 clock-names = "wkupclk", "refclk";
906 usb3_phy: usb3phy@4a084400 {
907 compatible = "ti,omap-usb3";
908 reg = <0x4a084400 0x80>,
911 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
912 syscon-phy-power = <&scm_conf 0x370>;
913 clocks = <&usb_phy_cm_clk32k>,
915 <&usb_otg_ss_refclk960m>;
916 clock-names = "wkupclk",
923 usbhstll: usbhstll@4a062000 {
924 compatible = "ti,usbhs-tll";
925 reg = <0x4a062000 0x1000>;
926 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
927 ti,hwmods = "usb_tll_hs";
930 usbhshost: usbhshost@4a064000 {
931 compatible = "ti,usbhs-host";
932 reg = <0x4a064000 0x800>;
933 ti,hwmods = "usb_host_hs";
934 #address-cells = <1>;
937 clocks = <&l3init_60m_fclk>,
940 clock-names = "refclk_60m_int",
944 usbhsohci: ohci@4a064800 {
945 compatible = "ti,ohci-omap3";
946 reg = <0x4a064800 0x400>;
947 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
950 usbhsehci: ehci@4a064c00 {
951 compatible = "ti,ehci-omap";
952 reg = <0x4a064c00 0x400>;
953 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
957 bandgap: bandgap@4a0021e0 {
958 reg = <0x4a0021e0 0xc
962 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
963 compatible = "ti,omap5430-bandgap";
965 #thermal-sensor-cells = <1>;
970 compatible = "ti,omap-ocp2scp";
971 #address-cells = <1>;
973 reg = <0x4a090000 0x20>;
975 ti,hwmods = "ocp2scp3";
976 sata_phy: phy@4a096000 {
977 compatible = "ti,phy-pipe3-sata";
978 reg = <0x4A096000 0x80>, /* phy_rx */
979 <0x4A096400 0x64>, /* phy_tx */
980 <0x4A096800 0x40>; /* pll_ctrl */
981 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
982 syscon-phy-power = <&scm_conf 0x374>;
983 clocks = <&sys_clkin>, <&sata_ref_clk>;
984 clock-names = "sysclk", "refclk";
989 sata: sata@4a141100 {
990 compatible = "snps,dwc-ahci";
991 reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
992 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
994 phy-names = "sata-phy";
995 clocks = <&sata_ref_clk>;
997 ports-implemented = <0x1>;
1001 compatible = "ti,omap5-dss";
1002 reg = <0x58000000 0x80>;
1003 status = "disabled";
1004 ti,hwmods = "dss_core";
1005 clocks = <&dss_dss_clk>;
1006 clock-names = "fck";
1007 #address-cells = <1>;
1012 compatible = "ti,omap5-dispc";
1013 reg = <0x58001000 0x1000>;
1014 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1015 ti,hwmods = "dss_dispc";
1016 clocks = <&dss_dss_clk>;
1017 clock-names = "fck";
1020 rfbi: encoder@58002000 {
1021 compatible = "ti,omap5-rfbi";
1022 reg = <0x58002000 0x100>;
1023 status = "disabled";
1024 ti,hwmods = "dss_rfbi";
1025 clocks = <&dss_dss_clk>, <&l3_iclk_div>;
1026 clock-names = "fck", "ick";
1029 dsi1: encoder@58004000 {
1030 compatible = "ti,omap5-dsi";
1031 reg = <0x58004000 0x200>,
1034 reg-names = "proto", "phy", "pll";
1035 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1036 status = "disabled";
1037 ti,hwmods = "dss_dsi1";
1038 clocks = <&dss_dss_clk>, <&dss_sys_clk>;
1039 clock-names = "fck", "sys_clk";
1042 dsi2: encoder@58005000 {
1043 compatible = "ti,omap5-dsi";
1044 reg = <0x58009000 0x200>,
1047 reg-names = "proto", "phy", "pll";
1048 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
1049 status = "disabled";
1050 ti,hwmods = "dss_dsi2";
1051 clocks = <&dss_dss_clk>, <&dss_sys_clk>;
1052 clock-names = "fck", "sys_clk";
1055 hdmi: encoder@58060000 {
1056 compatible = "ti,omap5-hdmi";
1057 reg = <0x58040000 0x200>,
1060 <0x58060000 0x19000>;
1061 reg-names = "wp", "pll", "phy", "core";
1062 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1063 status = "disabled";
1064 ti,hwmods = "dss_hdmi";
1065 clocks = <&dss_48mhz_clk>, <&dss_sys_clk>;
1066 clock-names = "fck", "sys_clk";
1068 dma-names = "audio_tx";
1072 abb_mpu: regulator-abb-mpu {
1073 compatible = "ti,abb-v2";
1074 regulator-name = "abb_mpu";
1075 #address-cells = <0>;
1077 clocks = <&sys_clkin>;
1078 ti,settling-time = <50>;
1079 ti,clock-cycles = <16>;
1081 reg = <0x4ae07cdc 0x8>, <0x4ae06014 0x4>,
1082 <0x4a0021c4 0x8>, <0x4ae0c318 0x4>;
1083 reg-names = "base-address", "int-address",
1084 "efuse-address", "ldo-address";
1085 ti,tranxdone-status-mask = <0x80>;
1086 /* LDOVBBMPU_MUX_CTRL */
1087 ti,ldovbb-override-mask = <0x400>;
1088 /* LDOVBBMPU_VSET_OUT */
1089 ti,ldovbb-vset-mask = <0x1F>;
1092 * NOTE: only FBB mode used but actual vset will
1093 * determine final biasing
1096 /*uV ABB efuse rbb_m fbb_m vset_m*/
1097 1060000 0 0x0 0 0x02000000 0x01F00000
1098 1250000 0 0x4 0 0x02000000 0x01F00000
1102 abb_mm: regulator-abb-mm {
1103 compatible = "ti,abb-v2";
1104 regulator-name = "abb_mm";
1105 #address-cells = <0>;
1107 clocks = <&sys_clkin>;
1108 ti,settling-time = <50>;
1109 ti,clock-cycles = <16>;
1111 reg = <0x4ae07ce4 0x8>, <0x4ae06010 0x4>,
1112 <0x4a0021a4 0x8>, <0x4ae0c314 0x4>;
1113 reg-names = "base-address", "int-address",
1114 "efuse-address", "ldo-address";
1115 ti,tranxdone-status-mask = <0x80000000>;
1116 /* LDOVBBMM_MUX_CTRL */
1117 ti,ldovbb-override-mask = <0x400>;
1118 /* LDOVBBMM_VSET_OUT */
1119 ti,ldovbb-vset-mask = <0x1F>;
1122 * NOTE: only FBB mode used but actual vset will
1123 * determine final biasing
1126 /*uV ABB efuse rbb_m fbb_m vset_m*/
1127 1025000 0 0x0 0 0x02000000 0x01F00000
1128 1120000 0 0x4 0 0x02000000 0x01F00000
1135 polling-delay = <500>; /* milliseconds */
1136 coefficients = <65 (-1791)>;
1139 /include/ "omap54xx-clocks.dtsi"
1142 coefficients = <117 (-2992)>;
1146 coefficients = <0 2000>;