arch/arm/boot/dts/omap5.dtsi

   1 /*
   2  * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  * Based on "omap4.dtsi"
   8  */
   9
  10 #include <dt-bindings/gpio/gpio.h>
  11 #include <dt-bindings/interrupt-controller/arm-gic.h>
  12 #include <dt-bindings/pinctrl/omap.h>
  13
  14 / {
  15         #address-cells = <2>;
  16         #size-cells = <2>;
  17
  18         compatible = "ti,omap5";
  19         interrupt-parent = <&wakeupgen>;
  20         chosen { };
  21
  22         aliases {
  23                 i2c0 = &i2c1;
  24                 i2c1 = &i2c2;
  25                 i2c2 = &i2c3;
  26                 i2c3 = &i2c4;
  27                 i2c4 = &i2c5;
  28                 mmc0 = &mmc1;
  29                 mmc1 = &mmc2;
  30                 mmc2 = &mmc3;
  31                 mmc3 = &mmc4;
  32                 mmc4 = &mmc5;
  33                 serial0 = &uart1;
  34                 serial1 = &uart2;
  35                 serial2 = &uart3;
  36                 serial3 = &uart4;
  37                 serial4 = &uart5;
  38                 serial5 = &uart6;
  39         };
  40
  41         cpus {
  42                 #address-cells = <1>;
  43                 #size-cells = <0>;
  44
  45                 cpu0: cpu@0 {
  46                         device_type = "cpu";
  47                         compatible = "arm,cortex-a15";
  48                         reg = <0x0>;
  49
  50                         operating-points = <
  51                                 /* kHz    uV */
  52                                 1000000 1060000
  53                                 1500000 1250000
  54                         >;
  55
  56                         clocks = <&dpll_mpu_ck>;
  57                         clock-names = "cpu";
  58
  59                         clock-latency = <300000>; /* From omap-cpufreq driver */
  60
  61                         /* cooling options */
  62                         cooling-min-level = <0>;
  63                         cooling-max-level = <2>;
  64                         #cooling-cells = <2>; /* min followed by max */
  65                 };
  66                 cpu@1 {
  67                         device_type = "cpu";
  68                         compatible = "arm,cortex-a15";
  69                         reg = <0x1>;
  70                 };
  71         };
  72
  73         thermal-zones {
  74                 #include "omap4-cpu-thermal.dtsi"
  75                 #include "omap5-gpu-thermal.dtsi"
  76                 #include "omap5-core-thermal.dtsi"
  77         };
  78
  79         timer {
  80                 compatible = "arm,armv7-timer";
  81                 /* PPI secure/nonsecure IRQ */
  82                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
  83                              <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
  84                              <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
  85                              <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>;
  86                 interrupt-parent = <&gic>;
  87         };
  88
  89         pmu {
  90                 compatible = "arm,cortex-a15-pmu";
  91                 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
  92                              <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
  93         };
  94
  95         gic: interrupt-controller@48211000 {
  96                 compatible = "arm,cortex-a15-gic";
  97                 interrupt-controller;
  98                 #interrupt-cells = <3>;
  99                 reg = <0 0x48211000 0 0x1000>,
 100                       <0 0x48212000 0 0x2000>,
 101                       <0 0x48214000 0 0x2000>,
 102                       <0 0x48216000 0 0x2000>;
 103                 interrupt-parent = <&gic>;
 104         };
 105
 106         wakeupgen: interrupt-controller@48281000 {
 107                 compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
 108                 interrupt-controller;
 109                 #interrupt-cells = <3>;
 110                 reg = <0 0x48281000 0 0x1000>;
 111                 interrupt-parent = <&gic>;
 112         };
 113
 114         /*
 115          * The soc node represents the soc top level view. It is used for IPs
 116          * that are not memory mapped in the MPU view or for the MPU itself.
 117          */
 118         soc {
 119                 compatible = "ti,omap-infra";
 120                 mpu {
 121                         compatible = "ti,omap4-mpu";
 122                         ti,hwmods = "mpu";
 123                         sram = <&ocmcram>;
 124                 };
 125         };
 126
 127         /*
 128          * XXX: Use a flat representation of the OMAP3 interconnect.
 129          * The real OMAP interconnect network is quite complex.
 130          * Since it will not bring real advantage to represent that in DT for
 131          * the moment, just use a fake OCP bus entry to represent the whole bus
 132          * hierarchy.
 133          */
 134         ocp {
 135                 compatible = "ti,omap5-l3-noc", "simple-bus";
 136                 #address-cells = <1>;
 137                 #size-cells = <1>;
 138                 ranges = <0 0 0 0xc0000000>;
 139                 dma-ranges = <0x80000000 0x0 0x80000000 0x80000000>;
 140                 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
 141                 reg = <0 0x44000000 0 0x2000>,
 142                       <0 0x44800000 0 0x3000>,
 143                       <0 0x45000000 0 0x4000>;
 144                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
 145                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 146
 147                 l4_cfg: l4@4a000000 {
 148                         compatible = "ti,omap5-l4-cfg", "simple-bus";
 149                         #address-cells = <1>;
 150                         #size-cells = <1>;
 151                         ranges = <0 0x4a000000 0x22a000>;
 152
 153                         scm_core: scm@2000 {
 154                                 compatible = "ti,omap5-scm-core", "simple-bus";
 155                                 reg = <0x2000 0x1000>;
 156                                 #address-cells = <1>;
 157                                 #size-cells = <1>;
 158                                 ranges = <0 0x2000 0x800>;
 159
 160                                 scm_conf: scm_conf@0 {
 161                                         compatible = "syscon";
 162                                         reg = <0x0 0x800>;
 163                                         #address-cells = <1>;
 164                                         #size-cells = <1>;
 165                                 };
 166                         };
 167
 168                         scm_padconf_core: scm@2800 {
 169                                 compatible = "ti,omap5-scm-padconf-core",
 170                                              "simple-bus";
 171                                 #address-cells = <1>;
 172                                 #size-cells = <1>;
 173                                 ranges = <0 0x2800 0x800>;
 174
 175                                 omap5_pmx_core: pinmux@40 {
 176                                         compatible = "ti,omap5-padconf",
 177                                                      "pinctrl-single";
 178                                         reg = <0x40 0x01b6>;
 179                                         #address-cells = <1>;
 180                                         #size-cells = <0>;
 181                                         #pinctrl-cells = <1>;
 182                                         #interrupt-cells = <1>;
 183                                         interrupt-controller;
 184                                         pinctrl-single,register-width = <16>;
 185                                         pinctrl-single,function-mask = <0x7fff>;
 186                                 };
 187
 188                                 omap5_padconf_global: omap5_padconf_global@5a0 {
 189                                         compatible = "syscon",
 190                                                      "simple-bus";
 191                                         reg = <0x5a0 0xec>;
 192                                         #address-cells = <1>;
 193                                         #size-cells = <1>;
 194                                         ranges = <0 0x5a0 0xec>;
 195
 196                                         pbias_regulator: pbias_regulator@60 {
 197                                                 compatible = "ti,pbias-omap5", "ti,pbias-omap";
 198                                                 reg = <0x60 0x4>;
 199                                                 syscon = <&omap5_padconf_global>;
 200                                                 pbias_mmc_reg: pbias_mmc_omap5 {
 201                                                         regulator-name = "pbias_mmc_omap5";
 202                                                         regulator-min-microvolt = <1800000>;
 203                                                         regulator-max-microvolt = <3000000>;
 204                                                 };
 205                                         };
 206                                 };
 207                         };
 208
 209                         cm_core_aon: cm_core_aon@4000 {
 210                                 compatible = "ti,omap5-cm-core-aon";
 211                                 reg = <0x4000 0x2000>;
 212
 213                                 cm_core_aon_clocks: clocks {
 214                                         #address-cells = <1>;
 215                                         #size-cells = <0>;
 216                                 };
 217
 218                                 cm_core_aon_clockdomains: clockdomains {
 219                                 };
 220                         };
 221
 222                         cm_core: cm_core@8000 {
 223                                 compatible = "ti,omap5-cm-core";
 224                                 reg = <0x8000 0x3000>;
 225
 226                                 cm_core_clocks: clocks {
 227                                         #address-cells = <1>;
 228                                         #size-cells = <0>;
 229                                 };
 230
 231                                 cm_core_clockdomains: clockdomains {
 232                                 };
 233                         };
 234                 };
 235
 236                 l4_wkup: l4@4ae00000 {
 237                         compatible = "ti,omap5-l4-wkup", "simple-bus";
 238                         #address-cells = <1>;
 239                         #size-cells = <1>;
 240                         ranges = <0 0x4ae00000 0x2b000>;
 241
 242                         counter32k: counter@4000 {
 243                                 compatible = "ti,omap-counter32k";
 244                                 reg = <0x4000 0x40>;
 245                                 ti,hwmods = "counter_32k";
 246                         };
 247
 248                         prm: prm@6000 {
 249                                 compatible = "ti,omap5-prm";
 250                                 reg = <0x6000 0x3000>;
 251                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 252
 253                                 prm_clocks: clocks {
 254                                         #address-cells = <1>;
 255                                         #size-cells = <0>;
 256                                 };
 257
 258                                 prm_clockdomains: clockdomains {
 259                                 };
 260                         };
 261
 262                         scrm: scrm@a000 {
 263                                 compatible = "ti,omap5-scrm";
 264                                 reg = <0xa000 0x2000>;
 265
 266                                 scrm_clocks: clocks {
 267                                         #address-cells = <1>;
 268                                         #size-cells = <0>;
 269                                 };
 270
 271                                 scrm_clockdomains: clockdomains {
 272                                 };
 273                         };
 274
 275                         omap5_pmx_wkup: pinmux@c840 {
 276                                 compatible = "ti,omap5-padconf",
 277                                              "pinctrl-single";
 278                                 reg = <0xc840 0x003c>;
 279                                 #address-cells = <1>;
 280                                 #size-cells = <0>;
 281                                 #pinctrl-cells = <1>;
 282                                 #interrupt-cells = <1>;
 283                                 interrupt-controller;
 284                                 pinctrl-single,register-width = <16>;
 285                                 pinctrl-single,function-mask = <0x7fff>;
 286                         };
 287                 };
 288
 289                 ocmcram: ocmcram@40300000 {
 290                         compatible = "mmio-sram";
 291                         reg = <0x40300000 0x20000>; /* 128k */
 292                 };
 293
 294                 sdma: dma-controller@4a056000 {
 295                         compatible = "ti,omap4430-sdma";
 296                         reg = <0x4a056000 0x1000>;
 297                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
 298                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 299                                      <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
 300                                      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 301                         #dma-cells = <1>;
 302                         dma-channels = <32>;
 303                         dma-requests = <127>;
 304                 };
 305
 306                 gpio1: gpio@4ae10000 {
 307                         compatible = "ti,omap4-gpio";
 308                         reg = <0x4ae10000 0x200>;
 309                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 310                         ti,hwmods = "gpio1";
 311                         ti,gpio-always-on;
 312                         gpio-controller;
 313                         #gpio-cells = <2>;
 314                         interrupt-controller;
 315                         #interrupt-cells = <2>;
 316                 };
 317
 318                 gpio2: gpio@48055000 {
 319                         compatible = "ti,omap4-gpio";
 320                         reg = <0x48055000 0x200>;
 321                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 322                         ti,hwmods = "gpio2";
 323                         gpio-controller;
 324                         #gpio-cells = <2>;
 325                         interrupt-controller;
 326                         #interrupt-cells = <2>;
 327                 };
 328
 329                 gpio3: gpio@48057000 {
 330                         compatible = "ti,omap4-gpio";
 331                         reg = <0x48057000 0x200>;
 332                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 333                         ti,hwmods = "gpio3";
 334                         gpio-controller;
 335                         #gpio-cells = <2>;
 336                         interrupt-controller;
 337                         #interrupt-cells = <2>;
 338                 };
 339
 340                 gpio4: gpio@48059000 {
 341                         compatible = "ti,omap4-gpio";
 342                         reg = <0x48059000 0x200>;
 343                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 344                         ti,hwmods = "gpio4";
 345                         gpio-controller;
 346                         #gpio-cells = <2>;
 347                         interrupt-controller;
 348                         #interrupt-cells = <2>;
 349                 };
 350
 351                 gpio5: gpio@4805b000 {
 352                         compatible = "ti,omap4-gpio";
 353                         reg = <0x4805b000 0x200>;
 354                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 355                         ti,hwmods = "gpio5";
 356                         gpio-controller;
 357                         #gpio-cells = <2>;
 358                         interrupt-controller;
 359                         #interrupt-cells = <2>;
 360                 };
 361
 362                 gpio6: gpio@4805d000 {
 363                         compatible = "ti,omap4-gpio";
 364                         reg = <0x4805d000 0x200>;
 365                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 366                         ti,hwmods = "gpio6";
 367                         gpio-controller;
 368                         #gpio-cells = <2>;
 369                         interrupt-controller;
 370                         #interrupt-cells = <2>;
 371                 };
 372
 373                 gpio7: gpio@48051000 {
 374                         compatible = "ti,omap4-gpio";
 375                         reg = <0x48051000 0x200>;
 376                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 377                         ti,hwmods = "gpio7";
 378                         gpio-controller;
 379                         #gpio-cells = <2>;
 380                         interrupt-controller;
 381                         #interrupt-cells = <2>;
 382                 };
 383
 384                 gpio8: gpio@48053000 {
 385                         compatible = "ti,omap4-gpio";
 386                         reg = <0x48053000 0x200>;
 387                         interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 388                         ti,hwmods = "gpio8";
 389                         gpio-controller;
 390                         #gpio-cells = <2>;
 391                         interrupt-controller;
 392                         #interrupt-cells = <2>;
 393                 };
 394
 395                 gpmc: gpmc@50000000 {
 396                         compatible = "ti,omap4430-gpmc";
 397                         reg = <0x50000000 0x1000>;
 398                         #address-cells = <2>;
 399                         #size-cells = <1>;
 400                         interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 401                         dmas = <&sdma 4>;
 402                         dma-names = "rxtx";
 403                         gpmc,num-cs = <8>;
 404                         gpmc,num-waitpins = <4>;
 405                         ti,hwmods = "gpmc";
 406                         clocks = <&l3_iclk_div>;
 407                         clock-names = "fck";
 408                         interrupt-controller;
 409                         #interrupt-cells = <2>;
 410                         gpio-controller;
 411                         #gpio-cells = <2>;
 412                 };
 413
 414                 i2c1: i2c@48070000 {
 415                         compatible = "ti,omap4-i2c";
 416                         reg = <0x48070000 0x100>;
 417                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 418                         #address-cells = <1>;
 419                         #size-cells = <0>;
 420                         ti,hwmods = "i2c1";
 421                 };
 422
 423                 i2c2: i2c@48072000 {
 424                         compatible = "ti,omap4-i2c";
 425                         reg = <0x48072000 0x100>;
 426                         interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 427                         #address-cells = <1>;
 428                         #size-cells = <0>;
 429                         ti,hwmods = "i2c2";
 430                 };
 431
 432                 i2c3: i2c@48060000 {
 433                         compatible = "ti,omap4-i2c";
 434                         reg = <0x48060000 0x100>;
 435                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 436                         #address-cells = <1>;
 437                         #size-cells = <0>;
 438                         ti,hwmods = "i2c3";
 439                 };
 440
 441                 i2c4: i2c@4807a000 {
 442                         compatible = "ti,omap4-i2c";
 443                         reg = <0x4807a000 0x100>;
 444                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 445                         #address-cells = <1>;
 446                         #size-cells = <0>;
 447                         ti,hwmods = "i2c4";
 448                 };
 449
 450                 i2c5: i2c@4807c000 {
 451                         compatible = "ti,omap4-i2c";
 452                         reg = <0x4807c000 0x100>;
 453                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 454                         #address-cells = <1>;
 455                         #size-cells = <0>;
 456                         ti,hwmods = "i2c5";
 457                 };
 458
 459                 hwspinlock: spinlock@4a0f6000 {
 460                         compatible = "ti,omap4-hwspinlock";
 461                         reg = <0x4a0f6000 0x1000>;
 462                         ti,hwmods = "spinlock";
 463                         #hwlock-cells = <1>;
 464                 };
 465
 466                 mcspi1: spi@48098000 {
 467                         compatible = "ti,omap4-mcspi";
 468                         reg = <0x48098000 0x200>;
 469                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 470                         #address-cells = <1>;
 471                         #size-cells = <0>;
 472                         ti,hwmods = "mcspi1";
 473                         ti,spi-num-cs = <4>;
 474                         dmas = <&sdma 35>,
 475                                <&sdma 36>,
 476                                <&sdma 37>,
 477                                <&sdma 38>,
 478                                <&sdma 39>,
 479                                <&sdma 40>,
 480                                <&sdma 41>,
 481                                <&sdma 42>;
 482                         dma-names = "tx0", "rx0", "tx1", "rx1",
 483                                     "tx2", "rx2", "tx3", "rx3";
 484                 };
 485
 486                 mcspi2: spi@4809a000 {
 487                         compatible = "ti,omap4-mcspi";
 488                         reg = <0x4809a000 0x200>;
 489                         interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 490                         #address-cells = <1>;
 491                         #size-cells = <0>;
 492                         ti,hwmods = "mcspi2";
 493                         ti,spi-num-cs = <2>;
 494                         dmas = <&sdma 43>,
 495                                <&sdma 44>,
 496                                <&sdma 45>,
 497                                <&sdma 46>;
 498                         dma-names = "tx0", "rx0", "tx1", "rx1";
 499                 };
 500
 501                 mcspi3: spi@480b8000 {
 502                         compatible = "ti,omap4-mcspi";
 503                         reg = <0x480b8000 0x200>;
 504                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 505                         #address-cells = <1>;
 506                         #size-cells = <0>;
 507                         ti,hwmods = "mcspi3";
 508                         ti,spi-num-cs = <2>;
 509                         dmas = <&sdma 15>, <&sdma 16>;
 510                         dma-names = "tx0", "rx0";
 511                 };
 512
 513                 mcspi4: spi@480ba000 {
 514                         compatible = "ti,omap4-mcspi";
 515                         reg = <0x480ba000 0x200>;
 516                         interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 517                         #address-cells = <1>;
 518                         #size-cells = <0>;
 519                         ti,hwmods = "mcspi4";
 520                         ti,spi-num-cs = <1>;
 521                         dmas = <&sdma 70>, <&sdma 71>;
 522                         dma-names = "tx0", "rx0";
 523                 };
 524
 525                 uart1: serial@4806a000 {
 526                         compatible = "ti,omap4-uart";
 527                         reg = <0x4806a000 0x100>;
 528                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 529                         ti,hwmods = "uart1";
 530                         clock-frequency = <48000000>;
 531                 };
 532
 533                 uart2: serial@4806c000 {
 534                         compatible = "ti,omap4-uart";
 535                         reg = <0x4806c000 0x100>;
 536                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 537                         ti,hwmods = "uart2";
 538                         clock-frequency = <48000000>;
 539                 };
 540
 541                 uart3: serial@48020000 {
 542                         compatible = "ti,omap4-uart";
 543                         reg = <0x48020000 0x100>;
 544                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 545                         ti,hwmods = "uart3";
 546                         clock-frequency = <48000000>;
 547                 };
 548
 549                 uart4: serial@4806e000 {
 550                         compatible = "ti,omap4-uart";
 551                         reg = <0x4806e000 0x100>;
 552                         interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 553                         ti,hwmods = "uart4";
 554                         clock-frequency = <48000000>;
 555                 };
 556
 557                 uart5: serial@48066000 {
 558                         compatible = "ti,omap4-uart";
 559                         reg = <0x48066000 0x100>;
 560                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 561                         ti,hwmods = "uart5";
 562                         clock-frequency = <48000000>;
 563                 };
 564
 565                 uart6: serial@48068000 {
 566                         compatible = "ti,omap4-uart";
 567                         reg = <0x48068000 0x100>;
 568                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 569                         ti,hwmods = "uart6";
 570                         clock-frequency = <48000000>;
 571                 };
 572
 573                 mmc1: mmc@4809c000 {
 574                         compatible = "ti,omap4-hsmmc";
 575                         reg = <0x4809c000 0x400>;
 576                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 577                         ti,hwmods = "mmc1";
 578                         ti,dual-volt;
 579                         ti,needs-special-reset;
 580                         dmas = <&sdma 61>, <&sdma 62>;
 581                         dma-names = "tx", "rx";
 582                         pbias-supply = <&pbias_mmc_reg>;
 583                 };
 584
 585                 mmc2: mmc@480b4000 {
 586                         compatible = "ti,omap4-hsmmc";
 587                         reg = <0x480b4000 0x400>;
 588                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 589                         ti,hwmods = "mmc2";
 590                         ti,needs-special-reset;
 591                         dmas = <&sdma 47>, <&sdma 48>;
 592                         dma-names = "tx", "rx";
 593                 };
 594
 595                 mmc3: mmc@480ad000 {
 596                         compatible = "ti,omap4-hsmmc";
 597                         reg = <0x480ad000 0x400>;
 598                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 599                         ti,hwmods = "mmc3";
 600                         ti,needs-special-reset;
 601                         dmas = <&sdma 77>, <&sdma 78>;
 602                         dma-names = "tx", "rx";
 603                 };
 604
 605                 mmc4: mmc@480d1000 {
 606                         compatible = "ti,omap4-hsmmc";
 607                         reg = <0x480d1000 0x400>;
 608                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 609                         ti,hwmods = "mmc4";
 610                         ti,needs-special-reset;
 611                         dmas = <&sdma 57>, <&sdma 58>;
 612                         dma-names = "tx", "rx";
 613                 };
 614
 615                 mmc5: mmc@480d5000 {
 616                         compatible = "ti,omap4-hsmmc";
 617                         reg = <0x480d5000 0x400>;
 618                         interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 619                         ti,hwmods = "mmc5";
 620                         ti,needs-special-reset;
 621                         dmas = <&sdma 59>, <&sdma 60>;
 622                         dma-names = "tx", "rx";
 623                 };
 624
 625                 mmu_dsp: mmu@4a066000 {
 626                         compatible = "ti,omap4-iommu";
 627                         reg = <0x4a066000 0x100>;
 628                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 629                         ti,hwmods = "mmu_dsp";
 630                         #iommu-cells = <0>;
 631                 };
 632
 633                 mmu_ipu: mmu@55082000 {
 634                         compatible = "ti,omap4-iommu";
 635                         reg = <0x55082000 0x100>;
 636                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 637                         ti,hwmods = "mmu_ipu";
 638                         #iommu-cells = <0>;
 639                         ti,iommu-bus-err-back;
 640                 };
 641
 642                 keypad: keypad@4ae1c000 {
 643                         compatible = "ti,omap4-keypad";
 644                         reg = <0x4ae1c000 0x400>;
 645                         ti,hwmods = "kbd";
 646                 };
 647
 648                 mcpdm: mcpdm@40132000 {
 649                         compatible = "ti,omap4-mcpdm";
 650                         reg = <0x40132000 0x7f>, /* MPU private access */
 651                               <0x49032000 0x7f>; /* L3 Interconnect */
 652                         reg-names = "mpu", "dma";
 653                         interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
 654                         ti,hwmods = "mcpdm";
 655                         dmas = <&sdma 65>,
 656                                <&sdma 66>;
 657                         dma-names = "up_link", "dn_link";
 658                         status = "disabled";
 659                 };
 660
 661                 dmic: dmic@4012e000 {
 662                         compatible = "ti,omap4-dmic";
 663                         reg = <0x4012e000 0x7f>, /* MPU private access */
 664                               <0x4902e000 0x7f>; /* L3 Interconnect */
 665                         reg-names = "mpu", "dma";
 666                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 667                         ti,hwmods = "dmic";
 668                         dmas = <&sdma 67>;
 669                         dma-names = "up_link";
 670                         status = "disabled";
 671                 };
 672
 673                 mcbsp1: mcbsp@40122000 {
 674                         compatible = "ti,omap4-mcbsp";
 675                         reg = <0x40122000 0xff>, /* MPU private access */
 676                               <0x49022000 0xff>; /* L3 Interconnect */
 677                         reg-names = "mpu", "dma";
 678                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 679                         interrupt-names = "common";
 680                         ti,buffer-size = <128>;
 681                         ti,hwmods = "mcbsp1";
 682                         dmas = <&sdma 33>,
 683                                <&sdma 34>;
 684                         dma-names = "tx", "rx";
 685                         status = "disabled";
 686                 };
 687
 688                 mcbsp2: mcbsp@40124000 {
 689                         compatible = "ti,omap4-mcbsp";
 690                         reg = <0x40124000 0xff>, /* MPU private access */
 691                               <0x49024000 0xff>; /* L3 Interconnect */
 692                         reg-names = "mpu", "dma";
 693                         interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 694                         interrupt-names = "common";
 695                         ti,buffer-size = <128>;
 696                         ti,hwmods = "mcbsp2";
 697                         dmas = <&sdma 17>,
 698                                <&sdma 18>;
 699                         dma-names = "tx", "rx";
 700                         status = "disabled";
 701                 };
 702
 703                 mcbsp3: mcbsp@40126000 {
 704                         compatible = "ti,omap4-mcbsp";
 705                         reg = <0x40126000 0xff>, /* MPU private access */
 706                               <0x49026000 0xff>; /* L3 Interconnect */
 707                         reg-names = "mpu", "dma";
 708                         interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 709                         interrupt-names = "common";
 710                         ti,buffer-size = <128>;
 711                         ti,hwmods = "mcbsp3";
 712                         dmas = <&sdma 19>,
 713                                <&sdma 20>;
 714                         dma-names = "tx", "rx";
 715                         status = "disabled";
 716                 };
 717
 718                 mailbox: mailbox@4a0f4000 {
 719                         compatible = "ti,omap4-mailbox";
 720                         reg = <0x4a0f4000 0x200>;
 721                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 722                         ti,hwmods = "mailbox";
 723                         #mbox-cells = <1>;
 724                         ti,mbox-num-users = <3>;
 725                         ti,mbox-num-fifos = <8>;
 726                         mbox_ipu: mbox_ipu {
 727                                 ti,mbox-tx = <0 0 0>;
 728                                 ti,mbox-rx = <1 0 0>;
 729                         };
 730                         mbox_dsp: mbox_dsp {
 731                                 ti,mbox-tx = <3 0 0>;
 732                                 ti,mbox-rx = <2 0 0>;
 733                         };
 734                 };
 735
 736                 timer1: timer@4ae18000 {
 737                         compatible = "ti,omap5430-timer";
 738                         reg = <0x4ae18000 0x80>;
 739                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 740                         ti,hwmods = "timer1";
 741                         ti,timer-alwon;
 742                 };
 743
 744                 timer2: timer@48032000 {
 745                         compatible = "ti,omap5430-timer";
 746                         reg = <0x48032000 0x80>;
 747                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 748                         ti,hwmods = "timer2";
 749                 };
 750
 751                 timer3: timer@48034000 {
 752                         compatible = "ti,omap5430-timer";
 753                         reg = <0x48034000 0x80>;
 754                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 755                         ti,hwmods = "timer3";
 756                 };
 757
 758                 timer4: timer@48036000 {
 759                         compatible = "ti,omap5430-timer";
 760                         reg = <0x48036000 0x80>;
 761                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 762                         ti,hwmods = "timer4";
 763                 };
 764
 765                 timer5: timer@40138000 {
 766                         compatible = "ti,omap5430-timer";
 767                         reg = <0x40138000 0x80>,
 768                               <0x49038000 0x80>;
 769                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 770                         ti,hwmods = "timer5";
 771                         ti,timer-dsp;
 772                         ti,timer-pwm;
 773                 };
 774
 775                 timer6: timer@4013a000 {
 776                         compatible = "ti,omap5430-timer";
 777                         reg = <0x4013a000 0x80>,
 778                               <0x4903a000 0x80>;
 779                         interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 780                         ti,hwmods = "timer6";
 781                         ti,timer-dsp;
 782                         ti,timer-pwm;
 783                 };
 784
 785                 timer7: timer@4013c000 {
 786                         compatible = "ti,omap5430-timer";
 787                         reg = <0x4013c000 0x80>,
 788                               <0x4903c000 0x80>;
 789                         interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 790                         ti,hwmods = "timer7";
 791                         ti,timer-dsp;
 792                 };
 793
 794                 timer8: timer@4013e000 {
 795                         compatible = "ti,omap5430-timer";
 796                         reg = <0x4013e000 0x80>,
 797                               <0x4903e000 0x80>;
 798                         interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 799                         ti,hwmods = "timer8";
 800                         ti,timer-dsp;
 801                         ti,timer-pwm;
 802                 };
 803
 804                 timer9: timer@4803e000 {
 805                         compatible = "ti,omap5430-timer";
 806                         reg = <0x4803e000 0x80>;
 807                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 808                         ti,hwmods = "timer9";
 809                         ti,timer-pwm;
 810                 };
 811
 812                 timer10: timer@48086000 {
 813                         compatible = "ti,omap5430-timer";
 814                         reg = <0x48086000 0x80>;
 815                         interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 816                         ti,hwmods = "timer10";
 817                         ti,timer-pwm;
 818                 };
 819
 820                 timer11: timer@48088000 {
 821                         compatible = "ti,omap5430-timer";
 822                         reg = <0x48088000 0x80>;
 823                         interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 824                         ti,hwmods = "timer11";
 825                         ti,timer-pwm;
 826                 };
 827
 828                 wdt2: wdt@4ae14000 {
 829                         compatible = "ti,omap5-wdt", "ti,omap3-wdt";
 830                         reg = <0x4ae14000 0x80>;
 831                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 832                         ti,hwmods = "wd_timer2";
 833                 };
 834
 835                 dmm@4e000000 {
 836                         compatible = "ti,omap5-dmm";
 837                         reg = <0x4e000000 0x800>;
 838                         interrupts = <0 113 0x4>;
 839                         ti,hwmods = "dmm";
 840                 };
 841
 842                 emif1: emif@4c000000 {
 843                         compatible      = "ti,emif-4d5";
 844                         ti,hwmods       = "emif1";
 845                         ti,no-idle-on-init;
 846                         phy-type        = <2>; /* DDR PHY type: Intelli PHY */
 847                         reg = <0x4c000000 0x400>;
 848                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 849                         hw-caps-read-idle-ctrl;
 850                         hw-caps-ll-interface;
 851                         hw-caps-temp-alert;
 852                 };
 853
 854                 emif2: emif@4d000000 {
 855                         compatible      = "ti,emif-4d5";
 856                         ti,hwmods       = "emif2";
 857                         ti,no-idle-on-init;
 858                         phy-type        = <2>; /* DDR PHY type: Intelli PHY */
 859                         reg = <0x4d000000 0x400>;
 860                         interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 861                         hw-caps-read-idle-ctrl;
 862                         hw-caps-ll-interface;
 863                         hw-caps-temp-alert;
 864                 };
 865
 866                 usb3: omap_dwc3@4a020000 {
 867                         compatible = "ti,dwc3";
 868                         ti,hwmods = "usb_otg_ss";
 869                         reg = <0x4a020000 0x10000>;
 870                         interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 871                         #address-cells = <1>;
 872                         #size-cells = <1>;
 873                         utmi-mode = <2>;
 874                         ranges;
 875                         dwc3: dwc3@4a030000 {
 876                                 compatible = "snps,dwc3";
 877                                 reg = <0x4a030000 0x10000>;
 878                                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
 879                                              <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
 880                                              <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 881                                 interrupt-names = "peripheral",
 882                                                   "host",
 883                                                   "otg";
 884                                 phys = <&usb2_phy>, <&usb3_phy>;
 885                                 phy-names = "usb2-phy", "usb3-phy";
 886                                 dr_mode = "peripheral";
 887                         };
 888                 };
 889
 890                 ocp2scp@4a080000 {
 891                         compatible = "ti,omap-ocp2scp";
 892                         #address-cells = <1>;
 893                         #size-cells = <1>;
 894                         reg = <0x4a080000 0x20>;
 895                         ranges;
 896                         ti,hwmods = "ocp2scp1";
 897                         usb2_phy: usb2phy@4a084000 {
 898                                 compatible = "ti,omap-usb2";
 899                                 reg = <0x4a084000 0x7c>;
 900                                 syscon-phy-power = <&scm_conf 0x300>;
 901                                 clocks = <&usb_phy_cm_clk32k>, <&usb_otg_ss_refclk960m>;
 902                                 clock-names = "wkupclk", "refclk";
 903                                 #phy-cells = <0>;
 904                         };
 905
 906                         usb3_phy: usb3phy@4a084400 {
 907                                 compatible = "ti,omap-usb3";
 908                                 reg = <0x4a084400 0x80>,
 909                                       <0x4a084800 0x64>,
 910                                       <0x4a084c00 0x40>;
 911                                 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
 912                                 syscon-phy-power = <&scm_conf 0x370>;
 913                                 clocks = <&usb_phy_cm_clk32k>,
 914                                          <&sys_clkin>,
 915                                          <&usb_otg_ss_refclk960m>;
 916                                 clock-names =   "wkupclk",
 917                                                 "sysclk",
 918                                                 "refclk";
 919                                 #phy-cells = <0>;
 920                         };
 921                 };
 922
 923                 usbhstll: usbhstll@4a062000 {
 924                         compatible = "ti,usbhs-tll";
 925                         reg = <0x4a062000 0x1000>;
 926                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 927                         ti,hwmods = "usb_tll_hs";
 928                 };
 929
 930                 usbhshost: usbhshost@4a064000 {
 931                         compatible = "ti,usbhs-host";
 932                         reg = <0x4a064000 0x800>;
 933                         ti,hwmods = "usb_host_hs";
 934                         #address-cells = <1>;
 935                         #size-cells = <1>;
 936                         ranges;
 937                         clocks = <&l3init_60m_fclk>,
 938                                  <&xclk60mhsp1_ck>,
 939                                  <&xclk60mhsp2_ck>;
 940                         clock-names = "refclk_60m_int",
 941                                       "refclk_60m_ext_p1",
 942                                       "refclk_60m_ext_p2";
 943
 944                         usbhsohci: ohci@4a064800 {
 945                                 compatible = "ti,ohci-omap3";
 946                                 reg = <0x4a064800 0x400>;
 947                                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 948                         };
 949
 950                         usbhsehci: ehci@4a064c00 {
 951                                 compatible = "ti,ehci-omap";
 952                                 reg = <0x4a064c00 0x400>;
 953                                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 954                         };
 955                 };
 956
 957                 bandgap: bandgap@4a0021e0 {
 958                         reg = <0x4a0021e0 0xc
 959                                0x4a00232c 0xc
 960                                0x4a002380 0x2c
 961                                0x4a0023C0 0x3c>;
 962                         interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
 963                         compatible = "ti,omap5430-bandgap";
 964
 965                         #thermal-sensor-cells = <1>;
 966                 };
 967
 968                 /* OCP2SCP3 */
 969                 ocp2scp@4a090000 {
 970                         compatible = "ti,omap-ocp2scp";
 971                         #address-cells = <1>;
 972                         #size-cells = <1>;
 973                         reg = <0x4a090000 0x20>;
 974                         ranges;
 975                         ti,hwmods = "ocp2scp3";
 976                         sata_phy: phy@4a096000 {
 977                                 compatible = "ti,phy-pipe3-sata";
 978                                 reg = <0x4A096000 0x80>, /* phy_rx */
 979                                       <0x4A096400 0x64>, /* phy_tx */
 980                                       <0x4A096800 0x40>; /* pll_ctrl */
 981                                 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
 982                                 syscon-phy-power = <&scm_conf 0x374>;
 983                                 clocks = <&sys_clkin>, <&sata_ref_clk>;
 984                                 clock-names = "sysclk", "refclk";
 985                                 #phy-cells = <0>;
 986                         };
 987                 };
 988
 989                 sata: sata@4a141100 {
 990                         compatible = "snps,dwc-ahci";
 991                         reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
 992                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 993                         phys = <&sata_phy>;
 994                         phy-names = "sata-phy";
 995                         clocks = <&sata_ref_clk>;
 996                         ti,hwmods = "sata";
 997                         ports-implemented = <0x1>;
 998                 };
 999
1000                 dss: dss@58000000 {
1001                         compatible = "ti,omap5-dss";
1002                         reg = <0x58000000 0x80>;
1003                         status = "disabled";
1004                         ti,hwmods = "dss_core";
1005                         clocks = <&dss_dss_clk>;
1006                         clock-names = "fck";
1007                         #address-cells = <1>;
1008                         #size-cells = <1>;
1009                         ranges;
1010
1011                         dispc@58001000 {
1012                                 compatible = "ti,omap5-dispc";
1013                                 reg = <0x58001000 0x1000>;
1014                                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1015                                 ti,hwmods = "dss_dispc";
1016                                 clocks = <&dss_dss_clk>;
1017                                 clock-names = "fck";
1018                         };
1019
1020                         rfbi: encoder@58002000  {
1021                                 compatible = "ti,omap5-rfbi";
1022                                 reg = <0x58002000 0x100>;
1023                                 status = "disabled";
1024                                 ti,hwmods = "dss_rfbi";
1025                                 clocks = <&dss_dss_clk>, <&l3_iclk_div>;
1026                                 clock-names = "fck", "ick";
1027                         };
1028
1029                         dsi1: encoder@58004000 {
1030                                 compatible = "ti,omap5-dsi";
1031                                 reg = <0x58004000 0x200>,
1032                                       <0x58004200 0x40>,
1033                                       <0x58004300 0x40>;
1034                                 reg-names = "proto", "phy", "pll";
1035                                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1036                                 status = "disabled";
1037                                 ti,hwmods = "dss_dsi1";
1038                                 clocks = <&dss_dss_clk>, <&dss_sys_clk>;
1039                                 clock-names = "fck", "sys_clk";
1040                         };
1041
1042                         dsi2: encoder@58005000 {
1043                                 compatible = "ti,omap5-dsi";
1044                                 reg = <0x58009000 0x200>,
1045                                       <0x58009200 0x40>,
1046                                       <0x58009300 0x40>;
1047                                 reg-names = "proto", "phy", "pll";
1048                                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
1049                                 status = "disabled";
1050                                 ti,hwmods = "dss_dsi2";
1051                                 clocks = <&dss_dss_clk>, <&dss_sys_clk>;
1052                                 clock-names = "fck", "sys_clk";
1053                         };
1054
1055                         hdmi: encoder@58060000 {
1056                                 compatible = "ti,omap5-hdmi";
1057                                 reg = <0x58040000 0x200>,
1058                                       <0x58040200 0x80>,
1059                                       <0x58040300 0x80>,
1060                                       <0x58060000 0x19000>;
1061                                 reg-names = "wp", "pll", "phy", "core";
1062                                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1063                                 status = "disabled";
1064                                 ti,hwmods = "dss_hdmi";
1065                                 clocks = <&dss_48mhz_clk>, <&dss_sys_clk>;
1066                                 clock-names = "fck", "sys_clk";
1067                                 dmas = <&sdma 76>;
1068                                 dma-names = "audio_tx";
1069                         };
1070                 };
1071
1072                 abb_mpu: regulator-abb-mpu {
1073                         compatible = "ti,abb-v2";
1074                         regulator-name = "abb_mpu";
1075                         #address-cells = <0>;
1076                         #size-cells = <0>;
1077                         clocks = <&sys_clkin>;
1078                         ti,settling-time = <50>;
1079                         ti,clock-cycles = <16>;
1080
1081                         reg = <0x4ae07cdc 0x8>, <0x4ae06014 0x4>,
1082                               <0x4a0021c4 0x8>, <0x4ae0c318 0x4>;
1083                         reg-names = "base-address", "int-address",
1084                                     "efuse-address", "ldo-address";
1085                         ti,tranxdone-status-mask = <0x80>;
1086                         /* LDOVBBMPU_MUX_CTRL */
1087                         ti,ldovbb-override-mask = <0x400>;
1088                         /* LDOVBBMPU_VSET_OUT */
1089                         ti,ldovbb-vset-mask = <0x1F>;
1090
1091                         /*
1092                          * NOTE: only FBB mode used but actual vset will
1093                          * determine final biasing
1094                          */
1095                         ti,abb_info = <
1096                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
1097                         1060000         0       0x0     0 0x02000000 0x01F00000
1098                         1250000         0       0x4     0 0x02000000 0x01F00000
1099                         >;
1100                 };
1101
1102                 abb_mm: regulator-abb-mm {
1103                         compatible = "ti,abb-v2";
1104                         regulator-name = "abb_mm";
1105                         #address-cells = <0>;
1106                         #size-cells = <0>;
1107                         clocks = <&sys_clkin>;
1108                         ti,settling-time = <50>;
1109                         ti,clock-cycles = <16>;
1110
1111                         reg = <0x4ae07ce4 0x8>, <0x4ae06010 0x4>,
1112                               <0x4a0021a4 0x8>, <0x4ae0c314 0x4>;
1113                         reg-names = "base-address", "int-address",
1114                                     "efuse-address", "ldo-address";
1115                         ti,tranxdone-status-mask = <0x80000000>;
1116                         /* LDOVBBMM_MUX_CTRL */
1117                         ti,ldovbb-override-mask = <0x400>;
1118                         /* LDOVBBMM_VSET_OUT */
1119                         ti,ldovbb-vset-mask = <0x1F>;
1120
1121                         /*
1122                          * NOTE: only FBB mode used but actual vset will
1123                          * determine final biasing
1124                          */
1125                         ti,abb_info = <
1126                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
1127                         1025000         0       0x0     0 0x02000000 0x01F00000
1128                         1120000         0       0x4     0 0x02000000 0x01F00000
1129                         >;
1130                 };
1131         };
1132 };
1133
1134 &cpu_thermal {
1135         polling-delay = <500>; /* milliseconds */
1136         coefficients = <65 (-1791)>;
1137 };
1138
1139 /include/ "omap54xx-clocks.dtsi"
1140
1141 &gpu_thermal {
1142         coefficients = <117 (-2992)>;
1143 };
1144
1145 &core_thermal {
1146         coefficients = <0 2000>;
1147 };