2 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 * Based on "omap4.dtsi"
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/pinctrl/omap.h>
18 compatible = "ti,omap5";
19 interrupt-parent = <&wakeupgen>;
47 compatible = "arm,cortex-a15";
56 clocks = <&dpll_mpu_ck>;
59 clock-latency = <300000>; /* From omap-cpufreq driver */
62 cooling-min-level = <0>;
63 cooling-max-level = <2>;
64 #cooling-cells = <2>; /* min followed by max */
68 compatible = "arm,cortex-a15";
74 #include "omap4-cpu-thermal.dtsi"
75 #include "omap5-gpu-thermal.dtsi"
76 #include "omap5-core-thermal.dtsi"
80 compatible = "arm,armv7-timer";
81 /* PPI secure/nonsecure IRQ */
82 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
83 <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
84 <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
85 <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>;
86 interrupt-parent = <&gic>;
90 compatible = "arm,cortex-a15-pmu";
91 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
92 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
95 gic: interrupt-controller@48211000 {
96 compatible = "arm,cortex-a15-gic";
98 #interrupt-cells = <3>;
99 reg = <0 0x48211000 0 0x1000>,
100 <0 0x48212000 0 0x1000>,
101 <0 0x48214000 0 0x2000>,
102 <0 0x48216000 0 0x2000>;
103 interrupt-parent = <&gic>;
106 wakeupgen: interrupt-controller@48281000 {
107 compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
108 interrupt-controller;
109 #interrupt-cells = <3>;
110 reg = <0 0x48281000 0 0x1000>;
111 interrupt-parent = <&gic>;
115 * The soc node represents the soc top level view. It is used for IPs
116 * that are not memory mapped in the MPU view or for the MPU itself.
119 compatible = "ti,omap-infra";
121 compatible = "ti,omap4-mpu";
128 * XXX: Use a flat representation of the OMAP3 interconnect.
129 * The real OMAP interconnect network is quite complex.
130 * Since it will not bring real advantage to represent that in DT for
131 * the moment, just use a fake OCP bus entry to represent the whole bus
135 compatible = "ti,omap5-l3-noc", "simple-bus";
136 #address-cells = <1>;
138 ranges = <0 0 0 0xc0000000>;
139 dma-ranges = <0x80000000 0x0 0x80000000 0x80000000>;
140 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
141 reg = <0 0x44000000 0 0x2000>,
142 <0 0x44800000 0 0x3000>,
143 <0 0x45000000 0 0x4000>;
144 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
145 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
147 l4_cfg: l4@4a000000 {
148 compatible = "ti,omap5-l4-cfg", "simple-bus";
149 #address-cells = <1>;
151 ranges = <0 0x4a000000 0x22a000>;
154 compatible = "ti,omap5-scm-core", "simple-bus";
155 reg = <0x2000 0x1000>;
156 #address-cells = <1>;
158 ranges = <0 0x2000 0x800>;
160 scm_conf: scm_conf@0 {
161 compatible = "syscon";
163 #address-cells = <1>;
168 scm_padconf_core: scm@2800 {
169 compatible = "ti,omap5-scm-padconf-core",
171 #address-cells = <1>;
173 ranges = <0 0x2800 0x800>;
175 omap5_pmx_core: pinmux@40 {
176 compatible = "ti,omap5-padconf",
179 #address-cells = <1>;
181 #interrupt-cells = <1>;
182 interrupt-controller;
183 pinctrl-single,register-width = <16>;
184 pinctrl-single,function-mask = <0x7fff>;
187 omap5_padconf_global: omap5_padconf_global@5a0 {
188 compatible = "syscon",
191 #address-cells = <1>;
193 ranges = <0 0x5a0 0xec>;
195 pbias_regulator: pbias_regulator@60 {
196 compatible = "ti,pbias-omap5", "ti,pbias-omap";
198 syscon = <&omap5_padconf_global>;
199 pbias_mmc_reg: pbias_mmc_omap5 {
200 regulator-name = "pbias_mmc_omap5";
201 regulator-min-microvolt = <1800000>;
202 regulator-max-microvolt = <3000000>;
208 cm_core_aon: cm_core_aon@4000 {
209 compatible = "ti,omap5-cm-core-aon";
210 reg = <0x4000 0x2000>;
212 cm_core_aon_clocks: clocks {
213 #address-cells = <1>;
217 cm_core_aon_clockdomains: clockdomains {
221 cm_core: cm_core@8000 {
222 compatible = "ti,omap5-cm-core";
223 reg = <0x8000 0x3000>;
225 cm_core_clocks: clocks {
226 #address-cells = <1>;
230 cm_core_clockdomains: clockdomains {
235 l4_wkup: l4@4ae00000 {
236 compatible = "ti,omap5-l4-wkup", "simple-bus";
237 #address-cells = <1>;
239 ranges = <0 0x4ae00000 0x2b000>;
241 counter32k: counter@4000 {
242 compatible = "ti,omap-counter32k";
244 ti,hwmods = "counter_32k";
248 compatible = "ti,omap5-prm";
249 reg = <0x6000 0x3000>;
250 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
253 #address-cells = <1>;
257 prm_clockdomains: clockdomains {
262 compatible = "ti,omap5-scrm";
263 reg = <0xa000 0x2000>;
265 scrm_clocks: clocks {
266 #address-cells = <1>;
270 scrm_clockdomains: clockdomains {
274 omap5_pmx_wkup: pinmux@c840 {
275 compatible = "ti,omap5-padconf",
277 reg = <0xc840 0x003c>;
278 #address-cells = <1>;
280 #interrupt-cells = <1>;
281 interrupt-controller;
282 pinctrl-single,register-width = <16>;
283 pinctrl-single,function-mask = <0x7fff>;
287 ocmcram: ocmcram@40300000 {
288 compatible = "mmio-sram";
289 reg = <0x40300000 0x20000>; /* 128k */
292 sdma: dma-controller@4a056000 {
293 compatible = "ti,omap4430-sdma";
294 reg = <0x4a056000 0x1000>;
295 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
296 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
297 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
298 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
301 dma-requests = <127>;
304 gpio1: gpio@4ae10000 {
305 compatible = "ti,omap4-gpio";
306 reg = <0x4ae10000 0x200>;
307 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
312 interrupt-controller;
313 #interrupt-cells = <2>;
316 gpio2: gpio@48055000 {
317 compatible = "ti,omap4-gpio";
318 reg = <0x48055000 0x200>;
319 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
323 interrupt-controller;
324 #interrupt-cells = <2>;
327 gpio3: gpio@48057000 {
328 compatible = "ti,omap4-gpio";
329 reg = <0x48057000 0x200>;
330 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
334 interrupt-controller;
335 #interrupt-cells = <2>;
338 gpio4: gpio@48059000 {
339 compatible = "ti,omap4-gpio";
340 reg = <0x48059000 0x200>;
341 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
345 interrupt-controller;
346 #interrupt-cells = <2>;
349 gpio5: gpio@4805b000 {
350 compatible = "ti,omap4-gpio";
351 reg = <0x4805b000 0x200>;
352 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
356 interrupt-controller;
357 #interrupt-cells = <2>;
360 gpio6: gpio@4805d000 {
361 compatible = "ti,omap4-gpio";
362 reg = <0x4805d000 0x200>;
363 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
367 interrupt-controller;
368 #interrupt-cells = <2>;
371 gpio7: gpio@48051000 {
372 compatible = "ti,omap4-gpio";
373 reg = <0x48051000 0x200>;
374 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
378 interrupt-controller;
379 #interrupt-cells = <2>;
382 gpio8: gpio@48053000 {
383 compatible = "ti,omap4-gpio";
384 reg = <0x48053000 0x200>;
385 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
389 interrupt-controller;
390 #interrupt-cells = <2>;
393 gpmc: gpmc@50000000 {
394 compatible = "ti,omap4430-gpmc";
395 reg = <0x50000000 0x1000>;
396 #address-cells = <2>;
398 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
402 gpmc,num-waitpins = <4>;
404 clocks = <&l3_iclk_div>;
406 interrupt-controller;
407 #interrupt-cells = <2>;
413 compatible = "ti,omap4-i2c";
414 reg = <0x48070000 0x100>;
415 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
416 #address-cells = <1>;
422 compatible = "ti,omap4-i2c";
423 reg = <0x48072000 0x100>;
424 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
425 #address-cells = <1>;
431 compatible = "ti,omap4-i2c";
432 reg = <0x48060000 0x100>;
433 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
434 #address-cells = <1>;
440 compatible = "ti,omap4-i2c";
441 reg = <0x4807a000 0x100>;
442 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
443 #address-cells = <1>;
449 compatible = "ti,omap4-i2c";
450 reg = <0x4807c000 0x100>;
451 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
452 #address-cells = <1>;
457 hwspinlock: spinlock@4a0f6000 {
458 compatible = "ti,omap4-hwspinlock";
459 reg = <0x4a0f6000 0x1000>;
460 ti,hwmods = "spinlock";
464 mcspi1: spi@48098000 {
465 compatible = "ti,omap4-mcspi";
466 reg = <0x48098000 0x200>;
467 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
468 #address-cells = <1>;
470 ti,hwmods = "mcspi1";
480 dma-names = "tx0", "rx0", "tx1", "rx1",
481 "tx2", "rx2", "tx3", "rx3";
484 mcspi2: spi@4809a000 {
485 compatible = "ti,omap4-mcspi";
486 reg = <0x4809a000 0x200>;
487 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
488 #address-cells = <1>;
490 ti,hwmods = "mcspi2";
496 dma-names = "tx0", "rx0", "tx1", "rx1";
499 mcspi3: spi@480b8000 {
500 compatible = "ti,omap4-mcspi";
501 reg = <0x480b8000 0x200>;
502 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
503 #address-cells = <1>;
505 ti,hwmods = "mcspi3";
507 dmas = <&sdma 15>, <&sdma 16>;
508 dma-names = "tx0", "rx0";
511 mcspi4: spi@480ba000 {
512 compatible = "ti,omap4-mcspi";
513 reg = <0x480ba000 0x200>;
514 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
515 #address-cells = <1>;
517 ti,hwmods = "mcspi4";
519 dmas = <&sdma 70>, <&sdma 71>;
520 dma-names = "tx0", "rx0";
523 uart1: serial@4806a000 {
524 compatible = "ti,omap4-uart";
525 reg = <0x4806a000 0x100>;
526 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
528 clock-frequency = <48000000>;
531 uart2: serial@4806c000 {
532 compatible = "ti,omap4-uart";
533 reg = <0x4806c000 0x100>;
534 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
536 clock-frequency = <48000000>;
539 uart3: serial@48020000 {
540 compatible = "ti,omap4-uart";
541 reg = <0x48020000 0x100>;
542 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
544 clock-frequency = <48000000>;
547 uart4: serial@4806e000 {
548 compatible = "ti,omap4-uart";
549 reg = <0x4806e000 0x100>;
550 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
552 clock-frequency = <48000000>;
555 uart5: serial@48066000 {
556 compatible = "ti,omap4-uart";
557 reg = <0x48066000 0x100>;
558 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
560 clock-frequency = <48000000>;
563 uart6: serial@48068000 {
564 compatible = "ti,omap4-uart";
565 reg = <0x48068000 0x100>;
566 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
568 clock-frequency = <48000000>;
572 compatible = "ti,omap4-hsmmc";
573 reg = <0x4809c000 0x400>;
574 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
577 ti,needs-special-reset;
578 dmas = <&sdma 61>, <&sdma 62>;
579 dma-names = "tx", "rx";
580 pbias-supply = <&pbias_mmc_reg>;
584 compatible = "ti,omap4-hsmmc";
585 reg = <0x480b4000 0x400>;
586 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
588 ti,needs-special-reset;
589 dmas = <&sdma 47>, <&sdma 48>;
590 dma-names = "tx", "rx";
594 compatible = "ti,omap4-hsmmc";
595 reg = <0x480ad000 0x400>;
596 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
598 ti,needs-special-reset;
599 dmas = <&sdma 77>, <&sdma 78>;
600 dma-names = "tx", "rx";
604 compatible = "ti,omap4-hsmmc";
605 reg = <0x480d1000 0x400>;
606 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
608 ti,needs-special-reset;
609 dmas = <&sdma 57>, <&sdma 58>;
610 dma-names = "tx", "rx";
614 compatible = "ti,omap4-hsmmc";
615 reg = <0x480d5000 0x400>;
616 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
618 ti,needs-special-reset;
619 dmas = <&sdma 59>, <&sdma 60>;
620 dma-names = "tx", "rx";
623 mmu_dsp: mmu@4a066000 {
624 compatible = "ti,omap4-iommu";
625 reg = <0x4a066000 0x100>;
626 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
627 ti,hwmods = "mmu_dsp";
631 mmu_ipu: mmu@55082000 {
632 compatible = "ti,omap4-iommu";
633 reg = <0x55082000 0x100>;
634 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
635 ti,hwmods = "mmu_ipu";
637 ti,iommu-bus-err-back;
640 keypad: keypad@4ae1c000 {
641 compatible = "ti,omap4-keypad";
642 reg = <0x4ae1c000 0x400>;
646 mcpdm: mcpdm@40132000 {
647 compatible = "ti,omap4-mcpdm";
648 reg = <0x40132000 0x7f>, /* MPU private access */
649 <0x49032000 0x7f>; /* L3 Interconnect */
650 reg-names = "mpu", "dma";
651 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
655 dma-names = "up_link", "dn_link";
659 dmic: dmic@4012e000 {
660 compatible = "ti,omap4-dmic";
661 reg = <0x4012e000 0x7f>, /* MPU private access */
662 <0x4902e000 0x7f>; /* L3 Interconnect */
663 reg-names = "mpu", "dma";
664 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
667 dma-names = "up_link";
671 mcbsp1: mcbsp@40122000 {
672 compatible = "ti,omap4-mcbsp";
673 reg = <0x40122000 0xff>, /* MPU private access */
674 <0x49022000 0xff>; /* L3 Interconnect */
675 reg-names = "mpu", "dma";
676 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
677 interrupt-names = "common";
678 ti,buffer-size = <128>;
679 ti,hwmods = "mcbsp1";
682 dma-names = "tx", "rx";
686 mcbsp2: mcbsp@40124000 {
687 compatible = "ti,omap4-mcbsp";
688 reg = <0x40124000 0xff>, /* MPU private access */
689 <0x49024000 0xff>; /* L3 Interconnect */
690 reg-names = "mpu", "dma";
691 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
692 interrupt-names = "common";
693 ti,buffer-size = <128>;
694 ti,hwmods = "mcbsp2";
697 dma-names = "tx", "rx";
701 mcbsp3: mcbsp@40126000 {
702 compatible = "ti,omap4-mcbsp";
703 reg = <0x40126000 0xff>, /* MPU private access */
704 <0x49026000 0xff>; /* L3 Interconnect */
705 reg-names = "mpu", "dma";
706 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
707 interrupt-names = "common";
708 ti,buffer-size = <128>;
709 ti,hwmods = "mcbsp3";
712 dma-names = "tx", "rx";
716 mailbox: mailbox@4a0f4000 {
717 compatible = "ti,omap4-mailbox";
718 reg = <0x4a0f4000 0x200>;
719 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
720 ti,hwmods = "mailbox";
722 ti,mbox-num-users = <3>;
723 ti,mbox-num-fifos = <8>;
725 ti,mbox-tx = <0 0 0>;
726 ti,mbox-rx = <1 0 0>;
729 ti,mbox-tx = <3 0 0>;
730 ti,mbox-rx = <2 0 0>;
734 timer1: timer@4ae18000 {
735 compatible = "ti,omap5430-timer";
736 reg = <0x4ae18000 0x80>;
737 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
738 ti,hwmods = "timer1";
742 timer2: timer@48032000 {
743 compatible = "ti,omap5430-timer";
744 reg = <0x48032000 0x80>;
745 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
746 ti,hwmods = "timer2";
749 timer3: timer@48034000 {
750 compatible = "ti,omap5430-timer";
751 reg = <0x48034000 0x80>;
752 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
753 ti,hwmods = "timer3";
756 timer4: timer@48036000 {
757 compatible = "ti,omap5430-timer";
758 reg = <0x48036000 0x80>;
759 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
760 ti,hwmods = "timer4";
763 timer5: timer@40138000 {
764 compatible = "ti,omap5430-timer";
765 reg = <0x40138000 0x80>,
767 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
768 ti,hwmods = "timer5";
773 timer6: timer@4013a000 {
774 compatible = "ti,omap5430-timer";
775 reg = <0x4013a000 0x80>,
777 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
778 ti,hwmods = "timer6";
783 timer7: timer@4013c000 {
784 compatible = "ti,omap5430-timer";
785 reg = <0x4013c000 0x80>,
787 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
788 ti,hwmods = "timer7";
792 timer8: timer@4013e000 {
793 compatible = "ti,omap5430-timer";
794 reg = <0x4013e000 0x80>,
796 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
797 ti,hwmods = "timer8";
802 timer9: timer@4803e000 {
803 compatible = "ti,omap5430-timer";
804 reg = <0x4803e000 0x80>;
805 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
806 ti,hwmods = "timer9";
810 timer10: timer@48086000 {
811 compatible = "ti,omap5430-timer";
812 reg = <0x48086000 0x80>;
813 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
814 ti,hwmods = "timer10";
818 timer11: timer@48088000 {
819 compatible = "ti,omap5430-timer";
820 reg = <0x48088000 0x80>;
821 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
822 ti,hwmods = "timer11";
827 compatible = "ti,omap5-wdt", "ti,omap3-wdt";
828 reg = <0x4ae14000 0x80>;
829 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
830 ti,hwmods = "wd_timer2";
834 compatible = "ti,omap5-dmm";
835 reg = <0x4e000000 0x800>;
836 interrupts = <0 113 0x4>;
840 emif1: emif@4c000000 {
841 compatible = "ti,emif-4d5";
844 phy-type = <2>; /* DDR PHY type: Intelli PHY */
845 reg = <0x4c000000 0x400>;
846 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
847 hw-caps-read-idle-ctrl;
848 hw-caps-ll-interface;
852 emif2: emif@4d000000 {
853 compatible = "ti,emif-4d5";
856 phy-type = <2>; /* DDR PHY type: Intelli PHY */
857 reg = <0x4d000000 0x400>;
858 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
859 hw-caps-read-idle-ctrl;
860 hw-caps-ll-interface;
864 usb3: omap_dwc3@4a020000 {
865 compatible = "ti,dwc3";
866 ti,hwmods = "usb_otg_ss";
867 reg = <0x4a020000 0x10000>;
868 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
869 #address-cells = <1>;
873 dwc3: dwc3@4a030000 {
874 compatible = "snps,dwc3";
875 reg = <0x4a030000 0x10000>;
876 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
877 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
878 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
879 interrupt-names = "peripheral",
882 phys = <&usb2_phy>, <&usb3_phy>;
883 phy-names = "usb2-phy", "usb3-phy";
884 dr_mode = "peripheral";
889 compatible = "ti,omap-ocp2scp";
890 #address-cells = <1>;
892 reg = <0x4a080000 0x20>;
894 ti,hwmods = "ocp2scp1";
895 usb2_phy: usb2phy@4a084000 {
896 compatible = "ti,omap-usb2";
897 reg = <0x4a084000 0x7c>;
898 syscon-phy-power = <&scm_conf 0x300>;
899 clocks = <&usb_phy_cm_clk32k>, <&usb_otg_ss_refclk960m>;
900 clock-names = "wkupclk", "refclk";
904 usb3_phy: usb3phy@4a084400 {
905 compatible = "ti,omap-usb3";
906 reg = <0x4a084400 0x80>,
909 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
910 syscon-phy-power = <&scm_conf 0x370>;
911 clocks = <&usb_phy_cm_clk32k>,
913 <&usb_otg_ss_refclk960m>;
914 clock-names = "wkupclk",
921 usbhstll: usbhstll@4a062000 {
922 compatible = "ti,usbhs-tll";
923 reg = <0x4a062000 0x1000>;
924 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
925 ti,hwmods = "usb_tll_hs";
928 usbhshost: usbhshost@4a064000 {
929 compatible = "ti,usbhs-host";
930 reg = <0x4a064000 0x800>;
931 ti,hwmods = "usb_host_hs";
932 #address-cells = <1>;
935 clocks = <&l3init_60m_fclk>,
938 clock-names = "refclk_60m_int",
942 usbhsohci: ohci@4a064800 {
943 compatible = "ti,ohci-omap3";
944 reg = <0x4a064800 0x400>;
945 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
948 usbhsehci: ehci@4a064c00 {
949 compatible = "ti,ehci-omap";
950 reg = <0x4a064c00 0x400>;
951 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
955 bandgap: bandgap@4a0021e0 {
956 reg = <0x4a0021e0 0xc
960 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
961 compatible = "ti,omap5430-bandgap";
963 #thermal-sensor-cells = <1>;
968 compatible = "ti,omap-ocp2scp";
969 #address-cells = <1>;
971 reg = <0x4a090000 0x20>;
973 ti,hwmods = "ocp2scp3";
974 sata_phy: phy@4a096000 {
975 compatible = "ti,phy-pipe3-sata";
976 reg = <0x4A096000 0x80>, /* phy_rx */
977 <0x4A096400 0x64>, /* phy_tx */
978 <0x4A096800 0x40>; /* pll_ctrl */
979 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
980 syscon-phy-power = <&scm_conf 0x374>;
981 clocks = <&sys_clkin>, <&sata_ref_clk>;
982 clock-names = "sysclk", "refclk";
987 sata: sata@4a141100 {
988 compatible = "snps,dwc-ahci";
989 reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
990 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
992 phy-names = "sata-phy";
993 clocks = <&sata_ref_clk>;
995 ports-implemented = <0x1>;
999 compatible = "ti,omap5-dss";
1000 reg = <0x58000000 0x80>;
1001 status = "disabled";
1002 ti,hwmods = "dss_core";
1003 clocks = <&dss_dss_clk>;
1004 clock-names = "fck";
1005 #address-cells = <1>;
1010 compatible = "ti,omap5-dispc";
1011 reg = <0x58001000 0x1000>;
1012 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1013 ti,hwmods = "dss_dispc";
1014 clocks = <&dss_dss_clk>;
1015 clock-names = "fck";
1018 rfbi: encoder@58002000 {
1019 compatible = "ti,omap5-rfbi";
1020 reg = <0x58002000 0x100>;
1021 status = "disabled";
1022 ti,hwmods = "dss_rfbi";
1023 clocks = <&dss_dss_clk>, <&l3_iclk_div>;
1024 clock-names = "fck", "ick";
1027 dsi1: encoder@58004000 {
1028 compatible = "ti,omap5-dsi";
1029 reg = <0x58004000 0x200>,
1032 reg-names = "proto", "phy", "pll";
1033 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1034 status = "disabled";
1035 ti,hwmods = "dss_dsi1";
1036 clocks = <&dss_dss_clk>, <&dss_sys_clk>;
1037 clock-names = "fck", "sys_clk";
1040 dsi2: encoder@58005000 {
1041 compatible = "ti,omap5-dsi";
1042 reg = <0x58009000 0x200>,
1045 reg-names = "proto", "phy", "pll";
1046 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
1047 status = "disabled";
1048 ti,hwmods = "dss_dsi2";
1049 clocks = <&dss_dss_clk>, <&dss_sys_clk>;
1050 clock-names = "fck", "sys_clk";
1053 hdmi: encoder@58060000 {
1054 compatible = "ti,omap5-hdmi";
1055 reg = <0x58040000 0x200>,
1058 <0x58060000 0x19000>;
1059 reg-names = "wp", "pll", "phy", "core";
1060 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1061 status = "disabled";
1062 ti,hwmods = "dss_hdmi";
1063 clocks = <&dss_48mhz_clk>, <&dss_sys_clk>;
1064 clock-names = "fck", "sys_clk";
1066 dma-names = "audio_tx";
1070 abb_mpu: regulator-abb-mpu {
1071 compatible = "ti,abb-v2";
1072 regulator-name = "abb_mpu";
1073 #address-cells = <0>;
1075 clocks = <&sys_clkin>;
1076 ti,settling-time = <50>;
1077 ti,clock-cycles = <16>;
1079 reg = <0x4ae07cdc 0x8>, <0x4ae06014 0x4>,
1080 <0x4a0021c4 0x8>, <0x4ae0c318 0x4>;
1081 reg-names = "base-address", "int-address",
1082 "efuse-address", "ldo-address";
1083 ti,tranxdone-status-mask = <0x80>;
1084 /* LDOVBBMPU_MUX_CTRL */
1085 ti,ldovbb-override-mask = <0x400>;
1086 /* LDOVBBMPU_VSET_OUT */
1087 ti,ldovbb-vset-mask = <0x1F>;
1090 * NOTE: only FBB mode used but actual vset will
1091 * determine final biasing
1094 /*uV ABB efuse rbb_m fbb_m vset_m*/
1095 1060000 0 0x0 0 0x02000000 0x01F00000
1096 1250000 0 0x4 0 0x02000000 0x01F00000
1100 abb_mm: regulator-abb-mm {
1101 compatible = "ti,abb-v2";
1102 regulator-name = "abb_mm";
1103 #address-cells = <0>;
1105 clocks = <&sys_clkin>;
1106 ti,settling-time = <50>;
1107 ti,clock-cycles = <16>;
1109 reg = <0x4ae07ce4 0x8>, <0x4ae06010 0x4>,
1110 <0x4a0021a4 0x8>, <0x4ae0c314 0x4>;
1111 reg-names = "base-address", "int-address",
1112 "efuse-address", "ldo-address";
1113 ti,tranxdone-status-mask = <0x80000000>;
1114 /* LDOVBBMM_MUX_CTRL */
1115 ti,ldovbb-override-mask = <0x400>;
1116 /* LDOVBBMM_VSET_OUT */
1117 ti,ldovbb-vset-mask = <0x1F>;
1120 * NOTE: only FBB mode used but actual vset will
1121 * determine final biasing
1124 /*uV ABB efuse rbb_m fbb_m vset_m*/
1125 1025000 0 0x0 0 0x02000000 0x01F00000
1126 1120000 0 0x4 0 0x02000000 0x01F00000
1133 polling-delay = <500>; /* milliseconds */
1136 /include/ "omap54xx-clocks.dtsi"