arch/arm/boot/dts/omap5.dtsi

   1 /*
   2  * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  * Based on "omap4.dtsi"
   8  */
   9
  10 #include <dt-bindings/gpio/gpio.h>
  11 #include <dt-bindings/interrupt-controller/arm-gic.h>
  12 #include <dt-bindings/pinctrl/omap.h>
  13
  14 / {
  15         #address-cells = <2>;
  16         #size-cells = <2>;
  17
  18         compatible = "ti,omap5";
  19         interrupt-parent = <&wakeupgen>;
  20         chosen { };
  21
  22         aliases {
  23                 i2c0 = &i2c1;
  24                 i2c1 = &i2c2;
  25                 i2c2 = &i2c3;
  26                 i2c3 = &i2c4;
  27                 i2c4 = &i2c5;
  28                 mmc0 = &mmc1;
  29                 mmc1 = &mmc2;
  30                 mmc2 = &mmc3;
  31                 mmc3 = &mmc4;
  32                 mmc4 = &mmc5;
  33                 serial0 = &uart1;
  34                 serial1 = &uart2;
  35                 serial2 = &uart3;
  36                 serial3 = &uart4;
  37                 serial4 = &uart5;
  38                 serial5 = &uart6;
  39         };
  40
  41         cpus {
  42                 #address-cells = <1>;
  43                 #size-cells = <0>;
  44
  45                 cpu0: cpu@0 {
  46                         device_type = "cpu";
  47                         compatible = "arm,cortex-a15";
  48                         reg = <0x0>;
  49
  50                         operating-points = <
  51                                 /* kHz    uV */
  52                                 1000000 1060000
  53                                 1500000 1250000
  54                         >;
  55
  56                         clocks = <&dpll_mpu_ck>;
  57                         clock-names = "cpu";
  58
  59                         clock-latency = <300000>; /* From omap-cpufreq driver */
  60
  61                         /* cooling options */
  62                         cooling-min-level = <0>;
  63                         cooling-max-level = <2>;
  64                         #cooling-cells = <2>; /* min followed by max */
  65                 };
  66                 cpu@1 {
  67                         device_type = "cpu";
  68                         compatible = "arm,cortex-a15";
  69                         reg = <0x1>;
  70                 };
  71         };
  72
  73         thermal-zones {
  74                 #include "omap4-cpu-thermal.dtsi"
  75                 #include "omap5-gpu-thermal.dtsi"
  76                 #include "omap5-core-thermal.dtsi"
  77         };
  78
  79         timer {
  80                 compatible = "arm,armv7-timer";
  81                 /* PPI secure/nonsecure IRQ */
  82                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
  83                              <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
  84                              <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
  85                              <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>;
  86                 interrupt-parent = <&gic>;
  87         };
  88
  89         pmu {
  90                 compatible = "arm,cortex-a15-pmu";
  91                 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
  92                              <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
  93         };
  94
  95         gic: interrupt-controller@48211000 {
  96                 compatible = "arm,cortex-a15-gic";
  97                 interrupt-controller;
  98                 #interrupt-cells = <3>;
  99                 reg = <0 0x48211000 0 0x1000>,
 100                       <0 0x48212000 0 0x1000>,
 101                       <0 0x48214000 0 0x2000>,
 102                       <0 0x48216000 0 0x2000>;
 103                 interrupt-parent = <&gic>;
 104         };
 105
 106         wakeupgen: interrupt-controller@48281000 {
 107                 compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
 108                 interrupt-controller;
 109                 #interrupt-cells = <3>;
 110                 reg = <0 0x48281000 0 0x1000>;
 111                 interrupt-parent = <&gic>;
 112         };
 113
 114         /*
 115          * The soc node represents the soc top level view. It is used for IPs
 116          * that are not memory mapped in the MPU view or for the MPU itself.
 117          */
 118         soc {
 119                 compatible = "ti,omap-infra";
 120                 mpu {
 121                         compatible = "ti,omap4-mpu";
 122                         ti,hwmods = "mpu";
 123                         sram = <&ocmcram>;
 124                 };
 125         };
 126
 127         /*
 128          * XXX: Use a flat representation of the OMAP3 interconnect.
 129          * The real OMAP interconnect network is quite complex.
 130          * Since it will not bring real advantage to represent that in DT for
 131          * the moment, just use a fake OCP bus entry to represent the whole bus
 132          * hierarchy.
 133          */
 134         ocp {
 135                 compatible = "ti,omap5-l3-noc", "simple-bus";
 136                 #address-cells = <1>;
 137                 #size-cells = <1>;
 138                 ranges = <0 0 0 0xc0000000>;
 139                 dma-ranges = <0x80000000 0x0 0x80000000 0x80000000>;
 140                 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
 141                 reg = <0 0x44000000 0 0x2000>,
 142                       <0 0x44800000 0 0x3000>,
 143                       <0 0x45000000 0 0x4000>;
 144                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
 145                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 146
 147                 l4_cfg: l4@4a000000 {
 148                         compatible = "ti,omap5-l4-cfg", "simple-bus";
 149                         #address-cells = <1>;
 150                         #size-cells = <1>;
 151                         ranges = <0 0x4a000000 0x22a000>;
 152
 153                         scm_core: scm@2000 {
 154                                 compatible = "ti,omap5-scm-core", "simple-bus";
 155                                 reg = <0x2000 0x1000>;
 156                                 #address-cells = <1>;
 157                                 #size-cells = <1>;
 158                                 ranges = <0 0x2000 0x800>;
 159
 160                                 scm_conf: scm_conf@0 {
 161                                         compatible = "syscon";
 162                                         reg = <0x0 0x800>;
 163                                         #address-cells = <1>;
 164                                         #size-cells = <1>;
 165                                 };
 166                         };
 167
 168                         scm_padconf_core: scm@2800 {
 169                                 compatible = "ti,omap5-scm-padconf-core",
 170                                              "simple-bus";
 171                                 #address-cells = <1>;
 172                                 #size-cells = <1>;
 173                                 ranges = <0 0x2800 0x800>;
 174
 175                                 omap5_pmx_core: pinmux@40 {
 176                                         compatible = "ti,omap5-padconf",
 177                                                      "pinctrl-single";
 178                                         reg = <0x40 0x01b6>;
 179                                         #address-cells = <1>;
 180                                         #size-cells = <0>;
 181                                         #interrupt-cells = <1>;
 182                                         interrupt-controller;
 183                                         pinctrl-single,register-width = <16>;
 184                                         pinctrl-single,function-mask = <0x7fff>;
 185                                 };
 186
 187                                 omap5_padconf_global: omap5_padconf_global@5a0 {
 188                                         compatible = "syscon",
 189                                                      "simple-bus";
 190                                         reg = <0x5a0 0xec>;
 191                                         #address-cells = <1>;
 192                                         #size-cells = <1>;
 193                                         ranges = <0 0x5a0 0xec>;
 194
 195                                         pbias_regulator: pbias_regulator@60 {
 196                                                 compatible = "ti,pbias-omap5", "ti,pbias-omap";
 197                                                 reg = <0x60 0x4>;
 198                                                 syscon = <&omap5_padconf_global>;
 199                                                 pbias_mmc_reg: pbias_mmc_omap5 {
 200                                                         regulator-name = "pbias_mmc_omap5";
 201                                                         regulator-min-microvolt = <1800000>;
 202                                                         regulator-max-microvolt = <3000000>;
 203                                                 };
 204                                         };
 205                                 };
 206                         };
 207
 208                         cm_core_aon: cm_core_aon@4000 {
 209                                 compatible = "ti,omap5-cm-core-aon";
 210                                 reg = <0x4000 0x2000>;
 211
 212                                 cm_core_aon_clocks: clocks {
 213                                         #address-cells = <1>;
 214                                         #size-cells = <0>;
 215                                 };
 216
 217                                 cm_core_aon_clockdomains: clockdomains {
 218                                 };
 219                         };
 220
 221                         cm_core: cm_core@8000 {
 222                                 compatible = "ti,omap5-cm-core";
 223                                 reg = <0x8000 0x3000>;
 224
 225                                 cm_core_clocks: clocks {
 226                                         #address-cells = <1>;
 227                                         #size-cells = <0>;
 228                                 };
 229
 230                                 cm_core_clockdomains: clockdomains {
 231                                 };
 232                         };
 233                 };
 234
 235                 l4_wkup: l4@4ae00000 {
 236                         compatible = "ti,omap5-l4-wkup", "simple-bus";
 237                         #address-cells = <1>;
 238                         #size-cells = <1>;
 239                         ranges = <0 0x4ae00000 0x2b000>;
 240
 241                         counter32k: counter@4000 {
 242                                 compatible = "ti,omap-counter32k";
 243                                 reg = <0x4000 0x40>;
 244                                 ti,hwmods = "counter_32k";
 245                         };
 246
 247                         prm: prm@6000 {
 248                                 compatible = "ti,omap5-prm";
 249                                 reg = <0x6000 0x3000>;
 250                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 251
 252                                 prm_clocks: clocks {
 253                                         #address-cells = <1>;
 254                                         #size-cells = <0>;
 255                                 };
 256
 257                                 prm_clockdomains: clockdomains {
 258                                 };
 259                         };
 260
 261                         scrm: scrm@a000 {
 262                                 compatible = "ti,omap5-scrm";
 263                                 reg = <0xa000 0x2000>;
 264
 265                                 scrm_clocks: clocks {
 266                                         #address-cells = <1>;
 267                                         #size-cells = <0>;
 268                                 };
 269
 270                                 scrm_clockdomains: clockdomains {
 271                                 };
 272                         };
 273
 274                         omap5_pmx_wkup: pinmux@c840 {
 275                                 compatible = "ti,omap5-padconf",
 276                                              "pinctrl-single";
 277                                 reg = <0xc840 0x003c>;
 278                                 #address-cells = <1>;
 279                                 #size-cells = <0>;
 280                                 #interrupt-cells = <1>;
 281                                 interrupt-controller;
 282                                 pinctrl-single,register-width = <16>;
 283                                 pinctrl-single,function-mask = <0x7fff>;
 284                         };
 285                 };
 286
 287                 ocmcram: ocmcram@40300000 {
 288                         compatible = "mmio-sram";
 289                         reg = <0x40300000 0x20000>; /* 128k */
 290                 };
 291
 292                 sdma: dma-controller@4a056000 {
 293                         compatible = "ti,omap4430-sdma";
 294                         reg = <0x4a056000 0x1000>;
 295                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
 296                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 297                                      <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
 298                                      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 299                         #dma-cells = <1>;
 300                         dma-channels = <32>;
 301                         dma-requests = <127>;
 302                 };
 303
 304                 gpio1: gpio@4ae10000 {
 305                         compatible = "ti,omap4-gpio";
 306                         reg = <0x4ae10000 0x200>;
 307                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 308                         ti,hwmods = "gpio1";
 309                         ti,gpio-always-on;
 310                         gpio-controller;
 311                         #gpio-cells = <2>;
 312                         interrupt-controller;
 313                         #interrupt-cells = <2>;
 314                 };
 315
 316                 gpio2: gpio@48055000 {
 317                         compatible = "ti,omap4-gpio";
 318                         reg = <0x48055000 0x200>;
 319                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 320                         ti,hwmods = "gpio2";
 321                         gpio-controller;
 322                         #gpio-cells = <2>;
 323                         interrupt-controller;
 324                         #interrupt-cells = <2>;
 325                 };
 326
 327                 gpio3: gpio@48057000 {
 328                         compatible = "ti,omap4-gpio";
 329                         reg = <0x48057000 0x200>;
 330                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 331                         ti,hwmods = "gpio3";
 332                         gpio-controller;
 333                         #gpio-cells = <2>;
 334                         interrupt-controller;
 335                         #interrupt-cells = <2>;
 336                 };
 337
 338                 gpio4: gpio@48059000 {
 339                         compatible = "ti,omap4-gpio";
 340                         reg = <0x48059000 0x200>;
 341                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 342                         ti,hwmods = "gpio4";
 343                         gpio-controller;
 344                         #gpio-cells = <2>;
 345                         interrupt-controller;
 346                         #interrupt-cells = <2>;
 347                 };
 348
 349                 gpio5: gpio@4805b000 {
 350                         compatible = "ti,omap4-gpio";
 351                         reg = <0x4805b000 0x200>;
 352                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 353                         ti,hwmods = "gpio5";
 354                         gpio-controller;
 355                         #gpio-cells = <2>;
 356                         interrupt-controller;
 357                         #interrupt-cells = <2>;
 358                 };
 359
 360                 gpio6: gpio@4805d000 {
 361                         compatible = "ti,omap4-gpio";
 362                         reg = <0x4805d000 0x200>;
 363                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 364                         ti,hwmods = "gpio6";
 365                         gpio-controller;
 366                         #gpio-cells = <2>;
 367                         interrupt-controller;
 368                         #interrupt-cells = <2>;
 369                 };
 370
 371                 gpio7: gpio@48051000 {
 372                         compatible = "ti,omap4-gpio";
 373                         reg = <0x48051000 0x200>;
 374                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 375                         ti,hwmods = "gpio7";
 376                         gpio-controller;
 377                         #gpio-cells = <2>;
 378                         interrupt-controller;
 379                         #interrupt-cells = <2>;
 380                 };
 381
 382                 gpio8: gpio@48053000 {
 383                         compatible = "ti,omap4-gpio";
 384                         reg = <0x48053000 0x200>;
 385                         interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 386                         ti,hwmods = "gpio8";
 387                         gpio-controller;
 388                         #gpio-cells = <2>;
 389                         interrupt-controller;
 390                         #interrupt-cells = <2>;
 391                 };
 392
 393                 gpmc: gpmc@50000000 {
 394                         compatible = "ti,omap4430-gpmc";
 395                         reg = <0x50000000 0x1000>;
 396                         #address-cells = <2>;
 397                         #size-cells = <1>;
 398                         interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 399                         dmas = <&sdma 4>;
 400                         dma-names = "rxtx";
 401                         gpmc,num-cs = <8>;
 402                         gpmc,num-waitpins = <4>;
 403                         ti,hwmods = "gpmc";
 404                         clocks = <&l3_iclk_div>;
 405                         clock-names = "fck";
 406                         interrupt-controller;
 407                         #interrupt-cells = <2>;
 408                         gpio-controller;
 409                         #gpio-cells = <2>;
 410                 };
 411
 412                 i2c1: i2c@48070000 {
 413                         compatible = "ti,omap4-i2c";
 414                         reg = <0x48070000 0x100>;
 415                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 416                         #address-cells = <1>;
 417                         #size-cells = <0>;
 418                         ti,hwmods = "i2c1";
 419                 };
 420
 421                 i2c2: i2c@48072000 {
 422                         compatible = "ti,omap4-i2c";
 423                         reg = <0x48072000 0x100>;
 424                         interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 425                         #address-cells = <1>;
 426                         #size-cells = <0>;
 427                         ti,hwmods = "i2c2";
 428                 };
 429
 430                 i2c3: i2c@48060000 {
 431                         compatible = "ti,omap4-i2c";
 432                         reg = <0x48060000 0x100>;
 433                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 434                         #address-cells = <1>;
 435                         #size-cells = <0>;
 436                         ti,hwmods = "i2c3";
 437                 };
 438
 439                 i2c4: i2c@4807a000 {
 440                         compatible = "ti,omap4-i2c";
 441                         reg = <0x4807a000 0x100>;
 442                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 443                         #address-cells = <1>;
 444                         #size-cells = <0>;
 445                         ti,hwmods = "i2c4";
 446                 };
 447
 448                 i2c5: i2c@4807c000 {
 449                         compatible = "ti,omap4-i2c";
 450                         reg = <0x4807c000 0x100>;
 451                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 452                         #address-cells = <1>;
 453                         #size-cells = <0>;
 454                         ti,hwmods = "i2c5";
 455                 };
 456
 457                 hwspinlock: spinlock@4a0f6000 {
 458                         compatible = "ti,omap4-hwspinlock";
 459                         reg = <0x4a0f6000 0x1000>;
 460                         ti,hwmods = "spinlock";
 461                         #hwlock-cells = <1>;
 462                 };
 463
 464                 mcspi1: spi@48098000 {
 465                         compatible = "ti,omap4-mcspi";
 466                         reg = <0x48098000 0x200>;
 467                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 468                         #address-cells = <1>;
 469                         #size-cells = <0>;
 470                         ti,hwmods = "mcspi1";
 471                         ti,spi-num-cs = <4>;
 472                         dmas = <&sdma 35>,
 473                                <&sdma 36>,
 474                                <&sdma 37>,
 475                                <&sdma 38>,
 476                                <&sdma 39>,
 477                                <&sdma 40>,
 478                                <&sdma 41>,
 479                                <&sdma 42>;
 480                         dma-names = "tx0", "rx0", "tx1", "rx1",
 481                                     "tx2", "rx2", "tx3", "rx3";
 482                 };
 483
 484                 mcspi2: spi@4809a000 {
 485                         compatible = "ti,omap4-mcspi";
 486                         reg = <0x4809a000 0x200>;
 487                         interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 488                         #address-cells = <1>;
 489                         #size-cells = <0>;
 490                         ti,hwmods = "mcspi2";
 491                         ti,spi-num-cs = <2>;
 492                         dmas = <&sdma 43>,
 493                                <&sdma 44>,
 494                                <&sdma 45>,
 495                                <&sdma 46>;
 496                         dma-names = "tx0", "rx0", "tx1", "rx1";
 497                 };
 498
 499                 mcspi3: spi@480b8000 {
 500                         compatible = "ti,omap4-mcspi";
 501                         reg = <0x480b8000 0x200>;
 502                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 503                         #address-cells = <1>;
 504                         #size-cells = <0>;
 505                         ti,hwmods = "mcspi3";
 506                         ti,spi-num-cs = <2>;
 507                         dmas = <&sdma 15>, <&sdma 16>;
 508                         dma-names = "tx0", "rx0";
 509                 };
 510
 511                 mcspi4: spi@480ba000 {
 512                         compatible = "ti,omap4-mcspi";
 513                         reg = <0x480ba000 0x200>;
 514                         interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 515                         #address-cells = <1>;
 516                         #size-cells = <0>;
 517                         ti,hwmods = "mcspi4";
 518                         ti,spi-num-cs = <1>;
 519                         dmas = <&sdma 70>, <&sdma 71>;
 520                         dma-names = "tx0", "rx0";
 521                 };
 522
 523                 uart1: serial@4806a000 {
 524                         compatible = "ti,omap4-uart";
 525                         reg = <0x4806a000 0x100>;
 526                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 527                         ti,hwmods = "uart1";
 528                         clock-frequency = <48000000>;
 529                 };
 530
 531                 uart2: serial@4806c000 {
 532                         compatible = "ti,omap4-uart";
 533                         reg = <0x4806c000 0x100>;
 534                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 535                         ti,hwmods = "uart2";
 536                         clock-frequency = <48000000>;
 537                 };
 538
 539                 uart3: serial@48020000 {
 540                         compatible = "ti,omap4-uart";
 541                         reg = <0x48020000 0x100>;
 542                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 543                         ti,hwmods = "uart3";
 544                         clock-frequency = <48000000>;
 545                 };
 546
 547                 uart4: serial@4806e000 {
 548                         compatible = "ti,omap4-uart";
 549                         reg = <0x4806e000 0x100>;
 550                         interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 551                         ti,hwmods = "uart4";
 552                         clock-frequency = <48000000>;
 553                 };
 554
 555                 uart5: serial@48066000 {
 556                         compatible = "ti,omap4-uart";
 557                         reg = <0x48066000 0x100>;
 558                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 559                         ti,hwmods = "uart5";
 560                         clock-frequency = <48000000>;
 561                 };
 562
 563                 uart6: serial@48068000 {
 564                         compatible = "ti,omap4-uart";
 565                         reg = <0x48068000 0x100>;
 566                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 567                         ti,hwmods = "uart6";
 568                         clock-frequency = <48000000>;
 569                 };
 570
 571                 mmc1: mmc@4809c000 {
 572                         compatible = "ti,omap4-hsmmc";
 573                         reg = <0x4809c000 0x400>;
 574                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 575                         ti,hwmods = "mmc1";
 576                         ti,dual-volt;
 577                         ti,needs-special-reset;
 578                         dmas = <&sdma 61>, <&sdma 62>;
 579                         dma-names = "tx", "rx";
 580                         pbias-supply = <&pbias_mmc_reg>;
 581                 };
 582
 583                 mmc2: mmc@480b4000 {
 584                         compatible = "ti,omap4-hsmmc";
 585                         reg = <0x480b4000 0x400>;
 586                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 587                         ti,hwmods = "mmc2";
 588                         ti,needs-special-reset;
 589                         dmas = <&sdma 47>, <&sdma 48>;
 590                         dma-names = "tx", "rx";
 591                 };
 592
 593                 mmc3: mmc@480ad000 {
 594                         compatible = "ti,omap4-hsmmc";
 595                         reg = <0x480ad000 0x400>;
 596                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 597                         ti,hwmods = "mmc3";
 598                         ti,needs-special-reset;
 599                         dmas = <&sdma 77>, <&sdma 78>;
 600                         dma-names = "tx", "rx";
 601                 };
 602
 603                 mmc4: mmc@480d1000 {
 604                         compatible = "ti,omap4-hsmmc";
 605                         reg = <0x480d1000 0x400>;
 606                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 607                         ti,hwmods = "mmc4";
 608                         ti,needs-special-reset;
 609                         dmas = <&sdma 57>, <&sdma 58>;
 610                         dma-names = "tx", "rx";
 611                 };
 612
 613                 mmc5: mmc@480d5000 {
 614                         compatible = "ti,omap4-hsmmc";
 615                         reg = <0x480d5000 0x400>;
 616                         interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 617                         ti,hwmods = "mmc5";
 618                         ti,needs-special-reset;
 619                         dmas = <&sdma 59>, <&sdma 60>;
 620                         dma-names = "tx", "rx";
 621                 };
 622
 623                 mmu_dsp: mmu@4a066000 {
 624                         compatible = "ti,omap4-iommu";
 625                         reg = <0x4a066000 0x100>;
 626                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 627                         ti,hwmods = "mmu_dsp";
 628                         #iommu-cells = <0>;
 629                 };
 630
 631                 mmu_ipu: mmu@55082000 {
 632                         compatible = "ti,omap4-iommu";
 633                         reg = <0x55082000 0x100>;
 634                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 635                         ti,hwmods = "mmu_ipu";
 636                         #iommu-cells = <0>;
 637                         ti,iommu-bus-err-back;
 638                 };
 639
 640                 keypad: keypad@4ae1c000 {
 641                         compatible = "ti,omap4-keypad";
 642                         reg = <0x4ae1c000 0x400>;
 643                         ti,hwmods = "kbd";
 644                 };
 645
 646                 mcpdm: mcpdm@40132000 {
 647                         compatible = "ti,omap4-mcpdm";
 648                         reg = <0x40132000 0x7f>, /* MPU private access */
 649                               <0x49032000 0x7f>; /* L3 Interconnect */
 650                         reg-names = "mpu", "dma";
 651                         interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
 652                         ti,hwmods = "mcpdm";
 653                         dmas = <&sdma 65>,
 654                                <&sdma 66>;
 655                         dma-names = "up_link", "dn_link";
 656                         status = "disabled";
 657                 };
 658
 659                 dmic: dmic@4012e000 {
 660                         compatible = "ti,omap4-dmic";
 661                         reg = <0x4012e000 0x7f>, /* MPU private access */
 662                               <0x4902e000 0x7f>; /* L3 Interconnect */
 663                         reg-names = "mpu", "dma";
 664                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 665                         ti,hwmods = "dmic";
 666                         dmas = <&sdma 67>;
 667                         dma-names = "up_link";
 668                         status = "disabled";
 669                 };
 670
 671                 mcbsp1: mcbsp@40122000 {
 672                         compatible = "ti,omap4-mcbsp";
 673                         reg = <0x40122000 0xff>, /* MPU private access */
 674                               <0x49022000 0xff>; /* L3 Interconnect */
 675                         reg-names = "mpu", "dma";
 676                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 677                         interrupt-names = "common";
 678                         ti,buffer-size = <128>;
 679                         ti,hwmods = "mcbsp1";
 680                         dmas = <&sdma 33>,
 681                                <&sdma 34>;
 682                         dma-names = "tx", "rx";
 683                         status = "disabled";
 684                 };
 685
 686                 mcbsp2: mcbsp@40124000 {
 687                         compatible = "ti,omap4-mcbsp";
 688                         reg = <0x40124000 0xff>, /* MPU private access */
 689                               <0x49024000 0xff>; /* L3 Interconnect */
 690                         reg-names = "mpu", "dma";
 691                         interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 692                         interrupt-names = "common";
 693                         ti,buffer-size = <128>;
 694                         ti,hwmods = "mcbsp2";
 695                         dmas = <&sdma 17>,
 696                                <&sdma 18>;
 697                         dma-names = "tx", "rx";
 698                         status = "disabled";
 699                 };
 700
 701                 mcbsp3: mcbsp@40126000 {
 702                         compatible = "ti,omap4-mcbsp";
 703                         reg = <0x40126000 0xff>, /* MPU private access */
 704                               <0x49026000 0xff>; /* L3 Interconnect */
 705                         reg-names = "mpu", "dma";
 706                         interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 707                         interrupt-names = "common";
 708                         ti,buffer-size = <128>;
 709                         ti,hwmods = "mcbsp3";
 710                         dmas = <&sdma 19>,
 711                                <&sdma 20>;
 712                         dma-names = "tx", "rx";
 713                         status = "disabled";
 714                 };
 715
 716                 mailbox: mailbox@4a0f4000 {
 717                         compatible = "ti,omap4-mailbox";
 718                         reg = <0x4a0f4000 0x200>;
 719                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 720                         ti,hwmods = "mailbox";
 721                         #mbox-cells = <1>;
 722                         ti,mbox-num-users = <3>;
 723                         ti,mbox-num-fifos = <8>;
 724                         mbox_ipu: mbox_ipu {
 725                                 ti,mbox-tx = <0 0 0>;
 726                                 ti,mbox-rx = <1 0 0>;
 727                         };
 728                         mbox_dsp: mbox_dsp {
 729                                 ti,mbox-tx = <3 0 0>;
 730                                 ti,mbox-rx = <2 0 0>;
 731                         };
 732                 };
 733
 734                 timer1: timer@4ae18000 {
 735                         compatible = "ti,omap5430-timer";
 736                         reg = <0x4ae18000 0x80>;
 737                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 738                         ti,hwmods = "timer1";
 739                         ti,timer-alwon;
 740                 };
 741
 742                 timer2: timer@48032000 {
 743                         compatible = "ti,omap5430-timer";
 744                         reg = <0x48032000 0x80>;
 745                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 746                         ti,hwmods = "timer2";
 747                 };
 748
 749                 timer3: timer@48034000 {
 750                         compatible = "ti,omap5430-timer";
 751                         reg = <0x48034000 0x80>;
 752                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 753                         ti,hwmods = "timer3";
 754                 };
 755
 756                 timer4: timer@48036000 {
 757                         compatible = "ti,omap5430-timer";
 758                         reg = <0x48036000 0x80>;
 759                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 760                         ti,hwmods = "timer4";
 761                 };
 762
 763                 timer5: timer@40138000 {
 764                         compatible = "ti,omap5430-timer";
 765                         reg = <0x40138000 0x80>,
 766                               <0x49038000 0x80>;
 767                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 768                         ti,hwmods = "timer5";
 769                         ti,timer-dsp;
 770                         ti,timer-pwm;
 771                 };
 772
 773                 timer6: timer@4013a000 {
 774                         compatible = "ti,omap5430-timer";
 775                         reg = <0x4013a000 0x80>,
 776                               <0x4903a000 0x80>;
 777                         interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 778                         ti,hwmods = "timer6";
 779                         ti,timer-dsp;
 780                         ti,timer-pwm;
 781                 };
 782
 783                 timer7: timer@4013c000 {
 784                         compatible = "ti,omap5430-timer";
 785                         reg = <0x4013c000 0x80>,
 786                               <0x4903c000 0x80>;
 787                         interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 788                         ti,hwmods = "timer7";
 789                         ti,timer-dsp;
 790                 };
 791
 792                 timer8: timer@4013e000 {
 793                         compatible = "ti,omap5430-timer";
 794                         reg = <0x4013e000 0x80>,
 795                               <0x4903e000 0x80>;
 796                         interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 797                         ti,hwmods = "timer8";
 798                         ti,timer-dsp;
 799                         ti,timer-pwm;
 800                 };
 801
 802                 timer9: timer@4803e000 {
 803                         compatible = "ti,omap5430-timer";
 804                         reg = <0x4803e000 0x80>;
 805                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 806                         ti,hwmods = "timer9";
 807                         ti,timer-pwm;
 808                 };
 809
 810                 timer10: timer@48086000 {
 811                         compatible = "ti,omap5430-timer";
 812                         reg = <0x48086000 0x80>;
 813                         interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 814                         ti,hwmods = "timer10";
 815                         ti,timer-pwm;
 816                 };
 817
 818                 timer11: timer@48088000 {
 819                         compatible = "ti,omap5430-timer";
 820                         reg = <0x48088000 0x80>;
 821                         interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 822                         ti,hwmods = "timer11";
 823                         ti,timer-pwm;
 824                 };
 825
 826                 wdt2: wdt@4ae14000 {
 827                         compatible = "ti,omap5-wdt", "ti,omap3-wdt";
 828                         reg = <0x4ae14000 0x80>;
 829                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 830                         ti,hwmods = "wd_timer2";
 831                 };
 832
 833                 dmm@4e000000 {
 834                         compatible = "ti,omap5-dmm";
 835                         reg = <0x4e000000 0x800>;
 836                         interrupts = <0 113 0x4>;
 837                         ti,hwmods = "dmm";
 838                 };
 839
 840                 emif1: emif@4c000000 {
 841                         compatible      = "ti,emif-4d5";
 842                         ti,hwmods       = "emif1";
 843                         ti,no-idle-on-init;
 844                         phy-type        = <2>; /* DDR PHY type: Intelli PHY */
 845                         reg = <0x4c000000 0x400>;
 846                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 847                         hw-caps-read-idle-ctrl;
 848                         hw-caps-ll-interface;
 849                         hw-caps-temp-alert;
 850                 };
 851
 852                 emif2: emif@4d000000 {
 853                         compatible      = "ti,emif-4d5";
 854                         ti,hwmods       = "emif2";
 855                         ti,no-idle-on-init;
 856                         phy-type        = <2>; /* DDR PHY type: Intelli PHY */
 857                         reg = <0x4d000000 0x400>;
 858                         interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 859                         hw-caps-read-idle-ctrl;
 860                         hw-caps-ll-interface;
 861                         hw-caps-temp-alert;
 862                 };
 863
 864                 usb3: omap_dwc3@4a020000 {
 865                         compatible = "ti,dwc3";
 866                         ti,hwmods = "usb_otg_ss";
 867                         reg = <0x4a020000 0x10000>;
 868                         interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 869                         #address-cells = <1>;
 870                         #size-cells = <1>;
 871                         utmi-mode = <2>;
 872                         ranges;
 873                         dwc3: dwc3@4a030000 {
 874                                 compatible = "snps,dwc3";
 875                                 reg = <0x4a030000 0x10000>;
 876                                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
 877                                              <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
 878                                              <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 879                                 interrupt-names = "peripheral",
 880                                                   "host",
 881                                                   "otg";
 882                                 phys = <&usb2_phy>, <&usb3_phy>;
 883                                 phy-names = "usb2-phy", "usb3-phy";
 884                                 dr_mode = "peripheral";
 885                         };
 886                 };
 887
 888                 ocp2scp@4a080000 {
 889                         compatible = "ti,omap-ocp2scp";
 890                         #address-cells = <1>;
 891                         #size-cells = <1>;
 892                         reg = <0x4a080000 0x20>;
 893                         ranges;
 894                         ti,hwmods = "ocp2scp1";
 895                         usb2_phy: usb2phy@4a084000 {
 896                                 compatible = "ti,omap-usb2";
 897                                 reg = <0x4a084000 0x7c>;
 898                                 syscon-phy-power = <&scm_conf 0x300>;
 899                                 clocks = <&usb_phy_cm_clk32k>, <&usb_otg_ss_refclk960m>;
 900                                 clock-names = "wkupclk", "refclk";
 901                                 #phy-cells = <0>;
 902                         };
 903
 904                         usb3_phy: usb3phy@4a084400 {
 905                                 compatible = "ti,omap-usb3";
 906                                 reg = <0x4a084400 0x80>,
 907                                       <0x4a084800 0x64>,
 908                                       <0x4a084c00 0x40>;
 909                                 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
 910                                 syscon-phy-power = <&scm_conf 0x370>;
 911                                 clocks = <&usb_phy_cm_clk32k>,
 912                                          <&sys_clkin>,
 913                                          <&usb_otg_ss_refclk960m>;
 914                                 clock-names =   "wkupclk",
 915                                                 "sysclk",
 916                                                 "refclk";
 917                                 #phy-cells = <0>;
 918                         };
 919                 };
 920
 921                 usbhstll: usbhstll@4a062000 {
 922                         compatible = "ti,usbhs-tll";
 923                         reg = <0x4a062000 0x1000>;
 924                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 925                         ti,hwmods = "usb_tll_hs";
 926                 };
 927
 928                 usbhshost: usbhshost@4a064000 {
 929                         compatible = "ti,usbhs-host";
 930                         reg = <0x4a064000 0x800>;
 931                         ti,hwmods = "usb_host_hs";
 932                         #address-cells = <1>;
 933                         #size-cells = <1>;
 934                         ranges;
 935                         clocks = <&l3init_60m_fclk>,
 936                                  <&xclk60mhsp1_ck>,
 937                                  <&xclk60mhsp2_ck>;
 938                         clock-names = "refclk_60m_int",
 939                                       "refclk_60m_ext_p1",
 940                                       "refclk_60m_ext_p2";
 941
 942                         usbhsohci: ohci@4a064800 {
 943                                 compatible = "ti,ohci-omap3";
 944                                 reg = <0x4a064800 0x400>;
 945                                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 946                         };
 947
 948                         usbhsehci: ehci@4a064c00 {
 949                                 compatible = "ti,ehci-omap";
 950                                 reg = <0x4a064c00 0x400>;
 951                                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 952                         };
 953                 };
 954
 955                 bandgap: bandgap@4a0021e0 {
 956                         reg = <0x4a0021e0 0xc
 957                                0x4a00232c 0xc
 958                                0x4a002380 0x2c
 959                                0x4a0023C0 0x3c>;
 960                         interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
 961                         compatible = "ti,omap5430-bandgap";
 962
 963                         #thermal-sensor-cells = <1>;
 964                 };
 965
 966                 /* OCP2SCP3 */
 967                 ocp2scp@4a090000 {
 968                         compatible = "ti,omap-ocp2scp";
 969                         #address-cells = <1>;
 970                         #size-cells = <1>;
 971                         reg = <0x4a090000 0x20>;
 972                         ranges;
 973                         ti,hwmods = "ocp2scp3";
 974                         sata_phy: phy@4a096000 {
 975                                 compatible = "ti,phy-pipe3-sata";
 976                                 reg = <0x4A096000 0x80>, /* phy_rx */
 977                                       <0x4A096400 0x64>, /* phy_tx */
 978                                       <0x4A096800 0x40>; /* pll_ctrl */
 979                                 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
 980                                 syscon-phy-power = <&scm_conf 0x374>;
 981                                 clocks = <&sys_clkin>, <&sata_ref_clk>;
 982                                 clock-names = "sysclk", "refclk";
 983                                 #phy-cells = <0>;
 984                         };
 985                 };
 986
 987                 sata: sata@4a141100 {
 988                         compatible = "snps,dwc-ahci";
 989                         reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
 990                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 991                         phys = <&sata_phy>;
 992                         phy-names = "sata-phy";
 993                         clocks = <&sata_ref_clk>;
 994                         ti,hwmods = "sata";
 995                         ports-implemented = <0x1>;
 996                 };
 997
 998                 dss: dss@58000000 {
 999                         compatible = "ti,omap5-dss";
1000                         reg = <0x58000000 0x80>;
1001                         status = "disabled";
1002                         ti,hwmods = "dss_core";
1003                         clocks = <&dss_dss_clk>;
1004                         clock-names = "fck";
1005                         #address-cells = <1>;
1006                         #size-cells = <1>;
1007                         ranges;
1008
1009                         dispc@58001000 {
1010                                 compatible = "ti,omap5-dispc";
1011                                 reg = <0x58001000 0x1000>;
1012                                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1013                                 ti,hwmods = "dss_dispc";
1014                                 clocks = <&dss_dss_clk>;
1015                                 clock-names = "fck";
1016                         };
1017
1018                         rfbi: encoder@58002000  {
1019                                 compatible = "ti,omap5-rfbi";
1020                                 reg = <0x58002000 0x100>;
1021                                 status = "disabled";
1022                                 ti,hwmods = "dss_rfbi";
1023                                 clocks = <&dss_dss_clk>, <&l3_iclk_div>;
1024                                 clock-names = "fck", "ick";
1025                         };
1026
1027                         dsi1: encoder@58004000 {
1028                                 compatible = "ti,omap5-dsi";
1029                                 reg = <0x58004000 0x200>,
1030                                       <0x58004200 0x40>,
1031                                       <0x58004300 0x40>;
1032                                 reg-names = "proto", "phy", "pll";
1033                                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1034                                 status = "disabled";
1035                                 ti,hwmods = "dss_dsi1";
1036                                 clocks = <&dss_dss_clk>, <&dss_sys_clk>;
1037                                 clock-names = "fck", "sys_clk";
1038                         };
1039
1040                         dsi2: encoder@58005000 {
1041                                 compatible = "ti,omap5-dsi";
1042                                 reg = <0x58009000 0x200>,
1043                                       <0x58009200 0x40>,
1044                                       <0x58009300 0x40>;
1045                                 reg-names = "proto", "phy", "pll";
1046                                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
1047                                 status = "disabled";
1048                                 ti,hwmods = "dss_dsi2";
1049                                 clocks = <&dss_dss_clk>, <&dss_sys_clk>;
1050                                 clock-names = "fck", "sys_clk";
1051                         };
1052
1053                         hdmi: encoder@58060000 {
1054                                 compatible = "ti,omap5-hdmi";
1055                                 reg = <0x58040000 0x200>,
1056                                       <0x58040200 0x80>,
1057                                       <0x58040300 0x80>,
1058                                       <0x58060000 0x19000>;
1059                                 reg-names = "wp", "pll", "phy", "core";
1060                                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1061                                 status = "disabled";
1062                                 ti,hwmods = "dss_hdmi";
1063                                 clocks = <&dss_48mhz_clk>, <&dss_sys_clk>;
1064                                 clock-names = "fck", "sys_clk";
1065                                 dmas = <&sdma 76>;
1066                                 dma-names = "audio_tx";
1067                         };
1068                 };
1069
1070                 abb_mpu: regulator-abb-mpu {
1071                         compatible = "ti,abb-v2";
1072                         regulator-name = "abb_mpu";
1073                         #address-cells = <0>;
1074                         #size-cells = <0>;
1075                         clocks = <&sys_clkin>;
1076                         ti,settling-time = <50>;
1077                         ti,clock-cycles = <16>;
1078
1079                         reg = <0x4ae07cdc 0x8>, <0x4ae06014 0x4>,
1080                               <0x4a0021c4 0x8>, <0x4ae0c318 0x4>;
1081                         reg-names = "base-address", "int-address",
1082                                     "efuse-address", "ldo-address";
1083                         ti,tranxdone-status-mask = <0x80>;
1084                         /* LDOVBBMPU_MUX_CTRL */
1085                         ti,ldovbb-override-mask = <0x400>;
1086                         /* LDOVBBMPU_VSET_OUT */
1087                         ti,ldovbb-vset-mask = <0x1F>;
1088
1089                         /*
1090                          * NOTE: only FBB mode used but actual vset will
1091                          * determine final biasing
1092                          */
1093                         ti,abb_info = <
1094                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
1095                         1060000         0       0x0     0 0x02000000 0x01F00000
1096                         1250000         0       0x4     0 0x02000000 0x01F00000
1097                         >;
1098                 };
1099
1100                 abb_mm: regulator-abb-mm {
1101                         compatible = "ti,abb-v2";
1102                         regulator-name = "abb_mm";
1103                         #address-cells = <0>;
1104                         #size-cells = <0>;
1105                         clocks = <&sys_clkin>;
1106                         ti,settling-time = <50>;
1107                         ti,clock-cycles = <16>;
1108
1109                         reg = <0x4ae07ce4 0x8>, <0x4ae06010 0x4>,
1110                               <0x4a0021a4 0x8>, <0x4ae0c314 0x4>;
1111                         reg-names = "base-address", "int-address",
1112                                     "efuse-address", "ldo-address";
1113                         ti,tranxdone-status-mask = <0x80000000>;
1114                         /* LDOVBBMM_MUX_CTRL */
1115                         ti,ldovbb-override-mask = <0x400>;
1116                         /* LDOVBBMM_VSET_OUT */
1117                         ti,ldovbb-vset-mask = <0x1F>;
1118
1119                         /*
1120                          * NOTE: only FBB mode used but actual vset will
1121                          * determine final biasing
1122                          */
1123                         ti,abb_info = <
1124                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
1125                         1025000         0       0x0     0 0x02000000 0x01F00000
1126                         1120000         0       0x4     0 0x02000000 0x01F00000
1127                         >;
1128                 };
1129         };
1130 };
1131
1132 &cpu_thermal {
1133         polling-delay = <500>; /* milliseconds */
1134 };
1135
1136 /include/ "omap54xx-clocks.dtsi"