2 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
9 #include <dt-bindings/bus/ti-sysc.h>
10 #include <dt-bindings/clock/omap4.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/pinctrl/omap.h>
14 #include <dt-bindings/clock/omap4.h>
17 compatible = "ti,omap4430", "ti,omap4";
18 interrupt-parent = <&wakeupgen>;
44 compatible = "arm,cortex-a9";
46 next-level-cache = <&L2>;
49 clocks = <&dpll_mpu_ck>;
52 clock-latency = <300000>; /* From omap-cpufreq driver */
55 compatible = "arm,cortex-a9";
57 next-level-cache = <&L2>;
63 * Note that 4430 needs cross trigger interface (CTI) supported
64 * before we can configure the interrupts. This means sampling
65 * events are not supported for pmu. Note that 4460 does not use
66 * CTI, see also 4460.dtsi.
69 compatible = "arm,cortex-a9-pmu";
70 ti,hwmods = "debugss";
73 gic: interrupt-controller@48241000 {
74 compatible = "arm,cortex-a9-gic";
76 #interrupt-cells = <3>;
77 reg = <0x48241000 0x1000>,
79 interrupt-parent = <&gic>;
82 L2: l2-cache-controller@48242000 {
83 compatible = "arm,pl310-cache";
84 reg = <0x48242000 0x1000>;
89 local-timer@48240600 {
90 compatible = "arm,cortex-a9-twd-timer";
91 clocks = <&mpu_periphclk>;
92 reg = <0x48240600 0x20>;
93 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_EDGE_RISING)>;
94 interrupt-parent = <&gic>;
97 wakeupgen: interrupt-controller@48281000 {
98 compatible = "ti,omap4-wugen-mpu";
100 #interrupt-cells = <3>;
101 reg = <0x48281000 0x1000>;
102 interrupt-parent = <&gic>;
106 * The soc node represents the soc top level view. It is used for IPs
107 * that are not memory mapped in the MPU view or for the MPU itself.
110 compatible = "ti,omap-infra";
112 compatible = "ti,omap4-mpu";
118 compatible = "ti,omap3-c64";
123 compatible = "ti,ivahd";
129 * XXX: Use a flat representation of the OMAP4 interconnect.
130 * The real OMAP interconnect network is quite complex.
131 * Since it will not bring real advantage to represent that in DT for
132 * the moment, just use a fake OCP bus entry to represent the whole bus
136 compatible = "ti,omap4-l3-noc", "simple-bus";
137 #address-cells = <1>;
140 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
141 reg = <0x44000000 0x1000>,
144 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
145 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
147 l4_wkup: interconnect@4a300000 {
150 l4_cfg: interconnect@4a000000 {
153 l4_per: interconnect@48000000 {
156 ocmcram: ocmcram@40304000 {
157 compatible = "mmio-sram";
158 reg = <0x40304000 0xa000>; /* 40k */
161 gpmc: gpmc@50000000 {
162 compatible = "ti,omap4430-gpmc";
163 reg = <0x50000000 0x1000>;
164 #address-cells = <2>;
166 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
170 gpmc,num-waitpins = <4>;
173 clocks = <&l3_div_ck>;
175 interrupt-controller;
176 #interrupt-cells = <2>;
181 mmu_dsp: mmu@4a066000 {
182 compatible = "ti,omap4-iommu";
183 reg = <0x4a066000 0x100>;
184 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
185 ti,hwmods = "mmu_dsp";
189 target-module@52000000 {
190 compatible = "ti,sysc-omap4", "ti,sysc";
192 reg = <0x52000000 0x4>,
194 reg-names = "rev", "sysc";
195 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
196 ti,sysc-midle = <SYSC_IDLE_FORCE>,
199 <SYSC_IDLE_SMART_WKUP>;
200 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
203 <SYSC_IDLE_SMART_WKUP>;
204 ti,sysc-delay-us = <2>;
205 clocks = <&iss_clkctrl OMAP4_ISS_CLKCTRL 0>;
207 #address-cells = <1>;
209 ranges = <0 0x52000000 0x1000000>;
211 /* No child device binding, driver in staging */
214 mmu_ipu: mmu@55082000 {
215 compatible = "ti,omap4-iommu";
216 reg = <0x55082000 0x100>;
217 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
218 ti,hwmods = "mmu_ipu";
220 ti,iommu-bus-err-back;
222 target-module@40130000 {
223 compatible = "ti,sysc-omap2", "ti,sysc";
224 ti,hwmods = "wd_timer3";
225 reg = <0x40130000 0x4>,
228 reg-names = "rev", "sysc", "syss";
229 ti,sysc-mask = <(SYSC_OMAP2_EMUFREE |
230 SYSC_OMAP2_SOFTRESET)>;
231 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
234 <SYSC_IDLE_SMART_WKUP>;
236 /* Domains (V, P, C): abe, abe_pwrdm, abe_clkdm */
237 clocks = <&abe_clkctrl OMAP4_WD_TIMER3_CLKCTRL 0>;
239 #address-cells = <1>;
241 ranges = <0x00000000 0x40130000 0x1000>, /* MPU private access */
242 <0x49030000 0x49030000 0x0080>; /* L3 Interconnect */
245 compatible = "ti,omap4-wdt", "ti,omap3-wdt";
247 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
251 mcpdm: mcpdm@40132000 {
252 compatible = "ti,omap4-mcpdm";
253 reg = <0x40132000 0x7f>, /* MPU private access */
254 <0x49032000 0x7f>; /* L3 Interconnect */
255 reg-names = "mpu", "dma";
256 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
260 dma-names = "up_link", "dn_link";
264 dmic: dmic@4012e000 {
265 compatible = "ti,omap4-dmic";
266 reg = <0x4012e000 0x7f>, /* MPU private access */
267 <0x4902e000 0x7f>; /* L3 Interconnect */
268 reg-names = "mpu", "dma";
269 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
272 dma-names = "up_link";
276 mcbsp1: mcbsp@40122000 {
277 compatible = "ti,omap4-mcbsp";
278 reg = <0x40122000 0xff>, /* MPU private access */
279 <0x49022000 0xff>; /* L3 Interconnect */
280 reg-names = "mpu", "dma";
281 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
282 interrupt-names = "common";
283 ti,buffer-size = <128>;
284 ti,hwmods = "mcbsp1";
287 dma-names = "tx", "rx";
291 mcbsp2: mcbsp@40124000 {
292 compatible = "ti,omap4-mcbsp";
293 reg = <0x40124000 0xff>, /* MPU private access */
294 <0x49024000 0xff>; /* L3 Interconnect */
295 reg-names = "mpu", "dma";
296 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
297 interrupt-names = "common";
298 ti,buffer-size = <128>;
299 ti,hwmods = "mcbsp2";
302 dma-names = "tx", "rx";
306 mcbsp3: mcbsp@40126000 {
307 compatible = "ti,omap4-mcbsp";
308 reg = <0x40126000 0xff>, /* MPU private access */
309 <0x49026000 0xff>; /* L3 Interconnect */
310 reg-names = "mpu", "dma";
311 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
312 interrupt-names = "common";
313 ti,buffer-size = <128>;
314 ti,hwmods = "mcbsp3";
317 dma-names = "tx", "rx";
321 target-module@40128000 {
322 compatible = "ti,sysc-mcasp", "ti,sysc";
324 reg = <0x40128000 0x4>,
326 reg-names = "rev", "sysc";
327 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
330 <SYSC_IDLE_SMART_WKUP>;
331 clocks = <&abe_clkctrl OMAP4_MCASP_CLKCTRL 0>;
333 #address-cells = <1>;
335 ranges = <0x00000000 0x40128000 0x1000>, /* MPU */
336 <0x49028000 0x49028000 0x1000>; /* L3 */
339 * Child device unsupported by davinci-mcasp. At least
340 * RX path is disabled for omap4, and only DIT mode
341 * works with no I2S. See also old Android kernel
342 * omap-mcasp driver for more information.
346 target-module@4012c000 {
347 compatible = "ti,sysc-omap4", "ti,sysc";
348 ti,hwmods = "slimbus1";
349 reg = <0x4012c000 0x4>,
351 reg-names = "rev", "sysc";
352 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
353 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
356 <SYSC_IDLE_SMART_WKUP>;
357 clocks = <&abe_clkctrl OMAP4_SLIMBUS1_CLKCTRL 0>;
359 #address-cells = <1>;
361 ranges = <0x00000000 0x4012c000 0x1000>, /* MPU */
362 <0x4902c000 0x4902c000 0x1000>; /* L3 */
364 /* No child device binding or driver in mainline */
367 target-module@401f1000 {
368 compatible = "ti,sysc-omap4", "ti,sysc";
370 reg = <0x401f1000 0x4>,
372 reg-names = "rev", "sysc";
373 ti,sysc-midle = <SYSC_IDLE_FORCE>,
376 <SYSC_IDLE_SMART_WKUP>;
377 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
380 clocks = <&abe_clkctrl OMAP4_AESS_CLKCTRL 0>;
382 #address-cells = <1>;
384 ranges = <0x00000000 0x401f1000 0x1000>, /* MPU */
385 <0x490f1000 0x490f1000 0x1000>; /* L3 */
388 * No child device binding or driver in mainline.
389 * See Android tree and related upstreaming efforts
390 * for the old driver.
395 compatible = "ti,omap4-dmm";
396 reg = <0x4e000000 0x800>;
397 interrupts = <0 113 0x4>;
401 emif1: emif@4c000000 {
402 compatible = "ti,emif-4d";
403 reg = <0x4c000000 0x100>;
404 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
408 hw-caps-read-idle-ctrl;
409 hw-caps-ll-interface;
413 emif2: emif@4d000000 {
414 compatible = "ti,emif-4d";
415 reg = <0x4d000000 0x100>;
416 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
420 hw-caps-read-idle-ctrl;
421 hw-caps-ll-interface;
425 timer5: timer@40138000 {
426 compatible = "ti,omap4430-timer";
427 reg = <0x40138000 0x80>,
429 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
430 ti,hwmods = "timer5";
434 timer6: timer@4013a000 {
435 compatible = "ti,omap4430-timer";
436 reg = <0x4013a000 0x80>,
438 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
439 ti,hwmods = "timer6";
443 timer7: timer@4013c000 {
444 compatible = "ti,omap4430-timer";
445 reg = <0x4013c000 0x80>,
447 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
448 ti,hwmods = "timer7";
452 timer8: timer@4013e000 {
453 compatible = "ti,omap4430-timer";
454 reg = <0x4013e000 0x80>,
456 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
457 ti,hwmods = "timer8";
463 compatible = "ti,omap4-aes";
465 reg = <0x4b501000 0xa0>;
466 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
467 dmas = <&sdma 111>, <&sdma 110>;
468 dma-names = "tx", "rx";
472 compatible = "ti,omap4-aes";
474 reg = <0x4b701000 0xa0>;
475 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
476 dmas = <&sdma 114>, <&sdma 113>;
477 dma-names = "tx", "rx";
481 compatible = "ti,omap4-des";
483 reg = <0x480a5000 0xa0>;
484 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
485 dmas = <&sdma 117>, <&sdma 116>;
486 dma-names = "tx", "rx";
489 sham: sham@4b100000 {
490 compatible = "ti,omap4-sham";
492 reg = <0x4b100000 0x300>;
493 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
498 abb_mpu: regulator-abb-mpu {
499 compatible = "ti,abb-v2";
500 regulator-name = "abb_mpu";
501 #address-cells = <0>;
503 ti,tranxdone-status-mask = <0x80>;
504 clocks = <&sys_clkin_ck>;
505 ti,settling-time = <50>;
506 ti,clock-cycles = <16>;
511 abb_iva: regulator-abb-iva {
512 compatible = "ti,abb-v2";
513 regulator-name = "abb_iva";
514 #address-cells = <0>;
516 ti,tranxdone-status-mask = <0x80000000>;
517 clocks = <&sys_clkin_ck>;
518 ti,settling-time = <50>;
519 ti,clock-cycles = <16>;
524 sgx_module: target-module@56000000 {
525 compatible = "ti,sysc-omap4", "ti,sysc";
527 reg = <0x5601fc00 0x4>,
529 reg-names = "rev", "sysc";
530 ti,sysc-midle = <SYSC_IDLE_FORCE>,
533 <SYSC_IDLE_SMART_WKUP>;
534 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
537 <SYSC_IDLE_SMART_WKUP>;
538 clocks = <&l3_gfx_clkctrl OMAP4_GPU_CLKCTRL 0>;
540 #address-cells = <1>;
542 ranges = <0 0x56000000 0x2000000>;
545 * Closed source PowerVR driver, no child device
546 * binding or driver in mainline
551 compatible = "ti,omap4-dss";
552 reg = <0x58000000 0x80>;
554 ti,hwmods = "dss_core";
555 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>;
557 #address-cells = <1>;
562 compatible = "ti,omap4-dispc";
563 reg = <0x58001000 0x1000>;
564 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
565 ti,hwmods = "dss_dispc";
566 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>;
570 rfbi: encoder@58002000 {
571 compatible = "ti,omap4-rfbi";
572 reg = <0x58002000 0x1000>;
574 ti,hwmods = "dss_rfbi";
575 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>, <&l3_div_ck>;
576 clock-names = "fck", "ick";
579 venc: encoder@58003000 {
580 compatible = "ti,omap4-venc";
581 reg = <0x58003000 0x1000>;
583 ti,hwmods = "dss_venc";
584 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 11>;
588 dsi1: encoder@58004000 {
589 compatible = "ti,omap4-dsi";
590 reg = <0x58004000 0x200>,
593 reg-names = "proto", "phy", "pll";
594 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
596 ti,hwmods = "dss_dsi1";
597 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
598 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
599 clock-names = "fck", "sys_clk";
602 dsi2: encoder@58005000 {
603 compatible = "ti,omap4-dsi";
604 reg = <0x58005000 0x200>,
607 reg-names = "proto", "phy", "pll";
608 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
610 ti,hwmods = "dss_dsi2";
611 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
612 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
613 clock-names = "fck", "sys_clk";
616 hdmi: encoder@58006000 {
617 compatible = "ti,omap4-hdmi";
618 reg = <0x58006000 0x200>,
622 reg-names = "wp", "pll", "phy", "core";
623 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
625 ti,hwmods = "dss_hdmi";
626 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 9>,
627 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
628 clock-names = "fck", "sys_clk";
630 dma-names = "audio_tx";
636 #include "omap4-l4.dtsi"
637 #include "omap44xx-clocks.dtsi"