1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
6 #include <dt-bindings/bus/ti-sysc.h>
7 #include <dt-bindings/clock/omap4.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/pinctrl/omap.h>
11 #include <dt-bindings/clock/omap4.h>
14 compatible = "ti,omap4430", "ti,omap4";
15 interrupt-parent = <&wakeupgen>;
41 compatible = "arm,cortex-a9";
43 next-level-cache = <&L2>;
46 clocks = <&dpll_mpu_ck>;
49 clock-latency = <300000>; /* From omap-cpufreq driver */
52 compatible = "arm,cortex-a9";
54 next-level-cache = <&L2>;
60 * Note that 4430 needs cross trigger interface (CTI) supported
61 * before we can configure the interrupts. This means sampling
62 * events are not supported for pmu. Note that 4460 does not use
63 * CTI, see also 4460.dtsi.
66 compatible = "arm,cortex-a9-pmu";
67 ti,hwmods = "debugss";
70 gic: interrupt-controller@48241000 {
71 compatible = "arm,cortex-a9-gic";
73 #interrupt-cells = <3>;
74 reg = <0x48241000 0x1000>,
76 interrupt-parent = <&gic>;
79 L2: l2-cache-controller@48242000 {
80 compatible = "arm,pl310-cache";
81 reg = <0x48242000 0x1000>;
86 local-timer@48240600 {
87 compatible = "arm,cortex-a9-twd-timer";
88 clocks = <&mpu_periphclk>;
89 reg = <0x48240600 0x20>;
90 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_EDGE_RISING)>;
91 interrupt-parent = <&gic>;
94 wakeupgen: interrupt-controller@48281000 {
95 compatible = "ti,omap4-wugen-mpu";
97 #interrupt-cells = <3>;
98 reg = <0x48281000 0x1000>;
99 interrupt-parent = <&gic>;
103 * The soc node represents the soc top level view. It is used for IPs
104 * that are not memory mapped in the MPU view or for the MPU itself.
107 compatible = "ti,omap-infra";
109 compatible = "ti,omap4-mpu";
115 compatible = "ti,omap3-c64";
120 compatible = "ti,ivahd";
126 * XXX: Use a flat representation of the OMAP4 interconnect.
127 * The real OMAP interconnect network is quite complex.
128 * Since it will not bring real advantage to represent that in DT for
129 * the moment, just use a fake OCP bus entry to represent the whole bus
133 compatible = "ti,omap4-l3-noc", "simple-bus";
134 #address-cells = <1>;
137 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
138 reg = <0x44000000 0x1000>,
141 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
142 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
144 l4_wkup: interconnect@4a300000 {
147 l4_cfg: interconnect@4a000000 {
150 l4_per: interconnect@48000000 {
153 l4_abe: interconnect@40100000 {
156 ocmcram: ocmcram@40304000 {
157 compatible = "mmio-sram";
158 reg = <0x40304000 0xa000>; /* 40k */
161 gpmc: gpmc@50000000 {
162 compatible = "ti,omap4430-gpmc";
163 reg = <0x50000000 0x1000>;
164 #address-cells = <2>;
166 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
170 gpmc,num-waitpins = <4>;
173 clocks = <&l3_div_ck>;
175 interrupt-controller;
176 #interrupt-cells = <2>;
181 mmu_dsp: mmu@4a066000 {
182 compatible = "ti,omap4-iommu";
183 reg = <0x4a066000 0x100>;
184 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
185 ti,hwmods = "mmu_dsp";
189 target-module@52000000 {
190 compatible = "ti,sysc-omap4", "ti,sysc";
192 reg = <0x52000000 0x4>,
194 reg-names = "rev", "sysc";
195 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
196 ti,sysc-midle = <SYSC_IDLE_FORCE>,
199 <SYSC_IDLE_SMART_WKUP>;
200 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
203 <SYSC_IDLE_SMART_WKUP>;
204 ti,sysc-delay-us = <2>;
205 clocks = <&iss_clkctrl OMAP4_ISS_CLKCTRL 0>;
207 #address-cells = <1>;
209 ranges = <0 0x52000000 0x1000000>;
211 /* No child device binding, driver in staging */
214 mmu_ipu: mmu@55082000 {
215 compatible = "ti,omap4-iommu";
216 reg = <0x55082000 0x100>;
217 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
218 ti,hwmods = "mmu_ipu";
220 ti,iommu-bus-err-back;
222 target-module@4012c000 {
223 compatible = "ti,sysc-omap4", "ti,sysc";
224 ti,hwmods = "slimbus1";
225 reg = <0x4012c000 0x4>,
227 reg-names = "rev", "sysc";
228 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
229 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
232 <SYSC_IDLE_SMART_WKUP>;
233 clocks = <&abe_clkctrl OMAP4_SLIMBUS1_CLKCTRL 0>;
235 #address-cells = <1>;
237 ranges = <0x00000000 0x4012c000 0x1000>, /* MPU */
238 <0x4902c000 0x4902c000 0x1000>; /* L3 */
240 /* No child device binding or driver in mainline */
244 compatible = "ti,omap4-dmm";
245 reg = <0x4e000000 0x800>;
246 interrupts = <0 113 0x4>;
250 emif1: emif@4c000000 {
251 compatible = "ti,emif-4d";
252 reg = <0x4c000000 0x100>;
253 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
257 hw-caps-read-idle-ctrl;
258 hw-caps-ll-interface;
262 emif2: emif@4d000000 {
263 compatible = "ti,emif-4d";
264 reg = <0x4d000000 0x100>;
265 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
269 hw-caps-read-idle-ctrl;
270 hw-caps-ll-interface;
275 compatible = "ti,omap4-aes";
277 reg = <0x4b501000 0xa0>;
278 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
279 dmas = <&sdma 111>, <&sdma 110>;
280 dma-names = "tx", "rx";
284 compatible = "ti,omap4-aes";
286 reg = <0x4b701000 0xa0>;
287 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
288 dmas = <&sdma 114>, <&sdma 113>;
289 dma-names = "tx", "rx";
293 compatible = "ti,omap4-des";
295 reg = <0x480a5000 0xa0>;
296 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
297 dmas = <&sdma 117>, <&sdma 116>;
298 dma-names = "tx", "rx";
301 sham: sham@4b100000 {
302 compatible = "ti,omap4-sham";
304 reg = <0x4b100000 0x300>;
305 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
310 abb_mpu: regulator-abb-mpu {
311 compatible = "ti,abb-v2";
312 regulator-name = "abb_mpu";
313 #address-cells = <0>;
315 ti,tranxdone-status-mask = <0x80>;
316 clocks = <&sys_clkin_ck>;
317 ti,settling-time = <50>;
318 ti,clock-cycles = <16>;
323 abb_iva: regulator-abb-iva {
324 compatible = "ti,abb-v2";
325 regulator-name = "abb_iva";
326 #address-cells = <0>;
328 ti,tranxdone-status-mask = <0x80000000>;
329 clocks = <&sys_clkin_ck>;
330 ti,settling-time = <50>;
331 ti,clock-cycles = <16>;
336 sgx_module: target-module@56000000 {
337 compatible = "ti,sysc-omap4", "ti,sysc";
338 reg = <0x5600fe00 0x4>,
340 reg-names = "rev", "sysc";
341 ti,sysc-midle = <SYSC_IDLE_FORCE>,
344 <SYSC_IDLE_SMART_WKUP>;
345 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
348 <SYSC_IDLE_SMART_WKUP>;
349 clocks = <&l3_gfx_clkctrl OMAP4_GPU_CLKCTRL 0>;
351 #address-cells = <1>;
353 ranges = <0 0x56000000 0x2000000>;
356 * Closed source PowerVR driver, no child device
357 * binding or driver in mainline
362 compatible = "ti,omap4-dss";
363 reg = <0x58000000 0x80>;
365 ti,hwmods = "dss_core";
366 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>;
368 #address-cells = <1>;
373 compatible = "ti,omap4-dispc";
374 reg = <0x58001000 0x1000>;
375 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
376 ti,hwmods = "dss_dispc";
377 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>;
381 rfbi: encoder@58002000 {
382 compatible = "ti,omap4-rfbi";
383 reg = <0x58002000 0x1000>;
385 ti,hwmods = "dss_rfbi";
386 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>, <&l3_div_ck>;
387 clock-names = "fck", "ick";
390 venc: encoder@58003000 {
391 compatible = "ti,omap4-venc";
392 reg = <0x58003000 0x1000>;
394 ti,hwmods = "dss_venc";
395 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 11>;
399 dsi1: encoder@58004000 {
400 compatible = "ti,omap4-dsi";
401 reg = <0x58004000 0x200>,
404 reg-names = "proto", "phy", "pll";
405 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
407 ti,hwmods = "dss_dsi1";
408 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
409 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
410 clock-names = "fck", "sys_clk";
413 dsi2: encoder@58005000 {
414 compatible = "ti,omap4-dsi";
415 reg = <0x58005000 0x200>,
418 reg-names = "proto", "phy", "pll";
419 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
421 ti,hwmods = "dss_dsi2";
422 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
423 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
424 clock-names = "fck", "sys_clk";
427 hdmi: encoder@58006000 {
428 compatible = "ti,omap4-hdmi";
429 reg = <0x58006000 0x200>,
433 reg-names = "wp", "pll", "phy", "core";
434 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
436 ti,hwmods = "dss_hdmi";
437 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 9>,
438 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
439 clock-names = "fck", "sys_clk";
441 dma-names = "audio_tx";
447 #include "omap4-l4.dtsi"
448 #include "omap4-l4-abe.dtsi"
449 #include "omap44xx-clocks.dtsi"