arch/arm/boot/dts/omap4.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
   4  */
   5
   6 #include <dt-bindings/bus/ti-sysc.h>
   7 #include <dt-bindings/clock/omap4.h>
   8 #include <dt-bindings/gpio/gpio.h>
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10 #include <dt-bindings/pinctrl/omap.h>
  11 #include <dt-bindings/clock/omap4.h>
  12
  13 / {
  14         compatible = "ti,omap4430", "ti,omap4";
  15         interrupt-parent = <&wakeupgen>;
  16         #address-cells = <1>;
  17         #size-cells = <1>;
  18         chosen { };
  19
  20         aliases {
  21                 i2c0 = &i2c1;
  22                 i2c1 = &i2c2;
  23                 i2c2 = &i2c3;
  24                 i2c3 = &i2c4;
  25                 mmc0 = &mmc1;
  26                 mmc1 = &mmc2;
  27                 mmc2 = &mmc3;
  28                 mmc3 = &mmc4;
  29                 mmc4 = &mmc5;
  30                 serial0 = &uart1;
  31                 serial1 = &uart2;
  32                 serial2 = &uart3;
  33                 serial3 = &uart4;
  34         };
  35
  36         cpus {
  37                 #address-cells = <1>;
  38                 #size-cells = <0>;
  39
  40                 cpu@0 {
  41                         compatible = "arm,cortex-a9";
  42                         device_type = "cpu";
  43                         next-level-cache = <&L2>;
  44                         reg = <0x0>;
  45
  46                         clocks = <&dpll_mpu_ck>;
  47                         clock-names = "cpu";
  48
  49                         clock-latency = <300000>; /* From omap-cpufreq driver */
  50                 };
  51                 cpu@1 {
  52                         compatible = "arm,cortex-a9";
  53                         device_type = "cpu";
  54                         next-level-cache = <&L2>;
  55                         reg = <0x1>;
  56                 };
  57         };
  58
  59         /*
  60          * Note that 4430 needs cross trigger interface (CTI) supported
  61          * before we can configure the interrupts. This means sampling
  62          * events are not supported for pmu. Note that 4460 does not use
  63          * CTI, see also 4460.dtsi.
  64          */
  65         pmu {
  66                 compatible = "arm,cortex-a9-pmu";
  67                 ti,hwmods = "debugss";
  68         };
  69
  70         gic: interrupt-controller@48241000 {
  71                 compatible = "arm,cortex-a9-gic";
  72                 interrupt-controller;
  73                 #interrupt-cells = <3>;
  74                 reg = <0x48241000 0x1000>,
  75                       <0x48240100 0x0100>;
  76                 interrupt-parent = <&gic>;
  77         };
  78
  79         L2: l2-cache-controller@48242000 {
  80                 compatible = "arm,pl310-cache";
  81                 reg = <0x48242000 0x1000>;
  82                 cache-unified;
  83                 cache-level = <2>;
  84         };
  85
  86         local-timer@48240600 {
  87                 compatible = "arm,cortex-a9-twd-timer";
  88                 clocks = <&mpu_periphclk>;
  89                 reg = <0x48240600 0x20>;
  90                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_EDGE_RISING)>;
  91                 interrupt-parent = <&gic>;
  92         };
  93
  94         wakeupgen: interrupt-controller@48281000 {
  95                 compatible = "ti,omap4-wugen-mpu";
  96                 interrupt-controller;
  97                 #interrupt-cells = <3>;
  98                 reg = <0x48281000 0x1000>;
  99                 interrupt-parent = <&gic>;
 100         };
 101
 102         /*
 103          * The soc node represents the soc top level view. It is used for IPs
 104          * that are not memory mapped in the MPU view or for the MPU itself.
 105          */
 106         soc {
 107                 compatible = "ti,omap-infra";
 108                 mpu {
 109                         compatible = "ti,omap4-mpu";
 110                         ti,hwmods = "mpu";
 111                         sram = <&ocmcram>;
 112                 };
 113
 114                 dsp {
 115                         compatible = "ti,omap3-c64";
 116                         ti,hwmods = "dsp";
 117                 };
 118
 119                 iva {
 120                         compatible = "ti,ivahd";
 121                         ti,hwmods = "iva";
 122                 };
 123         };
 124
 125         /*
 126          * XXX: Use a flat representation of the OMAP4 interconnect.
 127          * The real OMAP interconnect network is quite complex.
 128          * Since it will not bring real advantage to represent that in DT for
 129          * the moment, just use a fake OCP bus entry to represent the whole bus
 130          * hierarchy.
 131          */
 132         ocp {
 133                 compatible = "ti,omap4-l3-noc", "simple-bus";
 134                 #address-cells = <1>;
 135                 #size-cells = <1>;
 136                 ranges;
 137                 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
 138                 reg = <0x44000000 0x1000>,
 139                       <0x44800000 0x2000>,
 140                       <0x45000000 0x1000>;
 141                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
 142                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 143
 144                 l4_wkup: interconnect@4a300000 {
 145                 };
 146
 147                 l4_cfg: interconnect@4a000000 {
 148                 };
 149
 150                 l4_per: interconnect@48000000 {
 151                 };
 152
 153                 l4_abe: interconnect@40100000 {
 154                 };
 155
 156                 ocmcram: ocmcram@40304000 {
 157                         compatible = "mmio-sram";
 158                         reg = <0x40304000 0xa000>; /* 40k */
 159                 };
 160
 161                 gpmc: gpmc@50000000 {
 162                         compatible = "ti,omap4430-gpmc";
 163                         reg = <0x50000000 0x1000>;
 164                         #address-cells = <2>;
 165                         #size-cells = <1>;
 166                         interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 167                         dmas = <&sdma 4>;
 168                         dma-names = "rxtx";
 169                         gpmc,num-cs = <8>;
 170                         gpmc,num-waitpins = <4>;
 171                         ti,hwmods = "gpmc";
 172                         ti,no-idle-on-init;
 173                         clocks = <&l3_div_ck>;
 174                         clock-names = "fck";
 175                         interrupt-controller;
 176                         #interrupt-cells = <2>;
 177                         gpio-controller;
 178                         #gpio-cells = <2>;
 179                 };
 180
 181                 mmu_dsp: mmu@4a066000 {
 182                         compatible = "ti,omap4-iommu";
 183                         reg = <0x4a066000 0x100>;
 184                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 185                         ti,hwmods = "mmu_dsp";
 186                         #iommu-cells = <0>;
 187                 };
 188
 189                 target-module@52000000 {
 190                         compatible = "ti,sysc-omap4", "ti,sysc";
 191                         ti,hwmods = "iss";
 192                         reg = <0x52000000 0x4>,
 193                               <0x52000010 0x4>;
 194                         reg-names = "rev", "sysc";
 195                         ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
 196                         ti,sysc-midle = <SYSC_IDLE_FORCE>,
 197                                         <SYSC_IDLE_NO>,
 198                                         <SYSC_IDLE_SMART>,
 199                                         <SYSC_IDLE_SMART_WKUP>;
 200                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 201                                         <SYSC_IDLE_NO>,
 202                                         <SYSC_IDLE_SMART>,
 203                                         <SYSC_IDLE_SMART_WKUP>;
 204                         ti,sysc-delay-us = <2>;
 205                         clocks = <&iss_clkctrl OMAP4_ISS_CLKCTRL 0>;
 206                         clock-names = "fck";
 207                         #address-cells = <1>;
 208                         #size-cells = <1>;
 209                         ranges = <0 0x52000000 0x1000000>;
 210
 211                         /* No child device binding, driver in staging */
 212                 };
 213
 214                 mmu_ipu: mmu@55082000 {
 215                         compatible = "ti,omap4-iommu";
 216                         reg = <0x55082000 0x100>;
 217                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 218                         ti,hwmods = "mmu_ipu";
 219                         #iommu-cells = <0>;
 220                         ti,iommu-bus-err-back;
 221                 };
 222                 target-module@4012c000 {
 223                         compatible = "ti,sysc-omap4", "ti,sysc";
 224                         ti,hwmods = "slimbus1";
 225                         reg = <0x4012c000 0x4>,
 226                               <0x4012c010 0x4>;
 227                         reg-names = "rev", "sysc";
 228                         ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
 229                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 230                                         <SYSC_IDLE_NO>,
 231                                         <SYSC_IDLE_SMART>,
 232                                         <SYSC_IDLE_SMART_WKUP>;
 233                         clocks = <&abe_clkctrl OMAP4_SLIMBUS1_CLKCTRL 0>;
 234                         clock-names = "fck";
 235                         #address-cells = <1>;
 236                         #size-cells = <1>;
 237                         ranges = <0x00000000 0x4012c000 0x1000>, /* MPU */
 238                                  <0x4902c000 0x4902c000 0x1000>; /* L3 */
 239
 240                         /* No child device binding or driver in mainline */
 241                 };
 242
 243                 dmm@4e000000 {
 244                         compatible = "ti,omap4-dmm";
 245                         reg = <0x4e000000 0x800>;
 246                         interrupts = <0 113 0x4>;
 247                         ti,hwmods = "dmm";
 248                 };
 249
 250                 emif1: emif@4c000000 {
 251                         compatible = "ti,emif-4d";
 252                         reg = <0x4c000000 0x100>;
 253                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 254                         ti,hwmods = "emif1";
 255                         ti,no-idle-on-init;
 256                         phy-type = <1>;
 257                         hw-caps-read-idle-ctrl;
 258                         hw-caps-ll-interface;
 259                         hw-caps-temp-alert;
 260                 };
 261
 262                 emif2: emif@4d000000 {
 263                         compatible = "ti,emif-4d";
 264                         reg = <0x4d000000 0x100>;
 265                         interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 266                         ti,hwmods = "emif2";
 267                         ti,no-idle-on-init;
 268                         phy-type = <1>;
 269                         hw-caps-read-idle-ctrl;
 270                         hw-caps-ll-interface;
 271                         hw-caps-temp-alert;
 272                 };
 273
 274                 aes1: aes@4b501000 {
 275                         compatible = "ti,omap4-aes";
 276                         ti,hwmods = "aes1";
 277                         reg = <0x4b501000 0xa0>;
 278                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 279                         dmas = <&sdma 111>, <&sdma 110>;
 280                         dma-names = "tx", "rx";
 281                 };
 282
 283                 aes2: aes@4b701000 {
 284                         compatible = "ti,omap4-aes";
 285                         ti,hwmods = "aes2";
 286                         reg = <0x4b701000 0xa0>;
 287                         interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 288                         dmas = <&sdma 114>, <&sdma 113>;
 289                         dma-names = "tx", "rx";
 290                 };
 291
 292                 des: des@480a5000 {
 293                         compatible = "ti,omap4-des";
 294                         ti,hwmods = "des";
 295                         reg = <0x480a5000 0xa0>;
 296                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 297                         dmas = <&sdma 117>, <&sdma 116>;
 298                         dma-names = "tx", "rx";
 299                 };
 300
 301                 sham: sham@4b100000 {
 302                         compatible = "ti,omap4-sham";
 303                         ti,hwmods = "sham";
 304                         reg = <0x4b100000 0x300>;
 305                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 306                         dmas = <&sdma 119>;
 307                         dma-names = "rx";
 308                 };
 309
 310                 abb_mpu: regulator-abb-mpu {
 311                         compatible = "ti,abb-v2";
 312                         regulator-name = "abb_mpu";
 313                         #address-cells = <0>;
 314                         #size-cells = <0>;
 315                         ti,tranxdone-status-mask = <0x80>;
 316                         clocks = <&sys_clkin_ck>;
 317                         ti,settling-time = <50>;
 318                         ti,clock-cycles = <16>;
 319
 320                         status = "disabled";
 321                 };
 322
 323                 abb_iva: regulator-abb-iva {
 324                         compatible = "ti,abb-v2";
 325                         regulator-name = "abb_iva";
 326                         #address-cells = <0>;
 327                         #size-cells = <0>;
 328                         ti,tranxdone-status-mask = <0x80000000>;
 329                         clocks = <&sys_clkin_ck>;
 330                         ti,settling-time = <50>;
 331                         ti,clock-cycles = <16>;
 332
 333                         status = "disabled";
 334                 };
 335
 336                 sgx_module: target-module@56000000 {
 337                         compatible = "ti,sysc-omap4", "ti,sysc";
 338                         reg = <0x5600fe00 0x4>,
 339                               <0x5600fe10 0x4>;
 340                         reg-names = "rev", "sysc";
 341                         ti,sysc-midle = <SYSC_IDLE_FORCE>,
 342                                         <SYSC_IDLE_NO>,
 343                                         <SYSC_IDLE_SMART>,
 344                                         <SYSC_IDLE_SMART_WKUP>;
 345                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 346                                         <SYSC_IDLE_NO>,
 347                                         <SYSC_IDLE_SMART>,
 348                                         <SYSC_IDLE_SMART_WKUP>;
 349                         clocks = <&l3_gfx_clkctrl OMAP4_GPU_CLKCTRL 0>;
 350                         clock-names = "fck";
 351                         #address-cells = <1>;
 352                         #size-cells = <1>;
 353                         ranges = <0 0x56000000 0x2000000>;
 354
 355                         /*
 356                          * Closed source PowerVR driver, no child device
 357                          * binding or driver in mainline
 358                          */
 359                 };
 360
 361                 dss: dss@58000000 {
 362                         compatible = "ti,omap4-dss";
 363                         reg = <0x58000000 0x80>;
 364                         status = "disabled";
 365                         ti,hwmods = "dss_core";
 366                         clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>;
 367                         clock-names = "fck";
 368                         #address-cells = <1>;
 369                         #size-cells = <1>;
 370                         ranges;
 371
 372                         dispc@58001000 {
 373                                 compatible = "ti,omap4-dispc";
 374                                 reg = <0x58001000 0x1000>;
 375                                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 376                                 ti,hwmods = "dss_dispc";
 377                                 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>;
 378                                 clock-names = "fck";
 379                         };
 380
 381                         rfbi: encoder@58002000  {
 382                                 compatible = "ti,omap4-rfbi";
 383                                 reg = <0x58002000 0x1000>;
 384                                 status = "disabled";
 385                                 ti,hwmods = "dss_rfbi";
 386                                 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>, <&l3_div_ck>;
 387                                 clock-names = "fck", "ick";
 388                         };
 389
 390                         venc: encoder@58003000 {
 391                                 compatible = "ti,omap4-venc";
 392                                 reg = <0x58003000 0x1000>;
 393                                 status = "disabled";
 394                                 ti,hwmods = "dss_venc";
 395                                 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 11>;
 396                                 clock-names = "fck";
 397                         };
 398
 399                         dsi1: encoder@58004000 {
 400                                 compatible = "ti,omap4-dsi";
 401                                 reg = <0x58004000 0x200>,
 402                                       <0x58004200 0x40>,
 403                                       <0x58004300 0x20>;
 404                                 reg-names = "proto", "phy", "pll";
 405                                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 406                                 status = "disabled";
 407                                 ti,hwmods = "dss_dsi1";
 408                                 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
 409                                          <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
 410                                 clock-names = "fck", "sys_clk";
 411                         };
 412
 413                         dsi2: encoder@58005000 {
 414                                 compatible = "ti,omap4-dsi";
 415                                 reg = <0x58005000 0x200>,
 416                                       <0x58005200 0x40>,
 417                                       <0x58005300 0x20>;
 418                                 reg-names = "proto", "phy", "pll";
 419                                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 420                                 status = "disabled";
 421                                 ti,hwmods = "dss_dsi2";
 422                                 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
 423                                          <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
 424                                 clock-names = "fck", "sys_clk";
 425                         };
 426
 427                         hdmi: encoder@58006000 {
 428                                 compatible = "ti,omap4-hdmi";
 429                                 reg = <0x58006000 0x200>,
 430                                       <0x58006200 0x100>,
 431                                       <0x58006300 0x100>,
 432                                       <0x58006400 0x1000>;
 433                                 reg-names = "wp", "pll", "phy", "core";
 434                                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 435                                 status = "disabled";
 436                                 ti,hwmods = "dss_hdmi";
 437                                 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 9>,
 438                                          <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
 439                                 clock-names = "fck", "sys_clk";
 440                                 dmas = <&sdma 76>;
 441                                 dma-names = "audio_tx";
 442                         };
 443                 };
 444         };
 445 };
 446
 447 #include "omap4-l4.dtsi"
 448 #include "omap4-l4-abe.dtsi"
 449 #include "omap44xx-clocks.dtsi"