2 * Device Tree Source for OMAP3 SoC
4 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
11 #include <dt-bindings/bus/ti-sysc.h>
12 #include <dt-bindings/media/omap3-isp.h>
22 /* OMAP3630/OMAP37xx variants OPP50 to OPP130 and OPP1G */
24 operating-points-v2 = <&cpu0_opp_table>;
26 vbb-supply = <&abb_mpu_iva>;
27 clock-latency = <300000>; /* From omap-cpufreq driver */
32 cpu0_opp_table: opp-table {
33 compatible = "operating-points-v2-ti-cpu";
37 opp-hz = /bits/ 64 <300000000>;
39 * we currently only select the max voltage from table
40 * Table 4-19 of the DM3730 Data sheet (SPRS685B)
41 * Format is: cpu0-supply: <target min max>
42 * vbb-supply: <target min max>
44 opp-microvolt = <1012500 1012500 1012500>,
45 <1012500 1012500 1012500>;
47 * first value is silicon revision bit mask
48 * second one is "speed binned" bit mask
50 opp-supported-hw = <0xffffffff 3>;
55 opp-hz = /bits/ 64 <600000000>;
56 opp-microvolt = <1200000 1200000 1200000>,
57 <1200000 1200000 1200000>;
58 opp-supported-hw = <0xffffffff 3>;
62 opp-hz = /bits/ 64 <800000000>;
63 opp-microvolt = <1325000 1325000 1325000>,
64 <1325000 1325000 1325000>;
65 opp-supported-hw = <0xffffffff 3>;
69 opp-hz = /bits/ 64 <1000000000>;
70 opp-microvolt = <1375000 1375000 1375000>,
71 <1375000 1375000 1375000>;
72 /* only on am/dm37x with speed-binned bit set */
73 opp-supported-hw = <0xffffffff 2>;
77 opp_supply_mpu_iva: opp_supply {
78 compatible = "ti,omap-opp-supply";
79 ti,absolute-max-voltage-uv = <1375000>;
83 uart4: serial@49042000 {
84 compatible = "ti,omap3-uart";
85 reg = <0x49042000 0x400>;
87 dmas = <&sdma 81 &sdma 82>;
88 dma-names = "tx", "rx";
90 clock-frequency = <48000000>;
93 abb_mpu_iva: regulator-abb-mpu {
94 compatible = "ti,abb-v1";
95 regulator-name = "abb_mpu_iva";
98 reg = <0x483072f0 0x8>, <0x48306818 0x4>;
99 reg-names = "base-address", "int-address";
100 ti,tranxdone-status-mask = <0x4000000>;
102 ti,settling-time = <30>;
103 ti,clock-cycles = <8>;
105 /*uV ABB efuse rbb_m fbb_m vset_m*/
113 omap3_pmx_core2: pinmux@480025a0 {
114 compatible = "ti,omap3-padconf", "pinctrl-single";
115 reg = <0x480025a0 0x5c>;
116 #address-cells = <1>;
118 #pinctrl-cells = <1>;
119 #interrupt-cells = <1>;
120 interrupt-controller;
121 pinctrl-single,register-width = <16>;
122 pinctrl-single,function-mask = <0xff1f>;
126 compatible = "ti,omap3-isp";
127 reg = <0x480bc000 0x12fc
131 syscon = <&scm_conf 0x2f0>;
132 ti,phy-type = <OMAP3ISP_PHY_TYPE_CSIPHY>;
135 #address-cells = <1>;
140 bandgap: bandgap@48002524 {
141 reg = <0x48002524 0x4>;
142 compatible = "ti,omap36xx-bandgap";
143 #thermal-sensor-cells = <0>;
146 target-module@480cb000 {
147 compatible = "ti,sysc-omap3630-sr", "ti,sysc";
148 ti,hwmods = "smartreflex_core";
149 reg = <0x480cb038 0x4>;
151 ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>;
152 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
157 #address-cells = <1>;
159 ranges = <0 0x480cb000 0x001000>;
161 smartreflex_core: smartreflex@0 {
162 compatible = "ti,omap3-smartreflex-core";
168 target-module@480c9000 {
169 compatible = "ti,sysc-omap3630-sr", "ti,sysc";
170 ti,hwmods = "smartreflex_mpu_iva";
171 reg = <0x480c9038 0x4>;
173 ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>;
174 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
179 #address-cells = <1>;
181 ranges = <0 0x480c9000 0x001000>;
184 smartreflex_mpu_iva: smartreflex@480c9000 {
185 compatible = "ti,omap3-smartreflex-mpu-iva";
192 * Note that the sysconfig register layout is a subset of the
193 * "ti,sysc-omap4" type register with just sidle and midle bits
194 * available while omap34xx has "ti,sysc-omap2" type sysconfig.
196 sgx_module: target-module@50000000 {
197 compatible = "ti,sysc-omap4", "ti,sysc";
198 reg = <0x5000fe00 0x4>,
200 reg-names = "rev", "sysc";
201 ti,sysc-midle = <SYSC_IDLE_FORCE>,
204 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
207 clocks = <&sgx_fck>, <&sgx_ick>;
208 clock-names = "fck", "ick";
209 #address-cells = <1>;
211 ranges = <0 0x50000000 0x2000000>;
214 * Closed source PowerVR driver, no child device
215 * binding or driver in mainline
220 thermal_zones: thermal-zones {
221 #include "omap3-cpu-thermal.dtsi"
226 compatible = "ti,omap3630-sdma", "ti,omap-sdma";
229 /* OMAP3630 needs dss_96m_fck for VENC */
231 clocks = <&dss_tv_fck>, <&dss_96m_fck>;
232 clock-names = "fck", "tv_dac_clk";
238 clocks = <&ssi_ssr_fck>,
241 clock-names = "ssi_ssr_fck",
246 /include/ "omap34xx-omap36xx-clocks.dtsi"
247 /include/ "omap36xx-omap3430es2plus-clocks.dtsi"
248 /include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"
249 /include/ "omap36xx-clocks.dtsi"