1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for OMAP36xx clock data
5 * Copyright (C) 2013 Texas Instruments, Inc.
8 dpll4_ck: dpll4_ck@d00 {
10 compatible = "ti,omap3-dpll-per-j-type-clock";
11 clocks = <&sys_ck>, <&sys_ck>;
12 reg = <0x0d00>, <0x0d20>, <0x0d44>, <0x0d30>;
15 dpll4_m5x2_ck: dpll4_m5x2_ck@d00 {
17 compatible = "ti,hsdiv-gate-clock";
18 clocks = <&dpll4_m5x2_mul_ck>;
19 ti,bit-shift = <0x1e>;
22 ti,set-bit-to-disable;
25 dpll4_m2x2_ck: dpll4_m2x2_ck@d00 {
27 compatible = "ti,hsdiv-gate-clock";
28 clocks = <&dpll4_m2x2_mul_ck>;
29 ti,bit-shift = <0x1b>;
31 ti,set-bit-to-disable;
34 dpll3_m3x2_ck: dpll3_m3x2_ck@d00 {
36 compatible = "ti,hsdiv-gate-clock";
37 clocks = <&dpll3_m3x2_mul_ck>;
40 ti,set-bit-to-disable;
43 dpll4_m3x2_ck: dpll4_m3x2_ck@d00 {
45 compatible = "ti,hsdiv-gate-clock";
46 clocks = <&dpll4_m3x2_mul_ck>;
47 ti,bit-shift = <0x1c>;
49 ti,set-bit-to-disable;
52 dpll4_m6x2_ck: dpll4_m6x2_ck@d00 {
54 compatible = "ti,hsdiv-gate-clock";
55 clocks = <&dpll4_m6x2_mul_ck>;
56 ti,bit-shift = <0x1f>;
58 ti,set-bit-to-disable;
62 compatible = "ti,clksel";
67 uart4_fck: clock-uart4-fck {
69 compatible = "ti,wait-gate-clock";
70 clock-output-names = "uart4_fck";
71 clocks = <&per_48m_fck>;
98 dpll4_clkdm: dpll4_clkdm {
99 compatible = "ti,clockdomain";
100 clocks = <&dpll4_ck>;
103 per_clkdm: per_clkdm {
104 compatible = "ti,clockdomain";
105 clocks = <&uart3_fck>, <&gpio6_dbck>, <&gpio5_dbck>,
106 <&gpio4_dbck>, <&gpio3_dbck>, <&gpio2_dbck>,
107 <&wdt3_fck>, <&gpio6_ick>, <&gpio5_ick>, <&gpio4_ick>,
108 <&gpio3_ick>, <&gpio2_ick>, <&wdt3_ick>, <&uart3_ick>,
109 <&uart4_ick>, <&gpt9_ick>, <&gpt8_ick>, <&gpt7_ick>,
110 <&gpt6_ick>, <&gpt5_ick>, <&gpt4_ick>, <&gpt3_ick>,
111 <&gpt2_ick>, <&mcbsp2_ick>, <&mcbsp3_ick>,
112 <&mcbsp4_ick>, <&uart4_fck>;