1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for OMAP34xx/OMAP35xx SoC
5 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/bus/ti-sysc.h>
9 #include <dt-bindings/media/omap3-isp.h>
16 /* OMAP343x/OMAP35xx variants OPP1-6 */
17 operating-points-v2 = <&cpu0_opp_table>;
19 clock-latency = <300000>; /* From legacy driver */
24 cpu0_opp_table: opp-table {
25 compatible = "operating-points-v2-ti-cpu";
29 opp-hz = /bits/ 64 <125000000>;
31 * we currently only select the max voltage from table
32 * Table 3-3 of the omap3530 Data sheet (SPRS507F).
33 * Format is: <target min max>
35 opp-microvolt = <975000 975000 975000>;
37 * first value is silicon revision bit mask
38 * second one 720MHz Device Identification bit mask
40 opp-supported-hw = <0xffffffff 3>;
44 opp-hz = /bits/ 64 <250000000>;
45 opp-microvolt = <1075000 1075000 1075000>;
46 opp-supported-hw = <0xffffffff 3>;
51 opp-hz = /bits/ 64 <500000000>;
52 opp-microvolt = <1200000 1200000 1200000>;
53 opp-supported-hw = <0xffffffff 3>;
57 opp-hz = /bits/ 64 <550000000>;
58 opp-microvolt = <1275000 1275000 1275000>;
59 opp-supported-hw = <0xffffffff 3>;
63 opp-hz = /bits/ 64 <600000000>;
64 opp-microvolt = <1350000 1350000 1350000>;
65 opp-supported-hw = <0xffffffff 3>;
69 opp-hz = /bits/ 64 <720000000>;
70 opp-microvolt = <1350000 1350000 1350000>;
71 /* only high-speed grade omap3530 devices */
72 opp-supported-hw = <0xffffffff 2>;
78 omap3_pmx_core2: pinmux@480025d8 {
79 compatible = "ti,omap3-padconf", "pinctrl-single";
80 reg = <0x480025d8 0x24>;
84 #interrupt-cells = <1>;
86 pinctrl-single,register-width = <16>;
87 pinctrl-single,function-mask = <0xff1f>;
91 compatible = "ti,omap3-isp";
92 reg = <0x480bc000 0x12fc
96 syscon = <&scm_conf 0x6c>;
97 ti,phy-type = <OMAP3ISP_PHY_TYPE_COMPLEX_IO>;
100 #address-cells = <1>;
105 bandgap: bandgap@48002524 {
106 reg = <0x48002524 0x4>;
107 compatible = "ti,omap34xx-bandgap";
108 #thermal-sensor-cells = <0>;
111 target-module@480cb000 {
112 compatible = "ti,sysc-omap3430-sr", "ti,sysc";
113 ti,hwmods = "smartreflex_core";
114 reg = <0x480cb024 0x4>;
116 ti,sysc-mask = <SYSC_OMAP2_CLOCKACTIVITY>;
119 #address-cells = <1>;
121 ranges = <0 0x480cb000 0x001000>;
123 smartreflex_core: smartreflex@0 {
124 compatible = "ti,omap3-smartreflex-core";
130 target-module@480c9000 {
131 compatible = "ti,sysc-omap3430-sr", "ti,sysc";
132 ti,hwmods = "smartreflex_mpu_iva";
133 reg = <0x480c9024 0x4>;
135 ti,sysc-mask = <SYSC_OMAP2_CLOCKACTIVITY>;
138 #address-cells = <1>;
140 ranges = <0 0x480c9000 0x001000>;
142 smartreflex_mpu_iva: smartreflex@480c9000 {
143 compatible = "ti,omap3-smartreflex-mpu-iva";
150 * On omap34xx the OCP registers do not seem to be accessible
151 * at all unlike on 36xx. Maybe SGX is permanently set to
152 * "OCP bypass mode", or maybe there is OCP_SYSCONFIG that is
153 * write-only at 0x50000e10. We detect SGX based on the SGX
154 * revision register instead of the unreadable OCP revision
155 * register. Also note that on early 34xx es1 revision there
156 * are also different clocks, but we do not have any dts users
159 sgx_module: target-module@50000000 {
160 compatible = "ti,sysc-omap2", "ti,sysc";
161 reg = <0x50000014 0x4>;
163 clocks = <&sgx_fck>, <&sgx_ick>;
164 clock-names = "fck", "ick";
165 #address-cells = <1>;
167 ranges = <0 0x50000000 0x4000>;
170 * Closed source PowerVR driver, no child device
171 * binding or driver in mainline
176 thermal_zones: thermal-zones {
177 #include "omap3-cpu-thermal.dtsi"
184 clocks = <&ssi_ssr_fck>,
187 clock-names = "ssi_ssr_fck",
192 /include/ "omap34xx-omap36xx-clocks.dtsi"
193 /include/ "omap36xx-omap3430es2plus-clocks.dtsi"
194 /include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"