1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for OMAP3 SoC
5 * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/bus/ti-sysc.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/pinctrl/omap.h>
14 compatible = "ti,omap3430", "ti,omap3";
15 interrupt-parent = <&intc>;
37 compatible = "arm,cortex-a8";
44 clock-latency = <300000>; /* From omap-cpufreq driver */
49 compatible = "arm,cortex-a8-pmu";
50 reg = <0x54000000 0x800000>;
52 ti,hwmods = "debugss";
56 * The soc node represents the soc top level view. It is used for IPs
57 * that are not memory mapped in the MPU view or for the MPU itself.
60 compatible = "ti,omap-infra";
62 compatible = "ti,omap3-mpu";
67 compatible = "ti,iva2.2";
71 compatible = "ti,omap3-c64";
77 * XXX: Use a flat representation of the OMAP3 interconnect.
78 * The real OMAP interconnect network is quite complex.
79 * Since it will not bring real advantage to represent that in DT for
80 * the moment, just use a fake OCP bus entry to represent the whole bus
84 compatible = "ti,omap3-l3-smx", "simple-bus";
85 reg = <0x68000000 0x10000>;
90 ti,hwmods = "l3_main";
92 l4_core: l4@48000000 {
93 compatible = "ti,omap3-l4-core", "simple-bus";
96 ranges = <0 0x48000000 0x1000000>;
99 compatible = "ti,omap3-scm", "simple-bus";
100 reg = <0x2000 0x2000>;
101 #address-cells = <1>;
103 ranges = <0 0x2000 0x2000>;
105 omap3_pmx_core: pinmux@30 {
106 compatible = "ti,omap3-padconf",
109 #address-cells = <1>;
111 #pinctrl-cells = <1>;
112 #interrupt-cells = <1>;
113 interrupt-controller;
114 pinctrl-single,register-width = <16>;
115 pinctrl-single,function-mask = <0xff1f>;
118 scm_conf: scm_conf@270 {
119 compatible = "syscon", "simple-bus";
121 #address-cells = <1>;
123 ranges = <0 0x270 0x330>;
125 pbias_regulator: pbias_regulator@2b0 {
126 compatible = "ti,pbias-omap3", "ti,pbias-omap";
128 syscon = <&scm_conf>;
129 pbias_mmc_reg: pbias_mmc_omap2430 {
130 regulator-name = "pbias_mmc_omap2430";
131 regulator-min-microvolt = <1800000>;
132 regulator-max-microvolt = <3000000>;
137 #address-cells = <1>;
142 scm_clockdomains: clockdomains {
145 omap3_pmx_wkup: pinmux@a00 {
146 compatible = "ti,omap3-padconf",
149 #address-cells = <1>;
151 #pinctrl-cells = <1>;
152 #interrupt-cells = <1>;
153 interrupt-controller;
154 pinctrl-single,register-width = <16>;
155 pinctrl-single,function-mask = <0xff1f>;
160 aes1_target: target-module@480a6000 {
161 compatible = "ti,sysc-omap2", "ti,sysc";
162 reg = <0x480a6044 0x4>,
165 reg-names = "rev", "sysc", "syss";
166 ti,sysc-mask = <(SYSC_OMAP2_AUTOIDLE)>;
167 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
171 clocks = <&aes1_ick>;
173 #address-cells = <1>;
175 ranges = <0 0x480a6000 0x2000>;
178 compatible = "ti,omap3-aes";
181 dmas = <&sdma 9 &sdma 10>;
182 dma-names = "tx", "rx";
186 aes2_target: target-module@480c5000 {
187 compatible = "ti,sysc-omap2", "ti,sysc";
188 reg = <0x480c5044 0x4>,
191 reg-names = "rev", "sysc", "syss";
192 ti,sysc-mask = <(SYSC_OMAP2_AUTOIDLE)>;
193 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
197 clocks = <&aes2_ick>;
199 #address-cells = <1>;
201 ranges = <0 0x480c5000 0x2000>;
204 compatible = "ti,omap3-aes";
207 dmas = <&sdma 65 &sdma 66>;
208 dma-names = "tx", "rx";
213 compatible = "ti,omap3-prm";
214 reg = <0x48306000 0x4000>;
218 #address-cells = <1>;
222 prm_clockdomains: clockdomains {
227 compatible = "ti,omap3-cm";
228 reg = <0x48004000 0x4000>;
231 #address-cells = <1>;
235 cm_clockdomains: clockdomains {
239 target-module@48320000 {
240 compatible = "ti,sysc-omap2", "ti,sysc";
241 reg = <0x48320000 0x4>,
243 reg-names = "rev", "sysc";
244 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
246 clocks = <&wkup_32k_fck>, <&omap_32ksync_ick>;
247 clock-names = "fck", "ick";
248 #address-cells = <1>;
250 ranges = <0x0 0x48320000 0x1000>;
252 counter32k: counter@0 {
253 compatible = "ti,omap-counter32k";
258 intc: interrupt-controller@48200000 {
259 compatible = "ti,omap3-intc";
260 interrupt-controller;
261 #interrupt-cells = <1>;
262 reg = <0x48200000 0x1000>;
265 target-module@48056000 {
266 compatible = "ti,sysc-omap2", "ti,sysc";
267 reg = <0x48056000 0x4>,
270 reg-names = "rev", "sysc", "syss";
271 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
273 SYSC_OMAP2_SOFTRESET |
274 SYSC_OMAP2_AUTOIDLE)>;
275 ti,sysc-midle = <SYSC_IDLE_FORCE>,
278 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
282 /* Domains (V, P, C): core, core_pwrdm, core_l3_clkdm */
283 clocks = <&core_l3_ick>;
285 #address-cells = <1>;
287 ranges = <0 0x48056000 0x1000>;
289 sdma: dma-controller@0 {
290 compatible = "ti,omap3430-sdma", "ti,omap-sdma";
302 gpio1: gpio@48310000 {
303 compatible = "ti,omap3-gpio";
304 reg = <0x48310000 0x200>;
310 interrupt-controller;
311 #interrupt-cells = <2>;
314 gpio2: gpio@49050000 {
315 compatible = "ti,omap3-gpio";
316 reg = <0x49050000 0x200>;
321 interrupt-controller;
322 #interrupt-cells = <2>;
325 gpio3: gpio@49052000 {
326 compatible = "ti,omap3-gpio";
327 reg = <0x49052000 0x200>;
332 interrupt-controller;
333 #interrupt-cells = <2>;
336 gpio4: gpio@49054000 {
337 compatible = "ti,omap3-gpio";
338 reg = <0x49054000 0x200>;
343 interrupt-controller;
344 #interrupt-cells = <2>;
347 gpio5: gpio@49056000 {
348 compatible = "ti,omap3-gpio";
349 reg = <0x49056000 0x200>;
354 interrupt-controller;
355 #interrupt-cells = <2>;
358 gpio6: gpio@49058000 {
359 compatible = "ti,omap3-gpio";
360 reg = <0x49058000 0x200>;
365 interrupt-controller;
366 #interrupt-cells = <2>;
369 uart1: serial@4806a000 {
370 compatible = "ti,omap3-uart";
371 reg = <0x4806a000 0x2000>;
372 interrupts-extended = <&intc 72>;
373 dmas = <&sdma 49 &sdma 50>;
374 dma-names = "tx", "rx";
376 clock-frequency = <48000000>;
379 uart2: serial@4806c000 {
380 compatible = "ti,omap3-uart";
381 reg = <0x4806c000 0x400>;
382 interrupts-extended = <&intc 73>;
383 dmas = <&sdma 51 &sdma 52>;
384 dma-names = "tx", "rx";
386 clock-frequency = <48000000>;
389 uart3: serial@49020000 {
390 compatible = "ti,omap3-uart";
391 reg = <0x49020000 0x400>;
392 interrupts-extended = <&intc 74>;
393 dmas = <&sdma 53 &sdma 54>;
394 dma-names = "tx", "rx";
396 clock-frequency = <48000000>;
400 compatible = "ti,omap3-i2c";
401 reg = <0x48070000 0x80>;
403 #address-cells = <1>;
409 compatible = "ti,omap3-i2c";
410 reg = <0x48072000 0x80>;
412 #address-cells = <1>;
418 compatible = "ti,omap3-i2c";
419 reg = <0x48060000 0x80>;
421 #address-cells = <1>;
426 mailbox: mailbox@48094000 {
427 compatible = "ti,omap3-mailbox";
428 ti,hwmods = "mailbox";
429 reg = <0x48094000 0x200>;
432 ti,mbox-num-users = <2>;
433 ti,mbox-num-fifos = <2>;
435 ti,mbox-tx = <0 0 0>;
436 ti,mbox-rx = <1 0 0>;
440 mcspi1: spi@48098000 {
441 compatible = "ti,omap2-mcspi";
442 reg = <0x48098000 0x100>;
444 #address-cells = <1>;
446 ti,hwmods = "mcspi1";
456 dma-names = "tx0", "rx0", "tx1", "rx1",
457 "tx2", "rx2", "tx3", "rx3";
460 mcspi2: spi@4809a000 {
461 compatible = "ti,omap2-mcspi";
462 reg = <0x4809a000 0x100>;
464 #address-cells = <1>;
466 ti,hwmods = "mcspi2";
472 dma-names = "tx0", "rx0", "tx1", "rx1";
475 mcspi3: spi@480b8000 {
476 compatible = "ti,omap2-mcspi";
477 reg = <0x480b8000 0x100>;
479 #address-cells = <1>;
481 ti,hwmods = "mcspi3";
487 dma-names = "tx0", "rx0", "tx1", "rx1";
490 mcspi4: spi@480ba000 {
491 compatible = "ti,omap2-mcspi";
492 reg = <0x480ba000 0x100>;
494 #address-cells = <1>;
496 ti,hwmods = "mcspi4";
498 dmas = <&sdma 70>, <&sdma 71>;
499 dma-names = "tx0", "rx0";
502 hdqw1w: 1w@480b2000 {
503 compatible = "ti,omap3-1w";
504 reg = <0x480b2000 0x1000>;
510 compatible = "ti,omap3-hsmmc";
511 reg = <0x4809c000 0x200>;
515 dmas = <&sdma 61>, <&sdma 62>;
516 dma-names = "tx", "rx";
517 pbias-supply = <&pbias_mmc_reg>;
521 compatible = "ti,omap3-hsmmc";
522 reg = <0x480b4000 0x200>;
525 dmas = <&sdma 47>, <&sdma 48>;
526 dma-names = "tx", "rx";
530 compatible = "ti,omap3-hsmmc";
531 reg = <0x480ad000 0x200>;
534 dmas = <&sdma 77>, <&sdma 78>;
535 dma-names = "tx", "rx";
538 mmu_isp: mmu@480bd400 {
540 compatible = "ti,omap2-iommu";
541 reg = <0x480bd400 0x80>;
543 ti,hwmods = "mmu_isp";
544 ti,#tlb-entries = <8>;
547 mmu_iva: mmu@5d000000 {
549 compatible = "ti,omap2-iommu";
550 reg = <0x5d000000 0x80>;
552 ti,hwmods = "mmu_iva";
557 compatible = "ti,omap3-wdt";
558 reg = <0x48314000 0x80>;
559 ti,hwmods = "wd_timer2";
562 mcbsp1: mcbsp@48074000 {
563 compatible = "ti,omap3-mcbsp";
564 reg = <0x48074000 0xff>;
566 interrupts = <16>, /* OCP compliant interrupt */
567 <59>, /* TX interrupt */
568 <60>; /* RX interrupt */
569 interrupt-names = "common", "tx", "rx";
570 ti,buffer-size = <128>;
571 ti,hwmods = "mcbsp1";
574 dma-names = "tx", "rx";
575 clocks = <&mcbsp1_fck>;
580 /* Likely needs to be tagged disabled on HS devices */
581 rng_target: target-module@480a0000 {
582 compatible = "ti,sysc-omap2", "ti,sysc";
583 reg = <0x480a003c 0x4>,
586 reg-names = "rev", "sysc", "syss";
587 ti,sysc-mask = <(SYSC_OMAP2_AUTOIDLE)>;
588 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
593 #address-cells = <1>;
595 ranges = <0 0x480a0000 0x2000>;
598 compatible = "ti,omap2-rng";
604 mcbsp2: mcbsp@49022000 {
605 compatible = "ti,omap3-mcbsp";
606 reg = <0x49022000 0xff>,
608 reg-names = "mpu", "sidetone";
609 interrupts = <17>, /* OCP compliant interrupt */
610 <62>, /* TX interrupt */
611 <63>, /* RX interrupt */
613 interrupt-names = "common", "tx", "rx", "sidetone";
614 ti,buffer-size = <1280>;
615 ti,hwmods = "mcbsp2", "mcbsp2_sidetone";
618 dma-names = "tx", "rx";
619 clocks = <&mcbsp2_fck>, <&mcbsp2_ick>;
620 clock-names = "fck", "ick";
624 mcbsp3: mcbsp@49024000 {
625 compatible = "ti,omap3-mcbsp";
626 reg = <0x49024000 0xff>,
628 reg-names = "mpu", "sidetone";
629 interrupts = <22>, /* OCP compliant interrupt */
630 <89>, /* TX interrupt */
631 <90>, /* RX interrupt */
633 interrupt-names = "common", "tx", "rx", "sidetone";
634 ti,buffer-size = <128>;
635 ti,hwmods = "mcbsp3", "mcbsp3_sidetone";
638 dma-names = "tx", "rx";
639 clocks = <&mcbsp3_fck>, <&mcbsp3_ick>;
640 clock-names = "fck", "ick";
644 mcbsp4: mcbsp@49026000 {
645 compatible = "ti,omap3-mcbsp";
646 reg = <0x49026000 0xff>;
648 interrupts = <23>, /* OCP compliant interrupt */
649 <54>, /* TX interrupt */
650 <55>; /* RX interrupt */
651 interrupt-names = "common", "tx", "rx";
652 ti,buffer-size = <128>;
653 ti,hwmods = "mcbsp4";
656 dma-names = "tx", "rx";
657 clocks = <&mcbsp4_fck>;
659 #sound-dai-cells = <0>;
663 mcbsp5: mcbsp@48096000 {
664 compatible = "ti,omap3-mcbsp";
665 reg = <0x48096000 0xff>;
667 interrupts = <27>, /* OCP compliant interrupt */
668 <81>, /* TX interrupt */
669 <82>; /* RX interrupt */
670 interrupt-names = "common", "tx", "rx";
671 ti,buffer-size = <128>;
672 ti,hwmods = "mcbsp5";
675 dma-names = "tx", "rx";
676 clocks = <&mcbsp5_fck>;
681 sham: sham@480c3000 {
682 compatible = "ti,omap3-sham";
684 reg = <0x480c3000 0x64>;
690 timer1_target: target-module@48318000 {
691 compatible = "ti,sysc-omap2-timer", "ti,sysc";
692 reg = <0x48318000 0x4>,
695 reg-names = "rev", "sysc", "syss";
696 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
698 SYSC_OMAP2_ENAWAKEUP |
699 SYSC_OMAP2_SOFTRESET |
700 SYSC_OMAP2_AUTOIDLE)>;
701 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
705 clocks = <&gpt1_fck>, <&gpt1_ick>;
706 clock-names = "fck", "ick";
707 #address-cells = <1>;
709 ranges = <0x0 0x48318000 0x1000>;
712 compatible = "ti,omap3430-timer";
714 clocks = <&gpt1_fck>;
721 timer2_target: target-module@49032000 {
722 compatible = "ti,sysc-omap2-timer", "ti,sysc";
723 reg = <0x49032000 0x4>,
726 reg-names = "rev", "sysc", "syss";
727 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
729 SYSC_OMAP2_ENAWAKEUP |
730 SYSC_OMAP2_SOFTRESET |
731 SYSC_OMAP2_AUTOIDLE)>;
732 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
736 clocks = <&gpt2_fck>, <&gpt2_ick>;
737 clock-names = "fck", "ick";
738 #address-cells = <1>;
740 ranges = <0x0 0x49032000 0x1000>;
743 compatible = "ti,omap3430-timer";
749 timer3: timer@49034000 {
750 compatible = "ti,omap3430-timer";
751 reg = <0x49034000 0x400>;
753 ti,hwmods = "timer3";
756 timer4: timer@49036000 {
757 compatible = "ti,omap3430-timer";
758 reg = <0x49036000 0x400>;
760 ti,hwmods = "timer4";
763 timer5: timer@49038000 {
764 compatible = "ti,omap3430-timer";
765 reg = <0x49038000 0x400>;
767 ti,hwmods = "timer5";
771 timer6: timer@4903a000 {
772 compatible = "ti,omap3430-timer";
773 reg = <0x4903a000 0x400>;
775 ti,hwmods = "timer6";
779 timer7: timer@4903c000 {
780 compatible = "ti,omap3430-timer";
781 reg = <0x4903c000 0x400>;
783 ti,hwmods = "timer7";
787 timer8: timer@4903e000 {
788 compatible = "ti,omap3430-timer";
789 reg = <0x4903e000 0x400>;
791 ti,hwmods = "timer8";
796 timer9: timer@49040000 {
797 compatible = "ti,omap3430-timer";
798 reg = <0x49040000 0x400>;
800 ti,hwmods = "timer9";
804 timer10: timer@48086000 {
805 compatible = "ti,omap3430-timer";
806 reg = <0x48086000 0x400>;
808 ti,hwmods = "timer10";
812 timer11: timer@48088000 {
813 compatible = "ti,omap3430-timer";
814 reg = <0x48088000 0x400>;
816 ti,hwmods = "timer11";
820 timer12_target: target-module@48304000 {
821 compatible = "ti,sysc-omap2-timer", "ti,sysc";
822 reg = <0x48304000 0x4>,
825 reg-names = "rev", "sysc", "syss";
826 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
828 SYSC_OMAP2_ENAWAKEUP |
829 SYSC_OMAP2_SOFTRESET |
830 SYSC_OMAP2_AUTOIDLE)>;
831 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
835 clocks = <&gpt12_fck>, <&gpt12_ick>;
836 clock-names = "fck", "ick";
837 #address-cells = <1>;
839 ranges = <0x0 0x48304000 0x1000>;
842 compatible = "ti,omap3430-timer";
850 usbhstll: usbhstll@48062000 {
851 compatible = "ti,usbhs-tll";
852 reg = <0x48062000 0x1000>;
854 ti,hwmods = "usb_tll_hs";
857 usbhshost: usbhshost@48064000 {
858 compatible = "ti,usbhs-host";
859 reg = <0x48064000 0x400>;
860 ti,hwmods = "usb_host_hs";
861 #address-cells = <1>;
865 usbhsohci: ohci@48064400 {
866 compatible = "ti,ohci-omap3";
867 reg = <0x48064400 0x400>;
869 remote-wakeup-connected;
872 usbhsehci: ehci@48064800 {
873 compatible = "ti,ehci-omap";
874 reg = <0x48064800 0x400>;
879 gpmc: gpmc@6e000000 {
880 compatible = "ti,omap3430-gpmc";
882 reg = <0x6e000000 0x02d0>;
887 gpmc,num-waitpins = <4>;
888 #address-cells = <2>;
890 interrupt-controller;
891 #interrupt-cells = <2>;
896 usb_otg_hs: usb_otg_hs@480ab000 {
897 compatible = "ti,omap3-musb";
898 reg = <0x480ab000 0x1000>;
899 interrupts = <92>, <93>;
900 interrupt-names = "mc", "dma";
901 ti,hwmods = "usb_otg_hs";
908 compatible = "ti,omap3-dss";
909 reg = <0x48050000 0x200>;
911 ti,hwmods = "dss_core";
912 clocks = <&dss1_alwon_fck>;
914 #address-cells = <1>;
919 compatible = "ti,omap3-dispc";
920 reg = <0x48050400 0x400>;
922 ti,hwmods = "dss_dispc";
923 clocks = <&dss1_alwon_fck>;
927 dsi: encoder@4804fc00 {
928 compatible = "ti,omap3-dsi";
929 reg = <0x4804fc00 0x200>,
932 reg-names = "proto", "phy", "pll";
935 ti,hwmods = "dss_dsi1";
936 clocks = <&dss1_alwon_fck>, <&dss2_alwon_fck>;
937 clock-names = "fck", "sys_clk";
939 #address-cells = <1>;
943 rfbi: encoder@48050800 {
944 compatible = "ti,omap3-rfbi";
945 reg = <0x48050800 0x100>;
947 ti,hwmods = "dss_rfbi";
948 clocks = <&dss1_alwon_fck>, <&dss_ick>;
949 clock-names = "fck", "ick";
952 venc: encoder@48050c00 {
953 compatible = "ti,omap3-venc";
954 reg = <0x48050c00 0x100>;
956 ti,hwmods = "dss_venc";
957 clocks = <&dss_tv_fck>;
962 ssi: ssi-controller@48058000 {
963 compatible = "ti,omap3-ssi";
968 reg = <0x48058000 0x1000>,
974 interrupt-names = "gdd_mpu";
976 #address-cells = <1>;
980 ssi_port1: ssi-port@4805a000 {
981 compatible = "ti,omap3-ssi-port";
983 reg = <0x4805a000 0x800>,
992 ssi_port2: ssi-port@4805b000 {
993 compatible = "ti,omap3-ssi-port";
995 reg = <0x4805b000 0x800>,
1007 #include "omap3xxx-clocks.dtsi"
1009 /* Preferred always-on timer for clockevent. Some boards must use dmtimer12 */
1011 ti,no-reset-on-init;
1014 assigned-clocks = <&gpt1_fck>;
1015 assigned-clock-parents = <&omap_32k_fck>;