arch/arm/boot/dts/omap3.dtsi

   1 /*
   2  * Device Tree Source for OMAP3 SoC
   3  *
   4  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
   5  *
   6  * This file is licensed under the terms of the GNU General Public License
   7  * version 2.  This program is licensed "as is" without any warranty of any
   8  * kind, whether express or implied.
   9  */
  10
  11 #include <dt-bindings/gpio/gpio.h>
  12 #include <dt-bindings/interrupt-controller/irq.h>
  13 #include <dt-bindings/pinctrl/omap.h>
  14
  15 #include "skeleton.dtsi"
  16
  17 / {
  18         compatible = "ti,omap3430", "ti,omap3";
  19         interrupt-parent = <&intc>;
  20
  21         aliases {
  22                 i2c0 = &i2c1;
  23                 i2c1 = &i2c2;
  24                 i2c2 = &i2c3;
  25                 mmc0 = &mmc1;
  26                 mmc1 = &mmc2;
  27                 mmc2 = &mmc3;
  28                 serial0 = &uart1;
  29                 serial1 = &uart2;
  30                 serial2 = &uart3;
  31         };
  32
  33         cpus {
  34                 #address-cells = <1>;
  35                 #size-cells = <0>;
  36
  37                 cpu@0 {
  38                         compatible = "arm,cortex-a8";
  39                         device_type = "cpu";
  40                         reg = <0x0>;
  41
  42                         clocks = <&dpll1_ck>;
  43                         clock-names = "cpu";
  44
  45                         clock-latency = <300000>; /* From omap-cpufreq driver */
  46                 };
  47         };
  48
  49         pmu {
  50                 compatible = "arm,cortex-a8-pmu";
  51                 reg = <0x54000000 0x800000>;
  52                 interrupts = <3>;
  53                 ti,hwmods = "debugss";
  54         };
  55
  56         /*
  57          * The soc node represents the soc top level view. It is used for IPs
  58          * that are not memory mapped in the MPU view or for the MPU itself.
  59          */
  60         soc {
  61                 compatible = "ti,omap-infra";
  62                 mpu {
  63                         compatible = "ti,omap3-mpu";
  64                         ti,hwmods = "mpu";
  65                 };
  66
  67                 iva: iva {
  68                         compatible = "ti,iva2.2";
  69                         ti,hwmods = "iva";
  70
  71                         dsp {
  72                                 compatible = "ti,omap3-c64";
  73                         };
  74                 };
  75         };
  76
  77         /*
  78          * XXX: Use a flat representation of the OMAP3 interconnect.
  79          * The real OMAP interconnect network is quite complex.
  80          * Since it will not bring real advantage to represent that in DT for
  81          * the moment, just use a fake OCP bus entry to represent the whole bus
  82          * hierarchy.
  83          */
  84         ocp {
  85                 compatible = "ti,omap3-l3-smx", "simple-bus";
  86                 reg = <0x68000000 0x10000>;
  87                 interrupts = <9 10>;
  88                 #address-cells = <1>;
  89                 #size-cells = <1>;
  90                 ranges;
  91                 ti,hwmods = "l3_main";
  92
  93                 l4_core: l4@48000000 {
  94                         compatible = "ti,omap3-l4-core", "simple-bus";
  95                         #address-cells = <1>;
  96                         #size-cells = <1>;
  97                         ranges = <0 0x48000000 0x1000000>;
  98
  99                         scm: scm@2000 {
 100                                 compatible = "ti,omap3-scm", "simple-bus";
 101                                 reg = <0x2000 0x2000>;
 102                                 #address-cells = <1>;
 103                                 #size-cells = <1>;
 104                                 ranges = <0 0x2000 0x2000>;
 105
 106                                 omap3_pmx_core: pinmux@30 {
 107                                         compatible = "ti,omap3-padconf",
 108                                                      "pinctrl-single";
 109                                         reg = <0x30 0x238>;
 110                                         #address-cells = <1>;
 111                                         #size-cells = <0>;
 112                                         #interrupt-cells = <1>;
 113                                         interrupt-controller;
 114                                         pinctrl-single,register-width = <16>;
 115                                         pinctrl-single,function-mask = <0xff1f>;
 116                                 };
 117
 118                                 scm_conf: scm_conf@270 {
 119                                         compatible = "syscon", "simple-bus";
 120                                         reg = <0x270 0x330>;
 121                                         #address-cells = <1>;
 122                                         #size-cells = <1>;
 123                                         ranges = <0 0x270 0x330>;
 124
 125                                         pbias_regulator: pbias_regulator {
 126                                                 compatible = "ti,pbias-omap3", "ti,pbias-omap";
 127                                                 reg = <0x2b0 0x4>;
 128                                                 syscon = <&scm_conf>;
 129                                                 pbias_mmc_reg: pbias_mmc_omap2430 {
 130                                                         regulator-name = "pbias_mmc_omap2430";
 131                                                         regulator-min-microvolt = <1800000>;
 132                                                         regulator-max-microvolt = <3000000>;
 133                                                 };
 134                                         };
 135
 136                                         scm_clocks: clocks {
 137                                                 #address-cells = <1>;
 138                                                 #size-cells = <0>;
 139                                         };
 140                                 };
 141
 142                                 scm_clockdomains: clockdomains {
 143                                 };
 144
 145                                 omap3_pmx_wkup: pinmux@a00 {
 146                                         compatible = "ti,omap3-padconf",
 147                                                      "pinctrl-single";
 148                                         reg = <0xa00 0x5c>;
 149                                         #address-cells = <1>;
 150                                         #size-cells = <0>;
 151                                         #interrupt-cells = <1>;
 152                                         interrupt-controller;
 153                                         pinctrl-single,register-width = <16>;
 154                                         pinctrl-single,function-mask = <0xff1f>;
 155                                 };
 156                         };
 157                 };
 158
 159                 aes: aes@480c5000 {
 160                         compatible = "ti,omap3-aes";
 161                         ti,hwmods = "aes";
 162                         reg = <0x480c5000 0x50>;
 163                         interrupts = <0>;
 164                         dmas = <&sdma 65 &sdma 66>;
 165                         dma-names = "tx", "rx";
 166                 };
 167
 168                 prm: prm@48306000 {
 169                         compatible = "ti,omap3-prm";
 170                         reg = <0x48306000 0x4000>;
 171                         interrupts = <11>;
 172
 173                         prm_clocks: clocks {
 174                                 #address-cells = <1>;
 175                                 #size-cells = <0>;
 176                         };
 177
 178                         prm_clockdomains: clockdomains {
 179                         };
 180                 };
 181
 182                 cm: cm@48004000 {
 183                         compatible = "ti,omap3-cm";
 184                         reg = <0x48004000 0x4000>;
 185
 186                         cm_clocks: clocks {
 187                                 #address-cells = <1>;
 188                                 #size-cells = <0>;
 189                         };
 190
 191                         cm_clockdomains: clockdomains {
 192                         };
 193                 };
 194
 195                 counter32k: counter@48320000 {
 196                         compatible = "ti,omap-counter32k";
 197                         reg = <0x48320000 0x20>;
 198                         ti,hwmods = "counter_32k";
 199                 };
 200
 201                 intc: interrupt-controller@48200000 {
 202                         compatible = "ti,omap3-intc";
 203                         interrupt-controller;
 204                         #interrupt-cells = <1>;
 205                         reg = <0x48200000 0x1000>;
 206                 };
 207
 208                 sdma: dma-controller@48056000 {
 209                         compatible = "ti,omap3630-sdma", "ti,omap3430-sdma";
 210                         reg = <0x48056000 0x1000>;
 211                         interrupts = <12>,
 212                                      <13>,
 213                                      <14>,
 214                                      <15>;
 215                         #dma-cells = <1>;
 216                         dma-channels = <32>;
 217                         dma-requests = <96>;
 218                 };
 219
 220                 gpio1: gpio@48310000 {
 221                         compatible = "ti,omap3-gpio";
 222                         reg = <0x48310000 0x200>;
 223                         interrupts = <29>;
 224                         ti,hwmods = "gpio1";
 225                         ti,gpio-always-on;
 226                         gpio-controller;
 227                         #gpio-cells = <2>;
 228                         interrupt-controller;
 229                         #interrupt-cells = <2>;
 230                 };
 231
 232                 gpio2: gpio@49050000 {
 233                         compatible = "ti,omap3-gpio";
 234                         reg = <0x49050000 0x200>;
 235                         interrupts = <30>;
 236                         ti,hwmods = "gpio2";
 237                         gpio-controller;
 238                         #gpio-cells = <2>;
 239                         interrupt-controller;
 240                         #interrupt-cells = <2>;
 241                 };
 242
 243                 gpio3: gpio@49052000 {
 244                         compatible = "ti,omap3-gpio";
 245                         reg = <0x49052000 0x200>;
 246                         interrupts = <31>;
 247                         ti,hwmods = "gpio3";
 248                         gpio-controller;
 249                         #gpio-cells = <2>;
 250                         interrupt-controller;
 251                         #interrupt-cells = <2>;
 252                 };
 253
 254                 gpio4: gpio@49054000 {
 255                         compatible = "ti,omap3-gpio";
 256                         reg = <0x49054000 0x200>;
 257                         interrupts = <32>;
 258                         ti,hwmods = "gpio4";
 259                         gpio-controller;
 260                         #gpio-cells = <2>;
 261                         interrupt-controller;
 262                         #interrupt-cells = <2>;
 263                 };
 264
 265                 gpio5: gpio@49056000 {
 266                         compatible = "ti,omap3-gpio";
 267                         reg = <0x49056000 0x200>;
 268                         interrupts = <33>;
 269                         ti,hwmods = "gpio5";
 270                         gpio-controller;
 271                         #gpio-cells = <2>;
 272                         interrupt-controller;
 273                         #interrupt-cells = <2>;
 274                 };
 275
 276                 gpio6: gpio@49058000 {
 277                         compatible = "ti,omap3-gpio";
 278                         reg = <0x49058000 0x200>;
 279                         interrupts = <34>;
 280                         ti,hwmods = "gpio6";
 281                         gpio-controller;
 282                         #gpio-cells = <2>;
 283                         interrupt-controller;
 284                         #interrupt-cells = <2>;
 285                 };
 286
 287                 uart1: serial@4806a000 {
 288                         compatible = "ti,omap3-uart";
 289                         reg = <0x4806a000 0x2000>;
 290                         interrupts-extended = <&intc 72>;
 291                         dmas = <&sdma 49 &sdma 50>;
 292                         dma-names = "tx", "rx";
 293                         ti,hwmods = "uart1";
 294                         clock-frequency = <48000000>;
 295                 };
 296
 297                 uart2: serial@4806c000 {
 298                         compatible = "ti,omap3-uart";
 299                         reg = <0x4806c000 0x400>;
 300                         interrupts-extended = <&intc 73>;
 301                         dmas = <&sdma 51 &sdma 52>;
 302                         dma-names = "tx", "rx";
 303                         ti,hwmods = "uart2";
 304                         clock-frequency = <48000000>;
 305                 };
 306
 307                 uart3: serial@49020000 {
 308                         compatible = "ti,omap3-uart";
 309                         reg = <0x49020000 0x400>;
 310                         interrupts-extended = <&intc 74>;
 311                         dmas = <&sdma 53 &sdma 54>;
 312                         dma-names = "tx", "rx";
 313                         ti,hwmods = "uart3";
 314                         clock-frequency = <48000000>;
 315                 };
 316
 317                 i2c1: i2c@48070000 {
 318                         compatible = "ti,omap3-i2c";
 319                         reg = <0x48070000 0x80>;
 320                         interrupts = <56>;
 321                         dmas = <&sdma 27 &sdma 28>;
 322                         dma-names = "tx", "rx";
 323                         #address-cells = <1>;
 324                         #size-cells = <0>;
 325                         ti,hwmods = "i2c1";
 326                 };
 327
 328                 i2c2: i2c@48072000 {
 329                         compatible = "ti,omap3-i2c";
 330                         reg = <0x48072000 0x80>;
 331                         interrupts = <57>;
 332                         dmas = <&sdma 29 &sdma 30>;
 333                         dma-names = "tx", "rx";
 334                         #address-cells = <1>;
 335                         #size-cells = <0>;
 336                         ti,hwmods = "i2c2";
 337                 };
 338
 339                 i2c3: i2c@48060000 {
 340                         compatible = "ti,omap3-i2c";
 341                         reg = <0x48060000 0x80>;
 342                         interrupts = <61>;
 343                         dmas = <&sdma 25 &sdma 26>;
 344                         dma-names = "tx", "rx";
 345                         #address-cells = <1>;
 346                         #size-cells = <0>;
 347                         ti,hwmods = "i2c3";
 348                 };
 349
 350                 mailbox: mailbox@48094000 {
 351                         compatible = "ti,omap3-mailbox";
 352                         ti,hwmods = "mailbox";
 353                         reg = <0x48094000 0x200>;
 354                         interrupts = <26>;
 355                         #mbox-cells = <1>;
 356                         ti,mbox-num-users = <2>;
 357                         ti,mbox-num-fifos = <2>;
 358                         mbox_dsp: dsp {
 359                                 ti,mbox-tx = <0 0 0>;
 360                                 ti,mbox-rx = <1 0 0>;
 361                         };
 362                 };
 363
 364                 mcspi1: spi@48098000 {
 365                         compatible = "ti,omap2-mcspi";
 366                         reg = <0x48098000 0x100>;
 367                         interrupts = <65>;
 368                         #address-cells = <1>;
 369                         #size-cells = <0>;
 370                         ti,hwmods = "mcspi1";
 371                         ti,spi-num-cs = <4>;
 372                         dmas = <&sdma 35>,
 373                                <&sdma 36>,
 374                                <&sdma 37>,
 375                                <&sdma 38>,
 376                                <&sdma 39>,
 377                                <&sdma 40>,
 378                                <&sdma 41>,
 379                                <&sdma 42>;
 380                         dma-names = "tx0", "rx0", "tx1", "rx1",
 381                                     "tx2", "rx2", "tx3", "rx3";
 382                 };
 383
 384                 mcspi2: spi@4809a000 {
 385                         compatible = "ti,omap2-mcspi";
 386                         reg = <0x4809a000 0x100>;
 387                         interrupts = <66>;
 388                         #address-cells = <1>;
 389                         #size-cells = <0>;
 390                         ti,hwmods = "mcspi2";
 391                         ti,spi-num-cs = <2>;
 392                         dmas = <&sdma 43>,
 393                                <&sdma 44>,
 394                                <&sdma 45>,
 395                                <&sdma 46>;
 396                         dma-names = "tx0", "rx0", "tx1", "rx1";
 397                 };
 398
 399                 mcspi3: spi@480b8000 {
 400                         compatible = "ti,omap2-mcspi";
 401                         reg = <0x480b8000 0x100>;
 402                         interrupts = <91>;
 403                         #address-cells = <1>;
 404                         #size-cells = <0>;
 405                         ti,hwmods = "mcspi3";
 406                         ti,spi-num-cs = <2>;
 407                         dmas = <&sdma 15>,
 408                                <&sdma 16>,
 409                                <&sdma 23>,
 410                                <&sdma 24>;
 411                         dma-names = "tx0", "rx0", "tx1", "rx1";
 412                 };
 413
 414                 mcspi4: spi@480ba000 {
 415                         compatible = "ti,omap2-mcspi";
 416                         reg = <0x480ba000 0x100>;
 417                         interrupts = <48>;
 418                         #address-cells = <1>;
 419                         #size-cells = <0>;
 420                         ti,hwmods = "mcspi4";
 421                         ti,spi-num-cs = <1>;
 422                         dmas = <&sdma 70>, <&sdma 71>;
 423                         dma-names = "tx0", "rx0";
 424                 };
 425
 426                 hdqw1w: 1w@480b2000 {
 427                         compatible = "ti,omap3-1w";
 428                         reg = <0x480b2000 0x1000>;
 429                         interrupts = <58>;
 430                         ti,hwmods = "hdq1w";
 431                 };
 432
 433                 mmc1: mmc@4809c000 {
 434                         compatible = "ti,omap3-hsmmc";
 435                         reg = <0x4809c000 0x200>;
 436                         interrupts = <83>;
 437                         ti,hwmods = "mmc1";
 438                         ti,dual-volt;
 439                         dmas = <&sdma 61>, <&sdma 62>;
 440                         dma-names = "tx", "rx";
 441                         pbias-supply = <&pbias_mmc_reg>;
 442                 };
 443
 444                 mmc2: mmc@480b4000 {
 445                         compatible = "ti,omap3-hsmmc";
 446                         reg = <0x480b4000 0x200>;
 447                         interrupts = <86>;
 448                         ti,hwmods = "mmc2";
 449                         dmas = <&sdma 47>, <&sdma 48>;
 450                         dma-names = "tx", "rx";
 451                 };
 452
 453                 mmc3: mmc@480ad000 {
 454                         compatible = "ti,omap3-hsmmc";
 455                         reg = <0x480ad000 0x200>;
 456                         interrupts = <94>;
 457                         ti,hwmods = "mmc3";
 458                         dmas = <&sdma 77>, <&sdma 78>;
 459                         dma-names = "tx", "rx";
 460                 };
 461
 462                 mmu_isp: mmu@480bd400 {
 463                         #iommu-cells = <0>;
 464                         compatible = "ti,omap2-iommu";
 465                         reg = <0x480bd400 0x80>;
 466                         interrupts = <24>;
 467                         ti,hwmods = "mmu_isp";
 468                         ti,#tlb-entries = <8>;
 469                 };
 470
 471                 mmu_iva: mmu@5d000000 {
 472                         #iommu-cells = <0>;
 473                         compatible = "ti,omap2-iommu";
 474                         reg = <0x5d000000 0x80>;
 475                         interrupts = <28>;
 476                         ti,hwmods = "mmu_iva";
 477                         status = "disabled";
 478                 };
 479
 480                 wdt2: wdt@48314000 {
 481                         compatible = "ti,omap3-wdt";
 482                         reg = <0x48314000 0x80>;
 483                         ti,hwmods = "wd_timer2";
 484                 };
 485
 486                 mcbsp1: mcbsp@48074000 {
 487                         compatible = "ti,omap3-mcbsp";
 488                         reg = <0x48074000 0xff>;
 489                         reg-names = "mpu";
 490                         interrupts = <16>, /* OCP compliant interrupt */
 491                                      <59>, /* TX interrupt */
 492                                      <60>; /* RX interrupt */
 493                         interrupt-names = "common", "tx", "rx";
 494                         ti,buffer-size = <128>;
 495                         ti,hwmods = "mcbsp1";
 496                         dmas = <&sdma 31>,
 497                                <&sdma 32>;
 498                         dma-names = "tx", "rx";
 499                         status = "disabled";
 500                 };
 501
 502                 mcbsp2: mcbsp@49022000 {
 503                         compatible = "ti,omap3-mcbsp";
 504                         reg = <0x49022000 0xff>,
 505                               <0x49028000 0xff>;
 506                         reg-names = "mpu", "sidetone";
 507                         interrupts = <17>, /* OCP compliant interrupt */
 508                                      <62>, /* TX interrupt */
 509                                      <63>, /* RX interrupt */
 510                                      <4>;  /* Sidetone */
 511                         interrupt-names = "common", "tx", "rx", "sidetone";
 512                         ti,buffer-size = <1280>;
 513                         ti,hwmods = "mcbsp2", "mcbsp2_sidetone";
 514                         dmas = <&sdma 33>,
 515                                <&sdma 34>;
 516                         dma-names = "tx", "rx";
 517                         status = "disabled";
 518                 };
 519
 520                 mcbsp3: mcbsp@49024000 {
 521                         compatible = "ti,omap3-mcbsp";
 522                         reg = <0x49024000 0xff>,
 523                               <0x4902a000 0xff>;
 524                         reg-names = "mpu", "sidetone";
 525                         interrupts = <22>, /* OCP compliant interrupt */
 526                                      <89>, /* TX interrupt */
 527                                      <90>, /* RX interrupt */
 528                                      <5>;  /* Sidetone */
 529                         interrupt-names = "common", "tx", "rx", "sidetone";
 530                         ti,buffer-size = <128>;
 531                         ti,hwmods = "mcbsp3", "mcbsp3_sidetone";
 532                         dmas = <&sdma 17>,
 533                                <&sdma 18>;
 534                         dma-names = "tx", "rx";
 535                         status = "disabled";
 536                 };
 537
 538                 mcbsp4: mcbsp@49026000 {
 539                         compatible = "ti,omap3-mcbsp";
 540                         reg = <0x49026000 0xff>;
 541                         reg-names = "mpu";
 542                         interrupts = <23>, /* OCP compliant interrupt */
 543                                      <54>, /* TX interrupt */
 544                                      <55>; /* RX interrupt */
 545                         interrupt-names = "common", "tx", "rx";
 546                         ti,buffer-size = <128>;
 547                         ti,hwmods = "mcbsp4";
 548                         dmas = <&sdma 19>,
 549                                <&sdma 20>;
 550                         dma-names = "tx", "rx";
 551                         status = "disabled";
 552                 };
 553
 554                 mcbsp5: mcbsp@48096000 {
 555                         compatible = "ti,omap3-mcbsp";
 556                         reg = <0x48096000 0xff>;
 557                         reg-names = "mpu";
 558                         interrupts = <27>, /* OCP compliant interrupt */
 559                                      <81>, /* TX interrupt */
 560                                      <82>; /* RX interrupt */
 561                         interrupt-names = "common", "tx", "rx";
 562                         ti,buffer-size = <128>;
 563                         ti,hwmods = "mcbsp5";
 564                         dmas = <&sdma 21>,
 565                                <&sdma 22>;
 566                         dma-names = "tx", "rx";
 567                         status = "disabled";
 568                 };
 569
 570                 sham: sham@480c3000 {
 571                         compatible = "ti,omap3-sham";
 572                         ti,hwmods = "sham";
 573                         reg = <0x480c3000 0x64>;
 574                         interrupts = <49>;
 575                         dmas = <&sdma 69>;
 576                         dma-names = "rx";
 577                 };
 578
 579                 smartreflex_core: smartreflex@480cb000 {
 580                         compatible = "ti,omap3-smartreflex-core";
 581                         ti,hwmods = "smartreflex_core";
 582                         reg = <0x480cb000 0x400>;
 583                         interrupts = <19>;
 584                 };
 585
 586                 smartreflex_mpu_iva: smartreflex@480c9000 {
 587                         compatible = "ti,omap3-smartreflex-iva";
 588                         ti,hwmods = "smartreflex_mpu_iva";
 589                         reg = <0x480c9000 0x400>;
 590                         interrupts = <18>;
 591                 };
 592
 593                 timer1: timer@48318000 {
 594                         compatible = "ti,omap3430-timer";
 595                         reg = <0x48318000 0x400>;
 596                         interrupts = <37>;
 597                         ti,hwmods = "timer1";
 598                         ti,timer-alwon;
 599                 };
 600
 601                 timer2: timer@49032000 {
 602                         compatible = "ti,omap3430-timer";
 603                         reg = <0x49032000 0x400>;
 604                         interrupts = <38>;
 605                         ti,hwmods = "timer2";
 606                 };
 607
 608                 timer3: timer@49034000 {
 609                         compatible = "ti,omap3430-timer";
 610                         reg = <0x49034000 0x400>;
 611                         interrupts = <39>;
 612                         ti,hwmods = "timer3";
 613                 };
 614
 615                 timer4: timer@49036000 {
 616                         compatible = "ti,omap3430-timer";
 617                         reg = <0x49036000 0x400>;
 618                         interrupts = <40>;
 619                         ti,hwmods = "timer4";
 620                 };
 621
 622                 timer5: timer@49038000 {
 623                         compatible = "ti,omap3430-timer";
 624                         reg = <0x49038000 0x400>;
 625                         interrupts = <41>;
 626                         ti,hwmods = "timer5";
 627                         ti,timer-dsp;
 628                 };
 629
 630                 timer6: timer@4903a000 {
 631                         compatible = "ti,omap3430-timer";
 632                         reg = <0x4903a000 0x400>;
 633                         interrupts = <42>;
 634                         ti,hwmods = "timer6";
 635                         ti,timer-dsp;
 636                 };
 637
 638                 timer7: timer@4903c000 {
 639                         compatible = "ti,omap3430-timer";
 640                         reg = <0x4903c000 0x400>;
 641                         interrupts = <43>;
 642                         ti,hwmods = "timer7";
 643                         ti,timer-dsp;
 644                 };
 645
 646                 timer8: timer@4903e000 {
 647                         compatible = "ti,omap3430-timer";
 648                         reg = <0x4903e000 0x400>;
 649                         interrupts = <44>;
 650                         ti,hwmods = "timer8";
 651                         ti,timer-pwm;
 652                         ti,timer-dsp;
 653                 };
 654
 655                 timer9: timer@49040000 {
 656                         compatible = "ti,omap3430-timer";
 657                         reg = <0x49040000 0x400>;
 658                         interrupts = <45>;
 659                         ti,hwmods = "timer9";
 660                         ti,timer-pwm;
 661                 };
 662
 663                 timer10: timer@48086000 {
 664                         compatible = "ti,omap3430-timer";
 665                         reg = <0x48086000 0x400>;
 666                         interrupts = <46>;
 667                         ti,hwmods = "timer10";
 668                         ti,timer-pwm;
 669                 };
 670
 671                 timer11: timer@48088000 {
 672                         compatible = "ti,omap3430-timer";
 673                         reg = <0x48088000 0x400>;
 674                         interrupts = <47>;
 675                         ti,hwmods = "timer11";
 676                         ti,timer-pwm;
 677                 };
 678
 679                 timer12: timer@48304000 {
 680                         compatible = "ti,omap3430-timer";
 681                         reg = <0x48304000 0x400>;
 682                         interrupts = <95>;
 683                         ti,hwmods = "timer12";
 684                         ti,timer-alwon;
 685                         ti,timer-secure;
 686                 };
 687
 688                 usbhstll: usbhstll@48062000 {
 689                         compatible = "ti,usbhs-tll";
 690                         reg = <0x48062000 0x1000>;
 691                         interrupts = <78>;
 692                         ti,hwmods = "usb_tll_hs";
 693                 };
 694
 695                 usbhshost: usbhshost@48064000 {
 696                         compatible = "ti,usbhs-host";
 697                         reg = <0x48064000 0x400>;
 698                         ti,hwmods = "usb_host_hs";
 699                         #address-cells = <1>;
 700                         #size-cells = <1>;
 701                         ranges;
 702
 703                         usbhsohci: ohci@48064400 {
 704                                 compatible = "ti,ohci-omap3";
 705                                 reg = <0x48064400 0x400>;
 706                                 interrupt-parent = <&intc>;
 707                                 interrupts = <76>;
 708                         };
 709
 710                         usbhsehci: ehci@48064800 {
 711                                 compatible = "ti,ehci-omap";
 712                                 reg = <0x48064800 0x400>;
 713                                 interrupt-parent = <&intc>;
 714                                 interrupts = <77>;
 715                         };
 716                 };
 717
 718                 gpmc: gpmc@6e000000 {
 719                         compatible = "ti,omap3430-gpmc";
 720                         ti,hwmods = "gpmc";
 721                         reg = <0x6e000000 0x02d0>;
 722                         interrupts = <20>;
 723                         gpmc,num-cs = <8>;
 724                         gpmc,num-waitpins = <4>;
 725                         #address-cells = <2>;
 726                         #size-cells = <1>;
 727                 };
 728
 729                 usb_otg_hs: usb_otg_hs@480ab000 {
 730                         compatible = "ti,omap3-musb";
 731                         reg = <0x480ab000 0x1000>;
 732                         interrupts = <92>, <93>;
 733                         interrupt-names = "mc", "dma";
 734                         ti,hwmods = "usb_otg_hs";
 735                         multipoint = <1>;
 736                         num-eps = <16>;
 737                         ram-bits = <12>;
 738                 };
 739
 740                 dss: dss@48050000 {
 741                         compatible = "ti,omap3-dss";
 742                         reg = <0x48050000 0x200>;
 743                         status = "disabled";
 744                         ti,hwmods = "dss_core";
 745                         clocks = <&dss1_alwon_fck>;
 746                         clock-names = "fck";
 747                         #address-cells = <1>;
 748                         #size-cells = <1>;
 749                         ranges;
 750
 751                         dispc@48050400 {
 752                                 compatible = "ti,omap3-dispc";
 753                                 reg = <0x48050400 0x400>;
 754                                 interrupts = <25>;
 755                                 ti,hwmods = "dss_dispc";
 756                                 clocks = <&dss1_alwon_fck>;
 757                                 clock-names = "fck";
 758                         };
 759
 760                         dsi: encoder@4804fc00 {
 761                                 compatible = "ti,omap3-dsi";
 762                                 reg = <0x4804fc00 0x200>,
 763                                       <0x4804fe00 0x40>,
 764                                       <0x4804ff00 0x20>;
 765                                 reg-names = "proto", "phy", "pll";
 766                                 interrupts = <25>;
 767                                 status = "disabled";
 768                                 ti,hwmods = "dss_dsi1";
 769                                 clocks = <&dss1_alwon_fck>, <&dss2_alwon_fck>;
 770                                 clock-names = "fck", "sys_clk";
 771                         };
 772
 773                         rfbi: encoder@48050800 {
 774                                 compatible = "ti,omap3-rfbi";
 775                                 reg = <0x48050800 0x100>;
 776                                 status = "disabled";
 777                                 ti,hwmods = "dss_rfbi";
 778                                 clocks = <&dss1_alwon_fck>, <&dss_ick>;
 779                                 clock-names = "fck", "ick";
 780                         };
 781
 782                         venc: encoder@48050c00 {
 783                                 compatible = "ti,omap3-venc";
 784                                 reg = <0x48050c00 0x100>;
 785                                 status = "disabled";
 786                                 ti,hwmods = "dss_venc";
 787                                 clocks = <&dss_tv_fck>;
 788                                 clock-names = "fck";
 789                         };
 790                 };
 791
 792                 ssi: ssi-controller@48058000 {
 793                         compatible = "ti,omap3-ssi";
 794                         ti,hwmods = "ssi";
 795
 796                         status = "disabled";
 797
 798                         reg = <0x48058000 0x1000>,
 799                               <0x48059000 0x1000>;
 800                         reg-names = "sys",
 801                                     "gdd";
 802
 803                         interrupts = <71>;
 804                         interrupt-names = "gdd_mpu";
 805
 806                         #address-cells = <1>;
 807                         #size-cells = <1>;
 808                         ranges;
 809
 810                         ssi_port1: ssi-port@4805a000 {
 811                                 compatible = "ti,omap3-ssi-port";
 812
 813                                 reg = <0x4805a000 0x800>,
 814                                       <0x4805a800 0x800>;
 815                                 reg-names = "tx",
 816                                             "rx";
 817
 818                                 interrupt-parent = <&intc>;
 819                                 interrupts = <67>,
 820                                              <68>;
 821                         };
 822
 823                         ssi_port2: ssi-port@4805b000 {
 824                                 compatible = "ti,omap3-ssi-port";
 825
 826                                 reg = <0x4805b000 0x800>,
 827                                       <0x4805b800 0x800>;
 828                                 reg-names = "tx",
 829                                             "rx";
 830
 831                                 interrupt-parent = <&intc>;
 832                                 interrupts = <69>,
 833                                              <70>;
 834                         };
 835                 };
 836         };
 837 };
 838
 839 /include/ "omap3xxx-clocks.dtsi"