arch/arm/boot/dts/omap3.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Device Tree Source for OMAP3 SoC
   4  *
   5  * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
   6  */
   7
   8 #include <dt-bindings/bus/ti-sysc.h>
   9 #include <dt-bindings/gpio/gpio.h>
  10 #include <dt-bindings/interrupt-controller/irq.h>
  11 #include <dt-bindings/pinctrl/omap.h>
  12
  13 / {
  14         compatible = "ti,omap3430", "ti,omap3";
  15         interrupt-parent = <&intc>;
  16         #address-cells = <1>;
  17         #size-cells = <1>;
  18         chosen { };
  19
  20         aliases {
  21                 i2c0 = &i2c1;
  22                 i2c1 = &i2c2;
  23                 i2c2 = &i2c3;
  24                 mmc0 = &mmc1;
  25                 mmc1 = &mmc2;
  26                 mmc2 = &mmc3;
  27                 serial0 = &uart1;
  28                 serial1 = &uart2;
  29                 serial2 = &uart3;
  30         };
  31
  32         cpus {
  33                 #address-cells = <1>;
  34                 #size-cells = <0>;
  35
  36                 cpu@0 {
  37                         compatible = "arm,cortex-a8";
  38                         device_type = "cpu";
  39                         reg = <0x0>;
  40
  41                         clocks = <&dpll1_ck>;
  42                         clock-names = "cpu";
  43
  44                         clock-latency = <300000>; /* From omap-cpufreq driver */
  45                 };
  46         };
  47
  48         pmu@54000000 {
  49                 compatible = "arm,cortex-a8-pmu";
  50                 reg = <0x54000000 0x800000>;
  51                 interrupts = <3>;
  52                 ti,hwmods = "debugss";
  53         };
  54
  55         /*
  56          * The soc node represents the soc top level view. It is used for IPs
  57          * that are not memory mapped in the MPU view or for the MPU itself.
  58          */
  59         soc {
  60                 compatible = "ti,omap-infra";
  61                 mpu {
  62                         compatible = "ti,omap3-mpu";
  63                         ti,hwmods = "mpu";
  64                 };
  65
  66                 iva: iva {
  67                         compatible = "ti,iva2.2";
  68                         ti,hwmods = "iva";
  69
  70                         dsp {
  71                                 compatible = "ti,omap3-c64";
  72                         };
  73                 };
  74         };
  75
  76         /*
  77          * XXX: Use a flat representation of the OMAP3 interconnect.
  78          * The real OMAP interconnect network is quite complex.
  79          * Since it will not bring real advantage to represent that in DT for
  80          * the moment, just use a fake OCP bus entry to represent the whole bus
  81          * hierarchy.
  82          */
  83         ocp@68000000 {
  84                 compatible = "ti,omap3-l3-smx", "simple-bus";
  85                 reg = <0x68000000 0x10000>;
  86                 interrupts = <9 10>;
  87                 #address-cells = <1>;
  88                 #size-cells = <1>;
  89                 ranges;
  90                 ti,hwmods = "l3_main";
  91
  92                 l4_core: l4@48000000 {
  93                         compatible = "ti,omap3-l4-core", "simple-bus";
  94                         #address-cells = <1>;
  95                         #size-cells = <1>;
  96                         ranges = <0 0x48000000 0x1000000>;
  97
  98                         scm: scm@2000 {
  99                                 compatible = "ti,omap3-scm", "simple-bus";
 100                                 reg = <0x2000 0x2000>;
 101                                 #address-cells = <1>;
 102                                 #size-cells = <1>;
 103                                 ranges = <0 0x2000 0x2000>;
 104
 105                                 omap3_pmx_core: pinmux@30 {
 106                                         compatible = "ti,omap3-padconf",
 107                                                      "pinctrl-single";
 108                                         reg = <0x30 0x238>;
 109                                         #address-cells = <1>;
 110                                         #size-cells = <0>;
 111                                         #pinctrl-cells = <1>;
 112                                         #interrupt-cells = <1>;
 113                                         interrupt-controller;
 114                                         pinctrl-single,register-width = <16>;
 115                                         pinctrl-single,function-mask = <0xff1f>;
 116                                 };
 117
 118                                 scm_conf: scm_conf@270 {
 119                                         compatible = "syscon", "simple-bus";
 120                                         reg = <0x270 0x330>;
 121                                         #address-cells = <1>;
 122                                         #size-cells = <1>;
 123                                         ranges = <0 0x270 0x330>;
 124
 125                                         pbias_regulator: pbias_regulator@2b0 {
 126                                                 compatible = "ti,pbias-omap3", "ti,pbias-omap";
 127                                                 reg = <0x2b0 0x4>;
 128                                                 syscon = <&scm_conf>;
 129                                                 pbias_mmc_reg: pbias_mmc_omap2430 {
 130                                                         regulator-name = "pbias_mmc_omap2430";
 131                                                         regulator-min-microvolt = <1800000>;
 132                                                         regulator-max-microvolt = <3000000>;
 133                                                 };
 134                                         };
 135
 136                                         scm_clocks: clocks {
 137                                                 #address-cells = <1>;
 138                                                 #size-cells = <0>;
 139                                         };
 140                                 };
 141
 142                                 scm_clockdomains: clockdomains {
 143                                 };
 144
 145                                 omap3_pmx_wkup: pinmux@a00 {
 146                                         compatible = "ti,omap3-padconf",
 147                                                      "pinctrl-single";
 148                                         reg = <0xa00 0x5c>;
 149                                         #address-cells = <1>;
 150                                         #size-cells = <0>;
 151                                         #pinctrl-cells = <1>;
 152                                         #interrupt-cells = <1>;
 153                                         interrupt-controller;
 154                                         pinctrl-single,register-width = <16>;
 155                                         pinctrl-single,function-mask = <0xff1f>;
 156                                 };
 157                         };
 158                 };
 159
 160                 aes1_target: target-module@480a6000 {
 161                         compatible = "ti,sysc-omap2", "ti,sysc";
 162                         reg = <0x480a6044 0x4>,
 163                               <0x480a6048 0x4>,
 164                               <0x480a604c 0x4>;
 165                         reg-names = "rev", "sysc", "syss";
 166                         ti,sysc-mask = <(SYSC_OMAP2_AUTOIDLE)>;
 167                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 168                                         <SYSC_IDLE_NO>,
 169                                         <SYSC_IDLE_SMART>;
 170                         ti,syss-mask = <1>;
 171                         clocks = <&aes1_ick>;
 172                         clock-names = "ick";
 173                         #address-cells = <1>;
 174                         #size-cells = <1>;
 175                         ranges = <0 0x480a6000 0x2000>;
 176
 177                         aes1: aes1@0 {
 178                                 compatible = "ti,omap3-aes";
 179                                 reg = <0 0x50>;
 180                                 interrupts = <0>;
 181                                 dmas = <&sdma 9 &sdma 10>;
 182                                 dma-names = "tx", "rx";
 183                         };
 184                 };
 185
 186                 aes2_target: target-module@480c5000 {
 187                         compatible = "ti,sysc-omap2", "ti,sysc";
 188                         reg = <0x480c5044 0x4>,
 189                               <0x480c5048 0x4>,
 190                               <0x480c504c 0x4>;
 191                         reg-names = "rev", "sysc", "syss";
 192                         ti,sysc-mask = <(SYSC_OMAP2_AUTOIDLE)>;
 193                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 194                                         <SYSC_IDLE_NO>,
 195                                         <SYSC_IDLE_SMART>;
 196                         ti,syss-mask = <1>;
 197                         clocks = <&aes2_ick>;
 198                         clock-names = "ick";
 199                         #address-cells = <1>;
 200                         #size-cells = <1>;
 201                         ranges = <0 0x480c5000 0x2000>;
 202
 203                         aes2: aes2@0 {
 204                                 compatible = "ti,omap3-aes";
 205                                 reg = <0 0x50>;
 206                                 interrupts = <0>;
 207                                 dmas = <&sdma 65 &sdma 66>;
 208                                 dma-names = "tx", "rx";
 209                         };
 210                 };
 211
 212                 prm: prm@48306000 {
 213                         compatible = "ti,omap3-prm";
 214                         reg = <0x48306000 0x4000>;
 215                         interrupts = <11>;
 216
 217                         prm_clocks: clocks {
 218                                 #address-cells = <1>;
 219                                 #size-cells = <0>;
 220                         };
 221
 222                         prm_clockdomains: clockdomains {
 223                         };
 224                 };
 225
 226                 cm: cm@48004000 {
 227                         compatible = "ti,omap3-cm";
 228                         reg = <0x48004000 0x4000>;
 229
 230                         cm_clocks: clocks {
 231                                 #address-cells = <1>;
 232                                 #size-cells = <0>;
 233                         };
 234
 235                         cm_clockdomains: clockdomains {
 236                         };
 237                 };
 238
 239                 target-module@48320000 {
 240                         compatible = "ti,sysc-omap2", "ti,sysc";
 241                         reg = <0x48320000 0x4>,
 242                               <0x48320004 0x4>;
 243                         reg-names = "rev", "sysc";
 244                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 245                                         <SYSC_IDLE_NO>;
 246                         clocks = <&wkup_32k_fck>, <&omap_32ksync_ick>;
 247                         clock-names = "fck", "ick";
 248                         #address-cells = <1>;
 249                         #size-cells = <1>;
 250                         ranges = <0x0 0x48320000 0x1000>;
 251
 252                         counter32k: counter@0 {
 253                                 compatible = "ti,omap-counter32k";
 254                                 reg = <0x0 0x20>;
 255                         };
 256                 };
 257
 258                 intc: interrupt-controller@48200000 {
 259                         compatible = "ti,omap3-intc";
 260                         interrupt-controller;
 261                         #interrupt-cells = <1>;
 262                         reg = <0x48200000 0x1000>;
 263                 };
 264
 265                 target-module@48056000 {
 266                         compatible = "ti,sysc-omap2", "ti,sysc";
 267                         reg = <0x48056000 0x4>,
 268                               <0x4805602c 0x4>,
 269                               <0x48056028 0x4>;
 270                         reg-names = "rev", "sysc", "syss";
 271                         ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
 272                                          SYSC_OMAP2_EMUFREE |
 273                                          SYSC_OMAP2_SOFTRESET |
 274                                          SYSC_OMAP2_AUTOIDLE)>;
 275                         ti,sysc-midle = <SYSC_IDLE_FORCE>,
 276                                         <SYSC_IDLE_NO>,
 277                                         <SYSC_IDLE_SMART>;
 278                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 279                                         <SYSC_IDLE_NO>,
 280                                         <SYSC_IDLE_SMART>;
 281                         ti,syss-mask = <1>;
 282                         /* Domains (V, P, C): core, core_pwrdm, core_l3_clkdm */
 283                         clocks = <&core_l3_ick>;
 284                         clock-names = "ick";
 285                         #address-cells = <1>;
 286                         #size-cells = <1>;
 287                         ranges = <0 0x48056000 0x1000>;
 288
 289                         sdma: dma-controller@0 {
 290                                 compatible = "ti,omap3430-sdma", "ti,omap-sdma";
 291                                 reg = <0x0 0x1000>;
 292                                 interrupts = <12>,
 293                                              <13>,
 294                                              <14>,
 295                                              <15>;
 296                                 #dma-cells = <1>;
 297                                 dma-channels = <32>;
 298                                 dma-requests = <96>;
 299                         };
 300                 };
 301
 302                 gpio1: gpio@48310000 {
 303                         compatible = "ti,omap3-gpio";
 304                         reg = <0x48310000 0x200>;
 305                         interrupts = <29>;
 306                         ti,hwmods = "gpio1";
 307                         ti,gpio-always-on;
 308                         gpio-controller;
 309                         #gpio-cells = <2>;
 310                         interrupt-controller;
 311                         #interrupt-cells = <2>;
 312                 };
 313
 314                 gpio2: gpio@49050000 {
 315                         compatible = "ti,omap3-gpio";
 316                         reg = <0x49050000 0x200>;
 317                         interrupts = <30>;
 318                         ti,hwmods = "gpio2";
 319                         gpio-controller;
 320                         #gpio-cells = <2>;
 321                         interrupt-controller;
 322                         #interrupt-cells = <2>;
 323                 };
 324
 325                 gpio3: gpio@49052000 {
 326                         compatible = "ti,omap3-gpio";
 327                         reg = <0x49052000 0x200>;
 328                         interrupts = <31>;
 329                         ti,hwmods = "gpio3";
 330                         gpio-controller;
 331                         #gpio-cells = <2>;
 332                         interrupt-controller;
 333                         #interrupt-cells = <2>;
 334                 };
 335
 336                 gpio4: gpio@49054000 {
 337                         compatible = "ti,omap3-gpio";
 338                         reg = <0x49054000 0x200>;
 339                         interrupts = <32>;
 340                         ti,hwmods = "gpio4";
 341                         gpio-controller;
 342                         #gpio-cells = <2>;
 343                         interrupt-controller;
 344                         #interrupt-cells = <2>;
 345                 };
 346
 347                 gpio5: gpio@49056000 {
 348                         compatible = "ti,omap3-gpio";
 349                         reg = <0x49056000 0x200>;
 350                         interrupts = <33>;
 351                         ti,hwmods = "gpio5";
 352                         gpio-controller;
 353                         #gpio-cells = <2>;
 354                         interrupt-controller;
 355                         #interrupt-cells = <2>;
 356                 };
 357
 358                 gpio6: gpio@49058000 {
 359                         compatible = "ti,omap3-gpio";
 360                         reg = <0x49058000 0x200>;
 361                         interrupts = <34>;
 362                         ti,hwmods = "gpio6";
 363                         gpio-controller;
 364                         #gpio-cells = <2>;
 365                         interrupt-controller;
 366                         #interrupt-cells = <2>;
 367                 };
 368
 369                 uart1: serial@4806a000 {
 370                         compatible = "ti,omap3-uart";
 371                         reg = <0x4806a000 0x2000>;
 372                         interrupts-extended = <&intc 72>;
 373                         dmas = <&sdma 49 &sdma 50>;
 374                         dma-names = "tx", "rx";
 375                         ti,hwmods = "uart1";
 376                         clock-frequency = <48000000>;
 377                 };
 378
 379                 uart2: serial@4806c000 {
 380                         compatible = "ti,omap3-uart";
 381                         reg = <0x4806c000 0x400>;
 382                         interrupts-extended = <&intc 73>;
 383                         dmas = <&sdma 51 &sdma 52>;
 384                         dma-names = "tx", "rx";
 385                         ti,hwmods = "uart2";
 386                         clock-frequency = <48000000>;
 387                 };
 388
 389                 uart3: serial@49020000 {
 390                         compatible = "ti,omap3-uart";
 391                         reg = <0x49020000 0x400>;
 392                         interrupts-extended = <&intc 74>;
 393                         dmas = <&sdma 53 &sdma 54>;
 394                         dma-names = "tx", "rx";
 395                         ti,hwmods = "uart3";
 396                         clock-frequency = <48000000>;
 397                 };
 398
 399                 i2c1: i2c@48070000 {
 400                         compatible = "ti,omap3-i2c";
 401                         reg = <0x48070000 0x80>;
 402                         interrupts = <56>;
 403                         #address-cells = <1>;
 404                         #size-cells = <0>;
 405                         ti,hwmods = "i2c1";
 406                 };
 407
 408                 i2c2: i2c@48072000 {
 409                         compatible = "ti,omap3-i2c";
 410                         reg = <0x48072000 0x80>;
 411                         interrupts = <57>;
 412                         #address-cells = <1>;
 413                         #size-cells = <0>;
 414                         ti,hwmods = "i2c2";
 415                 };
 416
 417                 i2c3: i2c@48060000 {
 418                         compatible = "ti,omap3-i2c";
 419                         reg = <0x48060000 0x80>;
 420                         interrupts = <61>;
 421                         #address-cells = <1>;
 422                         #size-cells = <0>;
 423                         ti,hwmods = "i2c3";
 424                 };
 425
 426                 mailbox: mailbox@48094000 {
 427                         compatible = "ti,omap3-mailbox";
 428                         ti,hwmods = "mailbox";
 429                         reg = <0x48094000 0x200>;
 430                         interrupts = <26>;
 431                         #mbox-cells = <1>;
 432                         ti,mbox-num-users = <2>;
 433                         ti,mbox-num-fifos = <2>;
 434                         mbox_dsp: mbox-dsp {
 435                                 ti,mbox-tx = <0 0 0>;
 436                                 ti,mbox-rx = <1 0 0>;
 437                         };
 438                 };
 439
 440                 mcspi1: spi@48098000 {
 441                         compatible = "ti,omap2-mcspi";
 442                         reg = <0x48098000 0x100>;
 443                         interrupts = <65>;
 444                         #address-cells = <1>;
 445                         #size-cells = <0>;
 446                         ti,hwmods = "mcspi1";
 447                         ti,spi-num-cs = <4>;
 448                         dmas = <&sdma 35>,
 449                                <&sdma 36>,
 450                                <&sdma 37>,
 451                                <&sdma 38>,
 452                                <&sdma 39>,
 453                                <&sdma 40>,
 454                                <&sdma 41>,
 455                                <&sdma 42>;
 456                         dma-names = "tx0", "rx0", "tx1", "rx1",
 457                                     "tx2", "rx2", "tx3", "rx3";
 458                 };
 459
 460                 mcspi2: spi@4809a000 {
 461                         compatible = "ti,omap2-mcspi";
 462                         reg = <0x4809a000 0x100>;
 463                         interrupts = <66>;
 464                         #address-cells = <1>;
 465                         #size-cells = <0>;
 466                         ti,hwmods = "mcspi2";
 467                         ti,spi-num-cs = <2>;
 468                         dmas = <&sdma 43>,
 469                                <&sdma 44>,
 470                                <&sdma 45>,
 471                                <&sdma 46>;
 472                         dma-names = "tx0", "rx0", "tx1", "rx1";
 473                 };
 474
 475                 mcspi3: spi@480b8000 {
 476                         compatible = "ti,omap2-mcspi";
 477                         reg = <0x480b8000 0x100>;
 478                         interrupts = <91>;
 479                         #address-cells = <1>;
 480                         #size-cells = <0>;
 481                         ti,hwmods = "mcspi3";
 482                         ti,spi-num-cs = <2>;
 483                         dmas = <&sdma 15>,
 484                                <&sdma 16>,
 485                                <&sdma 23>,
 486                                <&sdma 24>;
 487                         dma-names = "tx0", "rx0", "tx1", "rx1";
 488                 };
 489
 490                 mcspi4: spi@480ba000 {
 491                         compatible = "ti,omap2-mcspi";
 492                         reg = <0x480ba000 0x100>;
 493                         interrupts = <48>;
 494                         #address-cells = <1>;
 495                         #size-cells = <0>;
 496                         ti,hwmods = "mcspi4";
 497                         ti,spi-num-cs = <1>;
 498                         dmas = <&sdma 70>, <&sdma 71>;
 499                         dma-names = "tx0", "rx0";
 500                 };
 501
 502                 hdqw1w: 1w@480b2000 {
 503                         compatible = "ti,omap3-1w";
 504                         reg = <0x480b2000 0x1000>;
 505                         interrupts = <58>;
 506                         ti,hwmods = "hdq1w";
 507                 };
 508
 509                 mmc1: mmc@4809c000 {
 510                         compatible = "ti,omap3-hsmmc";
 511                         reg = <0x4809c000 0x200>;
 512                         interrupts = <83>;
 513                         ti,hwmods = "mmc1";
 514                         ti,dual-volt;
 515                         dmas = <&sdma 61>, <&sdma 62>;
 516                         dma-names = "tx", "rx";
 517                         pbias-supply = <&pbias_mmc_reg>;
 518                 };
 519
 520                 mmc2: mmc@480b4000 {
 521                         compatible = "ti,omap3-hsmmc";
 522                         reg = <0x480b4000 0x200>;
 523                         interrupts = <86>;
 524                         ti,hwmods = "mmc2";
 525                         dmas = <&sdma 47>, <&sdma 48>;
 526                         dma-names = "tx", "rx";
 527                 };
 528
 529                 mmc3: mmc@480ad000 {
 530                         compatible = "ti,omap3-hsmmc";
 531                         reg = <0x480ad000 0x200>;
 532                         interrupts = <94>;
 533                         ti,hwmods = "mmc3";
 534                         dmas = <&sdma 77>, <&sdma 78>;
 535                         dma-names = "tx", "rx";
 536                 };
 537
 538                 mmu_isp: mmu@480bd400 {
 539                         #iommu-cells = <0>;
 540                         compatible = "ti,omap2-iommu";
 541                         reg = <0x480bd400 0x80>;
 542                         interrupts = <24>;
 543                         ti,hwmods = "mmu_isp";
 544                         ti,#tlb-entries = <8>;
 545                 };
 546
 547                 mmu_iva: mmu@5d000000 {
 548                         #iommu-cells = <0>;
 549                         compatible = "ti,omap2-iommu";
 550                         reg = <0x5d000000 0x80>;
 551                         interrupts = <28>;
 552                         ti,hwmods = "mmu_iva";
 553                         status = "disabled";
 554                 };
 555
 556                 wdt2: wdt@48314000 {
 557                         compatible = "ti,omap3-wdt";
 558                         reg = <0x48314000 0x80>;
 559                         ti,hwmods = "wd_timer2";
 560                 };
 561
 562                 mcbsp1: mcbsp@48074000 {
 563                         compatible = "ti,omap3-mcbsp";
 564                         reg = <0x48074000 0xff>;
 565                         reg-names = "mpu";
 566                         interrupts = <16>, /* OCP compliant interrupt */
 567                                      <59>, /* TX interrupt */
 568                                      <60>; /* RX interrupt */
 569                         interrupt-names = "common", "tx", "rx";
 570                         ti,buffer-size = <128>;
 571                         ti,hwmods = "mcbsp1";
 572                         dmas = <&sdma 31>,
 573                                <&sdma 32>;
 574                         dma-names = "tx", "rx";
 575                         clocks = <&mcbsp1_fck>;
 576                         clock-names = "fck";
 577                         status = "disabled";
 578                 };
 579
 580                 /* Likely needs to be tagged disabled on HS devices */
 581                 rng_target: target-module@480a0000 {
 582                         compatible = "ti,sysc-omap2", "ti,sysc";
 583                         reg = <0x480a003c 0x4>,
 584                               <0x480a0040 0x4>,
 585                               <0x480a0044 0x4>;
 586                         reg-names = "rev", "sysc", "syss";
 587                         ti,sysc-mask = <(SYSC_OMAP2_AUTOIDLE)>;
 588                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 589                                         <SYSC_IDLE_NO>;
 590                         ti,syss-mask = <1>;
 591                         clocks = <&rng_ick>;
 592                         clock-names = "ick";
 593                         #address-cells = <1>;
 594                         #size-cells = <1>;
 595                         ranges = <0 0x480a0000 0x2000>;
 596
 597                         rng: rng@0 {
 598                                 compatible = "ti,omap2-rng";
 599                                 reg = <0x0 0x2000>;
 600                                 interrupts = <52>;
 601                         };
 602                 };
 603
 604                 mcbsp2: mcbsp@49022000 {
 605                         compatible = "ti,omap3-mcbsp";
 606                         reg = <0x49022000 0xff>,
 607                               <0x49028000 0xff>;
 608                         reg-names = "mpu", "sidetone";
 609                         interrupts = <17>, /* OCP compliant interrupt */
 610                                      <62>, /* TX interrupt */
 611                                      <63>, /* RX interrupt */
 612                                      <4>;  /* Sidetone */
 613                         interrupt-names = "common", "tx", "rx", "sidetone";
 614                         ti,buffer-size = <1280>;
 615                         ti,hwmods = "mcbsp2", "mcbsp2_sidetone";
 616                         dmas = <&sdma 33>,
 617                                <&sdma 34>;
 618                         dma-names = "tx", "rx";
 619                         clocks = <&mcbsp2_fck>, <&mcbsp2_ick>;
 620                         clock-names = "fck", "ick";
 621                         status = "disabled";
 622                 };
 623
 624                 mcbsp3: mcbsp@49024000 {
 625                         compatible = "ti,omap3-mcbsp";
 626                         reg = <0x49024000 0xff>,
 627                               <0x4902a000 0xff>;
 628                         reg-names = "mpu", "sidetone";
 629                         interrupts = <22>, /* OCP compliant interrupt */
 630                                      <89>, /* TX interrupt */
 631                                      <90>, /* RX interrupt */
 632                                      <5>;  /* Sidetone */
 633                         interrupt-names = "common", "tx", "rx", "sidetone";
 634                         ti,buffer-size = <128>;
 635                         ti,hwmods = "mcbsp3", "mcbsp3_sidetone";
 636                         dmas = <&sdma 17>,
 637                                <&sdma 18>;
 638                         dma-names = "tx", "rx";
 639                         clocks = <&mcbsp3_fck>, <&mcbsp3_ick>;
 640                         clock-names = "fck", "ick";
 641                         status = "disabled";
 642                 };
 643
 644                 mcbsp4: mcbsp@49026000 {
 645                         compatible = "ti,omap3-mcbsp";
 646                         reg = <0x49026000 0xff>;
 647                         reg-names = "mpu";
 648                         interrupts = <23>, /* OCP compliant interrupt */
 649                                      <54>, /* TX interrupt */
 650                                      <55>; /* RX interrupt */
 651                         interrupt-names = "common", "tx", "rx";
 652                         ti,buffer-size = <128>;
 653                         ti,hwmods = "mcbsp4";
 654                         dmas = <&sdma 19>,
 655                                <&sdma 20>;
 656                         dma-names = "tx", "rx";
 657                         clocks = <&mcbsp4_fck>;
 658                         clock-names = "fck";
 659                         #sound-dai-cells = <0>;
 660                         status = "disabled";
 661                 };
 662
 663                 mcbsp5: mcbsp@48096000 {
 664                         compatible = "ti,omap3-mcbsp";
 665                         reg = <0x48096000 0xff>;
 666                         reg-names = "mpu";
 667                         interrupts = <27>, /* OCP compliant interrupt */
 668                                      <81>, /* TX interrupt */
 669                                      <82>; /* RX interrupt */
 670                         interrupt-names = "common", "tx", "rx";
 671                         ti,buffer-size = <128>;
 672                         ti,hwmods = "mcbsp5";
 673                         dmas = <&sdma 21>,
 674                                <&sdma 22>;
 675                         dma-names = "tx", "rx";
 676                         clocks = <&mcbsp5_fck>;
 677                         clock-names = "fck";
 678                         status = "disabled";
 679                 };
 680
 681                 sham: sham@480c3000 {
 682                         compatible = "ti,omap3-sham";
 683                         ti,hwmods = "sham";
 684                         reg = <0x480c3000 0x64>;
 685                         interrupts = <49>;
 686                         dmas = <&sdma 69>;
 687                         dma-names = "rx";
 688                 };
 689
 690                 timer1_target: target-module@48318000 {
 691                         compatible = "ti,sysc-omap2-timer", "ti,sysc";
 692                         reg = <0x48318000 0x4>,
 693                               <0x48318010 0x4>,
 694                               <0x48318014 0x4>;
 695                         reg-names = "rev", "sysc", "syss";
 696                         ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
 697                                          SYSC_OMAP2_EMUFREE |
 698                                          SYSC_OMAP2_ENAWAKEUP |
 699                                          SYSC_OMAP2_SOFTRESET |
 700                                          SYSC_OMAP2_AUTOIDLE)>;
 701                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 702                                         <SYSC_IDLE_NO>,
 703                                         <SYSC_IDLE_SMART>;
 704                         ti,syss-mask = <1>;
 705                         clocks = <&gpt1_fck>, <&gpt1_ick>;
 706                         clock-names = "fck", "ick";
 707                         #address-cells = <1>;
 708                         #size-cells = <1>;
 709                         ranges = <0x0 0x48318000 0x1000>;
 710
 711                         timer1: timer@0 {
 712                                 compatible = "ti,omap3430-timer";
 713                                 reg = <0x0 0x80>;
 714                                 clocks = <&gpt1_fck>;
 715                                 clock-names = "fck";
 716                                 interrupts = <37>;
 717                                 ti,timer-alwon;
 718                         };
 719                 };
 720
 721                 timer2_target: target-module@49032000 {
 722                         compatible = "ti,sysc-omap2-timer", "ti,sysc";
 723                         reg = <0x49032000 0x4>,
 724                               <0x49032010 0x4>,
 725                               <0x49032014 0x4>;
 726                         reg-names = "rev", "sysc", "syss";
 727                         ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
 728                                          SYSC_OMAP2_EMUFREE |
 729                                          SYSC_OMAP2_ENAWAKEUP |
 730                                          SYSC_OMAP2_SOFTRESET |
 731                                          SYSC_OMAP2_AUTOIDLE)>;
 732                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 733                                         <SYSC_IDLE_NO>,
 734                                         <SYSC_IDLE_SMART>;
 735                         ti,syss-mask = <1>;
 736                         clocks = <&gpt2_fck>, <&gpt2_ick>;
 737                         clock-names = "fck", "ick";
 738                         #address-cells = <1>;
 739                         #size-cells = <1>;
 740                         ranges = <0x0 0x49032000 0x1000>;
 741
 742                         timer2: timer@0 {
 743                                 compatible = "ti,omap3430-timer";
 744                                 reg = <0 0x400>;
 745                                 interrupts = <38>;
 746                         };
 747                 };
 748
 749                 timer3: timer@49034000 {
 750                         compatible = "ti,omap3430-timer";
 751                         reg = <0x49034000 0x400>;
 752                         interrupts = <39>;
 753                         ti,hwmods = "timer3";
 754                 };
 755
 756                 timer4: timer@49036000 {
 757                         compatible = "ti,omap3430-timer";
 758                         reg = <0x49036000 0x400>;
 759                         interrupts = <40>;
 760                         ti,hwmods = "timer4";
 761                 };
 762
 763                 timer5: timer@49038000 {
 764                         compatible = "ti,omap3430-timer";
 765                         reg = <0x49038000 0x400>;
 766                         interrupts = <41>;
 767                         ti,hwmods = "timer5";
 768                         ti,timer-dsp;
 769                 };
 770
 771                 timer6: timer@4903a000 {
 772                         compatible = "ti,omap3430-timer";
 773                         reg = <0x4903a000 0x400>;
 774                         interrupts = <42>;
 775                         ti,hwmods = "timer6";
 776                         ti,timer-dsp;
 777                 };
 778
 779                 timer7: timer@4903c000 {
 780                         compatible = "ti,omap3430-timer";
 781                         reg = <0x4903c000 0x400>;
 782                         interrupts = <43>;
 783                         ti,hwmods = "timer7";
 784                         ti,timer-dsp;
 785                 };
 786
 787                 timer8: timer@4903e000 {
 788                         compatible = "ti,omap3430-timer";
 789                         reg = <0x4903e000 0x400>;
 790                         interrupts = <44>;
 791                         ti,hwmods = "timer8";
 792                         ti,timer-pwm;
 793                         ti,timer-dsp;
 794                 };
 795
 796                 timer9: timer@49040000 {
 797                         compatible = "ti,omap3430-timer";
 798                         reg = <0x49040000 0x400>;
 799                         interrupts = <45>;
 800                         ti,hwmods = "timer9";
 801                         ti,timer-pwm;
 802                 };
 803
 804                 timer10: timer@48086000 {
 805                         compatible = "ti,omap3430-timer";
 806                         reg = <0x48086000 0x400>;
 807                         interrupts = <46>;
 808                         ti,hwmods = "timer10";
 809                         ti,timer-pwm;
 810                 };
 811
 812                 timer11: timer@48088000 {
 813                         compatible = "ti,omap3430-timer";
 814                         reg = <0x48088000 0x400>;
 815                         interrupts = <47>;
 816                         ti,hwmods = "timer11";
 817                         ti,timer-pwm;
 818                 };
 819
 820                 timer12_target: target-module@48304000 {
 821                         compatible = "ti,sysc-omap2-timer", "ti,sysc";
 822                         reg = <0x48304000 0x4>,
 823                               <0x48304010 0x4>,
 824                               <0x48304014 0x4>;
 825                         reg-names = "rev", "sysc", "syss";
 826                         ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
 827                                          SYSC_OMAP2_EMUFREE |
 828                                          SYSC_OMAP2_ENAWAKEUP |
 829                                          SYSC_OMAP2_SOFTRESET |
 830                                          SYSC_OMAP2_AUTOIDLE)>;
 831                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 832                                         <SYSC_IDLE_NO>,
 833                                         <SYSC_IDLE_SMART>;
 834                         ti,syss-mask = <1>;
 835                         clocks = <&gpt12_fck>, <&gpt12_ick>;
 836                         clock-names = "fck", "ick";
 837                         #address-cells = <1>;
 838                         #size-cells = <1>;
 839                         ranges = <0x0 0x48304000 0x1000>;
 840
 841                         timer12: timer@0 {
 842                                 compatible = "ti,omap3430-timer";
 843                                 reg = <0 0x400>;
 844                                 interrupts = <95>;
 845                                 ti,timer-alwon;
 846                                 ti,timer-secure;
 847                         };
 848                 };
 849
 850                 usbhstll: usbhstll@48062000 {
 851                         compatible = "ti,usbhs-tll";
 852                         reg = <0x48062000 0x1000>;
 853                         interrupts = <78>;
 854                         ti,hwmods = "usb_tll_hs";
 855                 };
 856
 857                 usbhshost: usbhshost@48064000 {
 858                         compatible = "ti,usbhs-host";
 859                         reg = <0x48064000 0x400>;
 860                         ti,hwmods = "usb_host_hs";
 861                         #address-cells = <1>;
 862                         #size-cells = <1>;
 863                         ranges;
 864
 865                         usbhsohci: ohci@48064400 {
 866                                 compatible = "ti,ohci-omap3";
 867                                 reg = <0x48064400 0x400>;
 868                                 interrupts = <76>;
 869                                 remote-wakeup-connected;
 870                         };
 871
 872                         usbhsehci: ehci@48064800 {
 873                                 compatible = "ti,ehci-omap";
 874                                 reg = <0x48064800 0x400>;
 875                                 interrupts = <77>;
 876                         };
 877                 };
 878
 879                 gpmc: gpmc@6e000000 {
 880                         compatible = "ti,omap3430-gpmc";
 881                         ti,hwmods = "gpmc";
 882                         reg = <0x6e000000 0x02d0>;
 883                         interrupts = <20>;
 884                         dmas = <&sdma 4>;
 885                         dma-names = "rxtx";
 886                         gpmc,num-cs = <8>;
 887                         gpmc,num-waitpins = <4>;
 888                         #address-cells = <2>;
 889                         #size-cells = <1>;
 890                         interrupt-controller;
 891                         #interrupt-cells = <2>;
 892                         gpio-controller;
 893                         #gpio-cells = <2>;
 894                 };
 895
 896                 usb_otg_hs: usb_otg_hs@480ab000 {
 897                         compatible = "ti,omap3-musb";
 898                         reg = <0x480ab000 0x1000>;
 899                         interrupts = <92>, <93>;
 900                         interrupt-names = "mc", "dma";
 901                         ti,hwmods = "usb_otg_hs";
 902                         multipoint = <1>;
 903                         num-eps = <16>;
 904                         ram-bits = <12>;
 905                 };
 906
 907                 dss: dss@48050000 {
 908                         compatible = "ti,omap3-dss";
 909                         reg = <0x48050000 0x200>;
 910                         status = "disabled";
 911                         ti,hwmods = "dss_core";
 912                         clocks = <&dss1_alwon_fck>;
 913                         clock-names = "fck";
 914                         #address-cells = <1>;
 915                         #size-cells = <1>;
 916                         ranges;
 917
 918                         dispc@48050400 {
 919                                 compatible = "ti,omap3-dispc";
 920                                 reg = <0x48050400 0x400>;
 921                                 interrupts = <25>;
 922                                 ti,hwmods = "dss_dispc";
 923                                 clocks = <&dss1_alwon_fck>;
 924                                 clock-names = "fck";
 925                         };
 926
 927                         dsi: encoder@4804fc00 {
 928                                 compatible = "ti,omap3-dsi";
 929                                 reg = <0x4804fc00 0x200>,
 930                                       <0x4804fe00 0x40>,
 931                                       <0x4804ff00 0x20>;
 932                                 reg-names = "proto", "phy", "pll";
 933                                 interrupts = <25>;
 934                                 status = "disabled";
 935                                 ti,hwmods = "dss_dsi1";
 936                                 clocks = <&dss1_alwon_fck>, <&dss2_alwon_fck>;
 937                                 clock-names = "fck", "sys_clk";
 938
 939                                 #address-cells = <1>;
 940                                 #size-cells = <0>;
 941                         };
 942
 943                         rfbi: encoder@48050800 {
 944                                 compatible = "ti,omap3-rfbi";
 945                                 reg = <0x48050800 0x100>;
 946                                 status = "disabled";
 947                                 ti,hwmods = "dss_rfbi";
 948                                 clocks = <&dss1_alwon_fck>, <&dss_ick>;
 949                                 clock-names = "fck", "ick";
 950                         };
 951
 952                         venc: encoder@48050c00 {
 953                                 compatible = "ti,omap3-venc";
 954                                 reg = <0x48050c00 0x100>;
 955                                 status = "disabled";
 956                                 ti,hwmods = "dss_venc";
 957                                 clocks = <&dss_tv_fck>;
 958                                 clock-names = "fck";
 959                         };
 960                 };
 961
 962                 ssi: ssi-controller@48058000 {
 963                         compatible = "ti,omap3-ssi";
 964                         ti,hwmods = "ssi";
 965
 966                         status = "disabled";
 967
 968                         reg = <0x48058000 0x1000>,
 969                               <0x48059000 0x1000>;
 970                         reg-names = "sys",
 971                                     "gdd";
 972
 973                         interrupts = <71>;
 974                         interrupt-names = "gdd_mpu";
 975
 976                         #address-cells = <1>;
 977                         #size-cells = <1>;
 978                         ranges;
 979
 980                         ssi_port1: ssi-port@4805a000 {
 981                                 compatible = "ti,omap3-ssi-port";
 982
 983                                 reg = <0x4805a000 0x800>,
 984                                       <0x4805a800 0x800>;
 985                                 reg-names = "tx",
 986                                             "rx";
 987
 988                                 interrupts = <67>,
 989                                              <68>;
 990                         };
 991
 992                         ssi_port2: ssi-port@4805b000 {
 993                                 compatible = "ti,omap3-ssi-port";
 994
 995                                 reg = <0x4805b000 0x800>,
 996                                       <0x4805b800 0x800>;
 997                                 reg-names = "tx",
 998                                             "rx";
 999
1000                                 interrupts = <69>,
1001                                              <70>;
1002                         };
1003                 };
1004         };
1005 };
1006
1007 #include "omap3xxx-clocks.dtsi"
1008
1009 /* Preferred always-on timer for clockevent. Some boards must use dmtimer12 */
1010 &timer1_target {
1011         ti,no-reset-on-init;
1012         ti,no-idle;
1013         timer@0 {
1014                 assigned-clocks = <&gpt1_fck>;
1015                 assigned-clock-parents = <&omap_32k_fck>;
1016         };
1017 };