2 * Device Tree Source for OMAP3 SoC
4 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/pinctrl/omap.h>
16 compatible = "ti,omap3430", "ti,omap3";
17 interrupt-parent = <&intc>;
39 compatible = "arm,cortex-a8";
46 clock-latency = <300000>; /* From omap-cpufreq driver */
51 compatible = "arm,cortex-a8-pmu";
52 reg = <0x54000000 0x800000>;
54 ti,hwmods = "debugss";
58 * The soc node represents the soc top level view. It is used for IPs
59 * that are not memory mapped in the MPU view or for the MPU itself.
62 compatible = "ti,omap-infra";
64 compatible = "ti,omap3-mpu";
69 compatible = "ti,iva2.2";
73 compatible = "ti,omap3-c64";
79 * XXX: Use a flat representation of the OMAP3 interconnect.
80 * The real OMAP interconnect network is quite complex.
81 * Since it will not bring real advantage to represent that in DT for
82 * the moment, just use a fake OCP bus entry to represent the whole bus
86 compatible = "ti,omap3-l3-smx", "simple-bus";
87 reg = <0x68000000 0x10000>;
92 ti,hwmods = "l3_main";
94 l4_core: l4@48000000 {
95 compatible = "ti,omap3-l4-core", "simple-bus";
98 ranges = <0 0x48000000 0x1000000>;
101 compatible = "ti,omap3-scm", "simple-bus";
102 reg = <0x2000 0x2000>;
103 #address-cells = <1>;
105 ranges = <0 0x2000 0x2000>;
107 omap3_pmx_core: pinmux@30 {
108 compatible = "ti,omap3-padconf",
111 #address-cells = <1>;
113 #pinctrl-cells = <1>;
114 #interrupt-cells = <1>;
115 interrupt-controller;
116 pinctrl-single,register-width = <16>;
117 pinctrl-single,function-mask = <0xff1f>;
120 scm_conf: scm_conf@270 {
121 compatible = "syscon", "simple-bus";
123 #address-cells = <1>;
125 ranges = <0 0x270 0x330>;
127 pbias_regulator: pbias_regulator@2b0 {
128 compatible = "ti,pbias-omap3", "ti,pbias-omap";
130 syscon = <&scm_conf>;
131 pbias_mmc_reg: pbias_mmc_omap2430 {
132 regulator-name = "pbias_mmc_omap2430";
133 regulator-min-microvolt = <1800000>;
134 regulator-max-microvolt = <3000000>;
139 #address-cells = <1>;
144 scm_clockdomains: clockdomains {
147 omap3_pmx_wkup: pinmux@a00 {
148 compatible = "ti,omap3-padconf",
151 #address-cells = <1>;
153 #pinctrl-cells = <1>;
154 #interrupt-cells = <1>;
155 interrupt-controller;
156 pinctrl-single,register-width = <16>;
157 pinctrl-single,function-mask = <0xff1f>;
163 compatible = "ti,omap3-aes";
165 reg = <0x480c5000 0x50>;
167 dmas = <&sdma 65 &sdma 66>;
168 dma-names = "tx", "rx";
172 compatible = "ti,omap3-prm";
173 reg = <0x48306000 0x4000>;
177 #address-cells = <1>;
181 prm_clockdomains: clockdomains {
186 compatible = "ti,omap3-cm";
187 reg = <0x48004000 0x4000>;
190 #address-cells = <1>;
194 cm_clockdomains: clockdomains {
198 counter32k: counter@48320000 {
199 compatible = "ti,omap-counter32k";
200 reg = <0x48320000 0x20>;
201 ti,hwmods = "counter_32k";
204 intc: interrupt-controller@48200000 {
205 compatible = "ti,omap3-intc";
206 interrupt-controller;
207 #interrupt-cells = <1>;
208 reg = <0x48200000 0x1000>;
211 sdma: dma-controller@48056000 {
212 compatible = "ti,omap3630-sdma", "ti,omap3430-sdma";
213 reg = <0x48056000 0x1000>;
223 gpio1: gpio@48310000 {
224 compatible = "ti,omap3-gpio";
225 reg = <0x48310000 0x200>;
231 interrupt-controller;
232 #interrupt-cells = <2>;
235 gpio2: gpio@49050000 {
236 compatible = "ti,omap3-gpio";
237 reg = <0x49050000 0x200>;
242 interrupt-controller;
243 #interrupt-cells = <2>;
246 gpio3: gpio@49052000 {
247 compatible = "ti,omap3-gpio";
248 reg = <0x49052000 0x200>;
253 interrupt-controller;
254 #interrupt-cells = <2>;
257 gpio4: gpio@49054000 {
258 compatible = "ti,omap3-gpio";
259 reg = <0x49054000 0x200>;
264 interrupt-controller;
265 #interrupt-cells = <2>;
268 gpio5: gpio@49056000 {
269 compatible = "ti,omap3-gpio";
270 reg = <0x49056000 0x200>;
275 interrupt-controller;
276 #interrupt-cells = <2>;
279 gpio6: gpio@49058000 {
280 compatible = "ti,omap3-gpio";
281 reg = <0x49058000 0x200>;
286 interrupt-controller;
287 #interrupt-cells = <2>;
290 uart1: serial@4806a000 {
291 compatible = "ti,omap3-uart";
292 reg = <0x4806a000 0x2000>;
293 interrupts-extended = <&intc 72>;
294 dmas = <&sdma 49 &sdma 50>;
295 dma-names = "tx", "rx";
297 clock-frequency = <48000000>;
300 uart2: serial@4806c000 {
301 compatible = "ti,omap3-uart";
302 reg = <0x4806c000 0x400>;
303 interrupts-extended = <&intc 73>;
304 dmas = <&sdma 51 &sdma 52>;
305 dma-names = "tx", "rx";
307 clock-frequency = <48000000>;
310 uart3: serial@49020000 {
311 compatible = "ti,omap3-uart";
312 reg = <0x49020000 0x400>;
313 interrupts-extended = <&intc 74>;
314 dmas = <&sdma 53 &sdma 54>;
315 dma-names = "tx", "rx";
317 clock-frequency = <48000000>;
321 compatible = "ti,omap3-i2c";
322 reg = <0x48070000 0x80>;
324 dmas = <&sdma 27 &sdma 28>;
325 dma-names = "tx", "rx";
326 #address-cells = <1>;
332 compatible = "ti,omap3-i2c";
333 reg = <0x48072000 0x80>;
335 dmas = <&sdma 29 &sdma 30>;
336 dma-names = "tx", "rx";
337 #address-cells = <1>;
343 compatible = "ti,omap3-i2c";
344 reg = <0x48060000 0x80>;
346 dmas = <&sdma 25 &sdma 26>;
347 dma-names = "tx", "rx";
348 #address-cells = <1>;
353 mailbox: mailbox@48094000 {
354 compatible = "ti,omap3-mailbox";
355 ti,hwmods = "mailbox";
356 reg = <0x48094000 0x200>;
359 ti,mbox-num-users = <2>;
360 ti,mbox-num-fifos = <2>;
362 ti,mbox-tx = <0 0 0>;
363 ti,mbox-rx = <1 0 0>;
367 mcspi1: spi@48098000 {
368 compatible = "ti,omap2-mcspi";
369 reg = <0x48098000 0x100>;
371 #address-cells = <1>;
373 ti,hwmods = "mcspi1";
383 dma-names = "tx0", "rx0", "tx1", "rx1",
384 "tx2", "rx2", "tx3", "rx3";
387 mcspi2: spi@4809a000 {
388 compatible = "ti,omap2-mcspi";
389 reg = <0x4809a000 0x100>;
391 #address-cells = <1>;
393 ti,hwmods = "mcspi2";
399 dma-names = "tx0", "rx0", "tx1", "rx1";
402 mcspi3: spi@480b8000 {
403 compatible = "ti,omap2-mcspi";
404 reg = <0x480b8000 0x100>;
406 #address-cells = <1>;
408 ti,hwmods = "mcspi3";
414 dma-names = "tx0", "rx0", "tx1", "rx1";
417 mcspi4: spi@480ba000 {
418 compatible = "ti,omap2-mcspi";
419 reg = <0x480ba000 0x100>;
421 #address-cells = <1>;
423 ti,hwmods = "mcspi4";
425 dmas = <&sdma 70>, <&sdma 71>;
426 dma-names = "tx0", "rx0";
429 hdqw1w: 1w@480b2000 {
430 compatible = "ti,omap3-1w";
431 reg = <0x480b2000 0x1000>;
437 compatible = "ti,omap3-hsmmc";
438 reg = <0x4809c000 0x200>;
442 dmas = <&sdma 61>, <&sdma 62>;
443 dma-names = "tx", "rx";
444 pbias-supply = <&pbias_mmc_reg>;
448 compatible = "ti,omap3-hsmmc";
449 reg = <0x480b4000 0x200>;
452 dmas = <&sdma 47>, <&sdma 48>;
453 dma-names = "tx", "rx";
457 compatible = "ti,omap3-hsmmc";
458 reg = <0x480ad000 0x200>;
461 dmas = <&sdma 77>, <&sdma 78>;
462 dma-names = "tx", "rx";
465 mmu_isp: mmu@480bd400 {
467 compatible = "ti,omap2-iommu";
468 reg = <0x480bd400 0x80>;
470 ti,hwmods = "mmu_isp";
471 ti,#tlb-entries = <8>;
474 mmu_iva: mmu@5d000000 {
476 compatible = "ti,omap2-iommu";
477 reg = <0x5d000000 0x80>;
479 ti,hwmods = "mmu_iva";
484 compatible = "ti,omap3-wdt";
485 reg = <0x48314000 0x80>;
486 ti,hwmods = "wd_timer2";
489 mcbsp1: mcbsp@48074000 {
490 compatible = "ti,omap3-mcbsp";
491 reg = <0x48074000 0xff>;
493 interrupts = <16>, /* OCP compliant interrupt */
494 <59>, /* TX interrupt */
495 <60>; /* RX interrupt */
496 interrupt-names = "common", "tx", "rx";
497 ti,buffer-size = <128>;
498 ti,hwmods = "mcbsp1";
501 dma-names = "tx", "rx";
502 clocks = <&mcbsp1_fck>;
507 mcbsp2: mcbsp@49022000 {
508 compatible = "ti,omap3-mcbsp";
509 reg = <0x49022000 0xff>,
511 reg-names = "mpu", "sidetone";
512 interrupts = <17>, /* OCP compliant interrupt */
513 <62>, /* TX interrupt */
514 <63>, /* RX interrupt */
516 interrupt-names = "common", "tx", "rx", "sidetone";
517 ti,buffer-size = <1280>;
518 ti,hwmods = "mcbsp2", "mcbsp2_sidetone";
521 dma-names = "tx", "rx";
522 clocks = <&mcbsp2_fck>, <&mcbsp2_ick>;
523 clock-names = "fck", "ick";
527 mcbsp3: mcbsp@49024000 {
528 compatible = "ti,omap3-mcbsp";
529 reg = <0x49024000 0xff>,
531 reg-names = "mpu", "sidetone";
532 interrupts = <22>, /* OCP compliant interrupt */
533 <89>, /* TX interrupt */
534 <90>, /* RX interrupt */
536 interrupt-names = "common", "tx", "rx", "sidetone";
537 ti,buffer-size = <128>;
538 ti,hwmods = "mcbsp3", "mcbsp3_sidetone";
541 dma-names = "tx", "rx";
542 clocks = <&mcbsp3_fck>, <&mcbsp3_ick>;
543 clock-names = "fck", "ick";
547 mcbsp4: mcbsp@49026000 {
548 compatible = "ti,omap3-mcbsp";
549 reg = <0x49026000 0xff>;
551 interrupts = <23>, /* OCP compliant interrupt */
552 <54>, /* TX interrupt */
553 <55>; /* RX interrupt */
554 interrupt-names = "common", "tx", "rx";
555 ti,buffer-size = <128>;
556 ti,hwmods = "mcbsp4";
559 dma-names = "tx", "rx";
560 clocks = <&mcbsp4_fck>;
565 mcbsp5: mcbsp@48096000 {
566 compatible = "ti,omap3-mcbsp";
567 reg = <0x48096000 0xff>;
569 interrupts = <27>, /* OCP compliant interrupt */
570 <81>, /* TX interrupt */
571 <82>; /* RX interrupt */
572 interrupt-names = "common", "tx", "rx";
573 ti,buffer-size = <128>;
574 ti,hwmods = "mcbsp5";
577 dma-names = "tx", "rx";
578 clocks = <&mcbsp5_fck>;
583 sham: sham@480c3000 {
584 compatible = "ti,omap3-sham";
586 reg = <0x480c3000 0x64>;
592 smartreflex_core: smartreflex@480cb000 {
593 compatible = "ti,omap3-smartreflex-core";
594 ti,hwmods = "smartreflex_core";
595 reg = <0x480cb000 0x400>;
599 smartreflex_mpu_iva: smartreflex@480c9000 {
600 compatible = "ti,omap3-smartreflex-iva";
601 ti,hwmods = "smartreflex_mpu_iva";
602 reg = <0x480c9000 0x400>;
606 timer1: timer@48318000 {
607 compatible = "ti,omap3430-timer";
608 reg = <0x48318000 0x400>;
610 ti,hwmods = "timer1";
614 timer2: timer@49032000 {
615 compatible = "ti,omap3430-timer";
616 reg = <0x49032000 0x400>;
618 ti,hwmods = "timer2";
621 timer3: timer@49034000 {
622 compatible = "ti,omap3430-timer";
623 reg = <0x49034000 0x400>;
625 ti,hwmods = "timer3";
628 timer4: timer@49036000 {
629 compatible = "ti,omap3430-timer";
630 reg = <0x49036000 0x400>;
632 ti,hwmods = "timer4";
635 timer5: timer@49038000 {
636 compatible = "ti,omap3430-timer";
637 reg = <0x49038000 0x400>;
639 ti,hwmods = "timer5";
643 timer6: timer@4903a000 {
644 compatible = "ti,omap3430-timer";
645 reg = <0x4903a000 0x400>;
647 ti,hwmods = "timer6";
651 timer7: timer@4903c000 {
652 compatible = "ti,omap3430-timer";
653 reg = <0x4903c000 0x400>;
655 ti,hwmods = "timer7";
659 timer8: timer@4903e000 {
660 compatible = "ti,omap3430-timer";
661 reg = <0x4903e000 0x400>;
663 ti,hwmods = "timer8";
668 timer9: timer@49040000 {
669 compatible = "ti,omap3430-timer";
670 reg = <0x49040000 0x400>;
672 ti,hwmods = "timer9";
676 timer10: timer@48086000 {
677 compatible = "ti,omap3430-timer";
678 reg = <0x48086000 0x400>;
680 ti,hwmods = "timer10";
684 timer11: timer@48088000 {
685 compatible = "ti,omap3430-timer";
686 reg = <0x48088000 0x400>;
688 ti,hwmods = "timer11";
692 timer12: timer@48304000 {
693 compatible = "ti,omap3430-timer";
694 reg = <0x48304000 0x400>;
696 ti,hwmods = "timer12";
701 usbhstll: usbhstll@48062000 {
702 compatible = "ti,usbhs-tll";
703 reg = <0x48062000 0x1000>;
705 ti,hwmods = "usb_tll_hs";
708 usbhshost: usbhshost@48064000 {
709 compatible = "ti,usbhs-host";
710 reg = <0x48064000 0x400>;
711 ti,hwmods = "usb_host_hs";
712 #address-cells = <1>;
716 usbhsohci: ohci@48064400 {
717 compatible = "ti,ohci-omap3";
718 reg = <0x48064400 0x400>;
722 usbhsehci: ehci@48064800 {
723 compatible = "ti,ehci-omap";
724 reg = <0x48064800 0x400>;
729 gpmc: gpmc@6e000000 {
730 compatible = "ti,omap3430-gpmc";
732 reg = <0x6e000000 0x02d0>;
737 gpmc,num-waitpins = <4>;
738 #address-cells = <2>;
740 interrupt-controller;
741 #interrupt-cells = <2>;
746 usb_otg_hs: usb_otg_hs@480ab000 {
747 compatible = "ti,omap3-musb";
748 reg = <0x480ab000 0x1000>;
749 interrupts = <92>, <93>;
750 interrupt-names = "mc", "dma";
751 ti,hwmods = "usb_otg_hs";
758 compatible = "ti,omap3-dss";
759 reg = <0x48050000 0x200>;
761 ti,hwmods = "dss_core";
762 clocks = <&dss1_alwon_fck>;
764 #address-cells = <1>;
769 compatible = "ti,omap3-dispc";
770 reg = <0x48050400 0x400>;
772 ti,hwmods = "dss_dispc";
773 clocks = <&dss1_alwon_fck>;
777 dsi: encoder@4804fc00 {
778 compatible = "ti,omap3-dsi";
779 reg = <0x4804fc00 0x200>,
782 reg-names = "proto", "phy", "pll";
785 ti,hwmods = "dss_dsi1";
786 clocks = <&dss1_alwon_fck>, <&dss2_alwon_fck>;
787 clock-names = "fck", "sys_clk";
790 rfbi: encoder@48050800 {
791 compatible = "ti,omap3-rfbi";
792 reg = <0x48050800 0x100>;
794 ti,hwmods = "dss_rfbi";
795 clocks = <&dss1_alwon_fck>, <&dss_ick>;
796 clock-names = "fck", "ick";
799 venc: encoder@48050c00 {
800 compatible = "ti,omap3-venc";
801 reg = <0x48050c00 0x100>;
803 ti,hwmods = "dss_venc";
804 clocks = <&dss_tv_fck>;
809 ssi: ssi-controller@48058000 {
810 compatible = "ti,omap3-ssi";
815 reg = <0x48058000 0x1000>,
821 interrupt-names = "gdd_mpu";
823 #address-cells = <1>;
827 ssi_port1: ssi-port@4805a000 {
828 compatible = "ti,omap3-ssi-port";
830 reg = <0x4805a000 0x800>,
839 ssi_port2: ssi-port@4805b000 {
840 compatible = "ti,omap3-ssi-port";
842 reg = <0x4805b000 0x800>,
854 /include/ "omap3xxx-clocks.dtsi"