arch/arm/boot/dts/mt8135.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2014 MediaTek Inc.
   4  * Author: Joe.C <yingjoe.chen@mediatek.com>
   5  *
   6  */
   7
   8 #include <dt-bindings/clock/mt8135-clk.h>
   9 #include <dt-bindings/interrupt-controller/irq.h>
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11 #include <dt-bindings/reset/mt8135-resets.h>
  12 #include "skeleton64.dtsi"
  13 #include "mt8135-pinfunc.h"
  14
  15 / {
  16         compatible = "mediatek,mt8135";
  17         interrupt-parent = <&sysirq>;
  18
  19         cpu-map {
  20                 cluster0 {
  21                         core0 {
  22                                 cpu = <&cpu0>;
  23                         };
  24                         core1 {
  25                                 cpu = <&cpu1>;
  26                         };
  27                 };
  28
  29                 cluster1 {
  30                         core0 {
  31                                 cpu = <&cpu2>;
  32                         };
  33                         core1 {
  34                                 cpu = <&cpu3>;
  35                         };
  36                 };
  37         };
  38
  39         cpus {
  40                 #address-cells = <1>;
  41                 #size-cells = <0>;
  42                 enable-method = "mediatek,mt81xx-tz-smp";
  43
  44                 cpu0: cpu@0 {
  45                         device_type = "cpu";
  46                         compatible = "arm,cortex-a7";
  47                         reg = <0x000>;
  48                 };
  49
  50                 cpu1: cpu@1 {
  51                         device_type = "cpu";
  52                         compatible = "arm,cortex-a7";
  53                         reg = <0x001>;
  54                 };
  55
  56                 cpu2: cpu@100 {
  57                         device_type = "cpu";
  58                         compatible = "arm,cortex-a15";
  59                         reg = <0x100>;
  60                 };
  61
  62                 cpu3: cpu@101 {
  63                         device_type = "cpu";
  64                         compatible = "arm,cortex-a15";
  65                         reg = <0x101>;
  66                 };
  67         };
  68
  69         reserved-memory {
  70                 #address-cells = <2>;
  71                 #size-cells = <2>;
  72                 ranges;
  73
  74                 trustzone-bootinfo@80002000 {
  75                         compatible = "mediatek,trustzone-bootinfo";
  76                         reg = <0 0x80002000 0 0x1000>;
  77                 };
  78         };
  79
  80         clocks {
  81                 #address-cells = <2>;
  82                 #size-cells = <2>;
  83                 compatible = "simple-bus";
  84                 ranges;
  85
  86                 system_clk: dummy13m {
  87                         compatible = "fixed-clock";
  88                         clock-frequency = <13000000>;
  89                         #clock-cells = <0>;
  90                 };
  91
  92                 rtc_clk: dummy32k {
  93                         compatible = "fixed-clock";
  94                         clock-frequency = <32000>;
  95                         #clock-cells = <0>;
  96                 };
  97
  98                 clk26m: clk26m {
  99                         compatible = "fixed-clock";
 100                         #clock-cells = <0>;
 101                         clock-frequency = <26000000>;
 102                 };
 103         };
 104
 105         timer {
 106                 compatible = "arm,armv7-timer";
 107                 interrupt-parent = <&gic>;
 108                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
 109                                           IRQ_TYPE_LEVEL_LOW)>,
 110                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
 111                                           IRQ_TYPE_LEVEL_LOW)>,
 112                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
 113                                           IRQ_TYPE_LEVEL_LOW)>,
 114                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
 115                                           IRQ_TYPE_LEVEL_LOW)>;
 116                 clock-frequency = <13000000>;
 117                 arm,cpu-registers-not-fw-configured;
 118         };
 119
 120         soc {
 121                 #address-cells = <2>;
 122                 #size-cells = <2>;
 123                 compatible = "simple-bus";
 124                 ranges;
 125
 126                 topckgen: topckgen@10000000 {
 127                         compatible = "mediatek,mt8135-topckgen";
 128                         reg = <0 0x10000000 0 0x1000>;
 129                         #clock-cells = <1>;
 130                 };
 131
 132                 infracfg: infracfg@10001000 {
 133                         #reset-cells = <1>;
 134                         #clock-cells = <1>;
 135                         compatible = "mediatek,mt8135-infracfg", "syscon";
 136                         reg = <0 0x10001000 0 0x1000>;
 137                 };
 138
 139                 pericfg: pericfg@10003000 {
 140                         #reset-cells = <1>;
 141                         #clock-cells = <1>;
 142                         compatible = "mediatek,mt8135-pericfg", "syscon";
 143                         reg = <0 0x10003000 0 0x1000>;
 144                 };
 145
 146                 /*
 147                  * Pinctrl access register at 0x10005000 and 0x1020c000 through
 148                  * regmap. Register 0x1000b000 is used by EINT.
 149                  */
 150                 pio: pinctrl@10005000 {
 151                         compatible = "mediatek,mt8135-pinctrl";
 152                         reg = <0 0x1000b000 0 0x1000>;
 153                         mediatek,pctl-regmap = <&syscfg_pctl_a &syscfg_pctl_b>;
 154                         pins-are-numbered;
 155                         gpio-controller;
 156                         #gpio-cells = <2>;
 157                         interrupt-controller;
 158                         #interrupt-cells = <2>;
 159                         interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 160                                      <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 161                                      <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
 162                 };
 163
 164                 syscfg_pctl_a: syscfg_pctl_a@10005000 {
 165                         compatible = "mediatek,mt8135-pctl-a-syscfg", "syscon";
 166                         reg = <0 0x10005000 0 0x1000>;
 167                 };
 168
 169                 timer: timer@10008000 {
 170                         compatible = "mediatek,mt8135-timer",
 171                                         "mediatek,mt6577-timer";
 172                         reg = <0 0x10008000 0 0x80>;
 173                         interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_LOW>;
 174                         clocks = <&system_clk>, <&rtc_clk>;
 175                         clock-names = "system-clk", "rtc-clk";
 176                 };
 177
 178                 pwrap: pwrap@1000f000 {
 179                         compatible = "mediatek,mt8135-pwrap";
 180                         reg = <0 0x1000f000 0 0x1000>,
 181                                 <0 0x11017000 0 0x1000>;
 182                         reg-names = "pwrap", "pwrap-bridge";
 183                         interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
 184                         resets = <&infracfg MT8135_INFRA_PMIC_WRAP_RST>,
 185                                         <&pericfg MT8135_PERI_PWRAP_BRIDGE_SW_RST>;
 186                         reset-names = "pwrap", "pwrap-bridge";
 187                         clocks = <&clk26m>, <&clk26m>;
 188                         clock-names = "spi", "wrap";
 189                 };
 190
 191                 sysirq: interrupt-controller@10200030 {
 192                         compatible = "mediatek,mt8135-sysirq",
 193                                      "mediatek,mt6577-sysirq";
 194                         interrupt-controller;
 195                         #interrupt-cells = <3>;
 196                         interrupt-parent = <&gic>;
 197                         reg = <0 0x10200030 0 0x1c>;
 198                 };
 199
 200                 apmixedsys: apmixedsys@10209000 {
 201                         compatible = "mediatek,mt8135-apmixedsys";
 202                         reg = <0 0x10209000 0 0x1000>;
 203                         #clock-cells = <1>;
 204                 };
 205
 206                 syscfg_pctl_b: syscfg_pctl_b@1020c000 {
 207                         compatible = "mediatek,mt8135-pctl-b-syscfg", "syscon";
 208                         reg = <0 0x1020c000 0 0x1000>;
 209                 };
 210
 211                 gic: interrupt-controller@10211000 {
 212                         compatible = "arm,cortex-a15-gic";
 213                         interrupt-controller;
 214                         #interrupt-cells = <3>;
 215                         interrupt-parent = <&gic>;
 216                         reg = <0 0x10211000 0 0x1000>,
 217                               <0 0x10212000 0 0x2000>,
 218                               <0 0x10214000 0 0x2000>,
 219                               <0 0x10216000 0 0x2000>;
 220                 };
 221
 222                 uart0: serial@11006000 {
 223                         compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart";
 224                         reg = <0 0x11006000 0 0x400>;
 225                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
 226                         clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
 227                         clock-names = "baud", "bus";
 228                         status = "disabled";
 229                 };
 230
 231                 uart1: serial@11007000 {
 232                         compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart";
 233                         reg = <0 0x11007000 0 0x400>;
 234                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
 235                         clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
 236                         clock-names = "baud", "bus";
 237                         status = "disabled";
 238                 };
 239
 240                 uart2: serial@11008000 {
 241                         compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart";
 242                         reg = <0 0x11008000 0 0x400>;
 243                         interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
 244                         clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
 245                         clock-names = "baud", "bus";
 246                         status = "disabled";
 247                 };
 248
 249                 uart3: serial@11009000 {
 250                         compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart";
 251                         reg = <0 0x11009000 0 0x400>;
 252                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
 253                         clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
 254                         clock-names = "baud", "bus";
 255                         status = "disabled";
 256                 };
 257
 258         };
 259 };