2 * Copyright (c) 2017 MediaTek Inc.
3 * Author: John Crispin <john@phrozen.org>
4 * Sean Wang <sean.wang@mediatek.com>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <dt-bindings/interrupt-controller/irq.h>
17 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 #include <dt-bindings/clock/mt2701-clk.h>
19 #include <dt-bindings/pinctrl/mt7623-pinfunc.h>
20 #include <dt-bindings/power/mt2701-power.h>
21 #include <dt-bindings/gpio/gpio.h>
22 #include <dt-bindings/phy/phy.h>
23 #include <dt-bindings/reset/mt2701-resets.h>
24 #include <dt-bindings/thermal/thermal.h>
27 compatible = "mediatek,mt7623";
28 interrupt-parent = <&sysirq>;
32 cpu_opp_table: opp_table {
33 compatible = "operating-points-v2";
37 opp-hz = /bits/ 64 <98000000>;
38 opp-microvolt = <1050000>;
42 opp-hz = /bits/ 64 <198000000>;
43 opp-microvolt = <1050000>;
47 opp-hz = /bits/ 64 <398000000>;
48 opp-microvolt = <1050000>;
52 opp-hz = /bits/ 64 <598000000>;
53 opp-microvolt = <1050000>;
57 opp-hz = /bits/ 64 <747500000>;
58 opp-microvolt = <1050000>;
62 opp-hz = /bits/ 64 <1040000000>;
63 opp-microvolt = <1150000>;
67 opp-hz = /bits/ 64 <1196000000>;
68 opp-microvolt = <1200000>;
72 opp-hz = /bits/ 64 <1300000000>;
73 opp-microvolt = <1300000>;
80 enable-method = "mediatek,mt6589-smp";
84 compatible = "arm,cortex-a7";
86 clocks = <&infracfg CLK_INFRA_CPUSEL>,
87 <&apmixedsys CLK_APMIXED_MAINPLL>;
88 clock-names = "cpu", "intermediate";
89 operating-points-v2 = <&cpu_opp_table>;
91 cooling-min-level = <0>;
92 cooling-max-level = <7>;
93 clock-frequency = <1300000000>;
98 compatible = "arm,cortex-a7";
100 operating-points-v2 = <&cpu_opp_table>;
101 #cooling-cells = <2>;
102 clock-frequency = <1300000000>;
107 compatible = "arm,cortex-a7";
109 operating-points-v2 = <&cpu_opp_table>;
110 #cooling-cells = <2>;
111 clock-frequency = <1300000000>;
116 compatible = "arm,cortex-a7";
118 operating-points-v2 = <&cpu_opp_table>;
119 #cooling-cells = <2>;
120 clock-frequency = <1300000000>;
124 system_clk: dummy13m {
125 compatible = "fixed-clock";
126 clock-frequency = <13000000>;
130 rtc32k: oscillator@1 {
131 compatible = "fixed-clock";
133 clock-frequency = <32000>;
134 clock-output-names = "rtc32k";
137 clk26m: oscillator@0 {
138 compatible = "fixed-clock";
140 clock-frequency = <26000000>;
141 clock-output-names = "clk26m";
145 cpu_thermal: cpu_thermal {
146 polling-delay-passive = <1000>;
147 polling-delay = <1000>;
149 thermal-sensors = <&thermal 0>;
152 cpu_passive: cpu_passive {
153 temperature = <47000>;
158 cpu_active: cpu_active {
159 temperature = <67000>;
165 temperature = <87000>;
171 temperature = <107000>;
179 trip = <&cpu_passive>;
180 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
184 trip = <&cpu_active>;
185 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
190 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
197 compatible = "arm,armv7-timer";
198 interrupt-parent = <&gic>;
199 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
200 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
201 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
202 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
203 clock-frequency = <13000000>;
204 arm,cpu-registers-not-fw-configured;
207 topckgen: syscon@10000000 {
208 compatible = "mediatek,mt7623-topckgen",
209 "mediatek,mt2701-topckgen",
211 reg = <0 0x10000000 0 0x1000>;
215 infracfg: syscon@10001000 {
216 compatible = "mediatek,mt7623-infracfg",
217 "mediatek,mt2701-infracfg",
219 reg = <0 0x10001000 0 0x1000>;
224 pericfg: syscon@10003000 {
225 compatible = "mediatek,mt7623-pericfg",
226 "mediatek,mt2701-pericfg",
228 reg = <0 0x10003000 0 0x1000>;
233 pio: pinctrl@10005000 {
234 compatible = "mediatek,mt7623-pinctrl",
235 "mediatek,mt2701-pinctrl";
236 reg = <0 0x1000b000 0 0x1000>;
237 mediatek,pctl-regmap = <&syscfg_pctl_a>;
241 interrupt-controller;
242 interrupt-parent = <&gic>;
243 #interrupt-cells = <2>;
244 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
245 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
248 syscfg_pctl_a: syscfg@10005000 {
249 compatible = "mediatek,mt7623-pctl-a-syscfg", "syscon";
250 reg = <0 0x10005000 0 0x1000>;
253 scpsys: scpsys@10006000 {
254 compatible = "mediatek,mt7623-scpsys",
255 "mediatek,mt2701-scpsys",
257 #power-domain-cells = <1>;
258 reg = <0 0x10006000 0 0x1000>;
259 infracfg = <&infracfg>;
260 clocks = <&topckgen CLK_TOP_MM_SEL>,
261 <&topckgen CLK_TOP_MFG_SEL>,
262 <&topckgen CLK_TOP_ETHIF_SEL>;
263 clock-names = "mm", "mfg", "ethif";
266 watchdog: watchdog@10007000 {
267 compatible = "mediatek,mt7623-wdt",
268 "mediatek,mt6589-wdt";
269 reg = <0 0x10007000 0 0x100>;
272 timer: timer@10008000 {
273 compatible = "mediatek,mt7623-timer",
274 "mediatek,mt6577-timer";
275 reg = <0 0x10008000 0 0x80>;
276 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
277 clocks = <&system_clk>, <&rtc32k>;
278 clock-names = "system-clk", "rtc-clk";
281 pwrap: pwrap@1000d000 {
282 compatible = "mediatek,mt7623-pwrap",
283 "mediatek,mt2701-pwrap";
284 reg = <0 0x1000d000 0 0x1000>;
286 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
287 resets = <&infracfg MT2701_INFRA_PMIC_WRAP_RST>;
288 reset-names = "pwrap";
289 clocks = <&infracfg CLK_INFRA_PMICSPI>,
290 <&infracfg CLK_INFRA_PMICWRAP>;
291 clock-names = "spi", "wrap";
295 compatible = "mediatek,mt7623-cir";
296 reg = <0 0x10013000 0 0x1000>;
297 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>;
298 clocks = <&infracfg CLK_INFRA_IRRX>;
303 sysirq: interrupt-controller@10200100 {
304 compatible = "mediatek,mt7623-sysirq",
305 "mediatek,mt6577-sysirq";
306 interrupt-controller;
307 #interrupt-cells = <3>;
308 interrupt-parent = <&gic>;
309 reg = <0 0x10200100 0 0x1c>;
312 efuse: efuse@10206000 {
313 compatible = "mediatek,mt7623-efuse",
314 "mediatek,mt8173-efuse";
315 reg = <0 0x10206000 0 0x1000>;
316 #address-cells = <1>;
318 thermal_calibration_data: calib@424 {
323 apmixedsys: syscon@10209000 {
324 compatible = "mediatek,mt7623-apmixedsys",
325 "mediatek,mt2701-apmixedsys",
327 reg = <0 0x10209000 0 0x1000>;
332 compatible = "mediatek,mt7623-rng";
333 reg = <0 0x1020f000 0 0x1000>;
334 clocks = <&infracfg CLK_INFRA_TRNG>;
338 gic: interrupt-controller@10211000 {
339 compatible = "arm,cortex-a7-gic";
340 interrupt-controller;
341 #interrupt-cells = <3>;
342 interrupt-parent = <&gic>;
343 reg = <0 0x10211000 0 0x1000>,
344 <0 0x10212000 0 0x2000>,
345 <0 0x10214000 0 0x2000>,
346 <0 0x10216000 0 0x2000>;
349 auxadc: adc@11001000 {
350 compatible = "mediatek,mt7623-auxadc",
351 "mediatek,mt2701-auxadc";
352 reg = <0 0x11001000 0 0x1000>;
353 clocks = <&pericfg CLK_PERI_AUXADC>;
354 clock-names = "main";
355 #io-channel-cells = <1>;
358 uart0: serial@11002000 {
359 compatible = "mediatek,mt7623-uart",
360 "mediatek,mt6577-uart";
361 reg = <0 0x11002000 0 0x400>;
362 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
363 clocks = <&pericfg CLK_PERI_UART0_SEL>,
364 <&pericfg CLK_PERI_UART0>;
365 clock-names = "baud", "bus";
369 uart1: serial@11003000 {
370 compatible = "mediatek,mt7623-uart",
371 "mediatek,mt6577-uart";
372 reg = <0 0x11003000 0 0x400>;
373 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
374 clocks = <&pericfg CLK_PERI_UART1_SEL>,
375 <&pericfg CLK_PERI_UART1>;
376 clock-names = "baud", "bus";
380 uart2: serial@11004000 {
381 compatible = "mediatek,mt7623-uart",
382 "mediatek,mt6577-uart";
383 reg = <0 0x11004000 0 0x400>;
384 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
385 clocks = <&pericfg CLK_PERI_UART2_SEL>,
386 <&pericfg CLK_PERI_UART2>;
387 clock-names = "baud", "bus";
391 uart3: serial@11005000 {
392 compatible = "mediatek,mt7623-uart",
393 "mediatek,mt6577-uart";
394 reg = <0 0x11005000 0 0x400>;
395 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
396 clocks = <&pericfg CLK_PERI_UART3_SEL>,
397 <&pericfg CLK_PERI_UART3>;
398 clock-names = "baud", "bus";
403 compatible = "mediatek,mt7623-pwm";
404 reg = <0 0x11006000 0 0x1000>;
406 clocks = <&topckgen CLK_TOP_PWM_SEL>,
407 <&pericfg CLK_PERI_PWM>,
408 <&pericfg CLK_PERI_PWM1>,
409 <&pericfg CLK_PERI_PWM2>,
410 <&pericfg CLK_PERI_PWM3>,
411 <&pericfg CLK_PERI_PWM4>,
412 <&pericfg CLK_PERI_PWM5>;
413 clock-names = "top", "main", "pwm1", "pwm2",
414 "pwm3", "pwm4", "pwm5";
419 compatible = "mediatek,mt7623-i2c",
420 "mediatek,mt6577-i2c";
421 reg = <0 0x11007000 0 0x70>,
422 <0 0x11000200 0 0x80>;
423 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_LOW>;
425 clocks = <&pericfg CLK_PERI_I2C0>,
426 <&pericfg CLK_PERI_AP_DMA>;
427 clock-names = "main", "dma";
428 #address-cells = <1>;
434 compatible = "mediatek,mt7623-i2c",
435 "mediatek,mt6577-i2c";
436 reg = <0 0x11008000 0 0x70>,
437 <0 0x11000280 0 0x80>;
438 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>;
440 clocks = <&pericfg CLK_PERI_I2C1>,
441 <&pericfg CLK_PERI_AP_DMA>;
442 clock-names = "main", "dma";
443 #address-cells = <1>;
449 compatible = "mediatek,mt7623-i2c",
450 "mediatek,mt6577-i2c";
451 reg = <0 0x11009000 0 0x70>,
452 <0 0x11000300 0 0x80>;
453 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_LOW>;
455 clocks = <&pericfg CLK_PERI_I2C2>,
456 <&pericfg CLK_PERI_AP_DMA>;
457 clock-names = "main", "dma";
458 #address-cells = <1>;
464 compatible = "mediatek,mt7623-spi",
465 "mediatek,mt2701-spi";
466 #address-cells = <1>;
468 reg = <0 0x1100a000 0 0x100>;
469 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
470 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
471 <&topckgen CLK_TOP_SPI0_SEL>,
472 <&pericfg CLK_PERI_SPI0>;
473 clock-names = "parent-clk", "sel-clk", "spi-clk";
477 thermal: thermal@1100b000 {
478 #thermal-sensor-cells = <1>;
479 compatible = "mediatek,mt7623-thermal",
480 "mediatek,mt2701-thermal";
481 reg = <0 0x1100b000 0 0x1000>;
482 interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>;
483 clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>;
484 clock-names = "therm", "auxadc";
485 resets = <&pericfg MT2701_PERI_THERM_SW_RST>;
486 reset-names = "therm";
487 mediatek,auxadc = <&auxadc>;
488 mediatek,apmixedsys = <&apmixedsys>;
489 nvmem-cells = <&thermal_calibration_data>;
490 nvmem-cell-names = "calibration-data";
493 nandc: nfi@1100d000 {
494 compatible = "mediatek,mt7623-nfc",
495 "mediatek,mt2701-nfc";
496 reg = <0 0x1100d000 0 0x1000>;
497 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>;
498 power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
499 clocks = <&pericfg CLK_PERI_NFI>,
500 <&pericfg CLK_PERI_NFI_PAD>;
501 clock-names = "nfi_clk", "pad_clk";
504 #address-cells = <1>;
509 compatible = "mediatek,mt7623-ecc",
510 "mediatek,mt2701-ecc";
511 reg = <0 0x1100e000 0 0x1000>;
512 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;
513 clocks = <&pericfg CLK_PERI_NFI_ECC>;
514 clock-names = "nfiecc_clk";
519 compatible = "mediatek,mt7623-spi",
520 "mediatek,mt2701-spi";
521 #address-cells = <1>;
523 reg = <0 0x11016000 0 0x100>;
524 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
525 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
526 <&topckgen CLK_TOP_SPI1_SEL>,
527 <&pericfg CLK_PERI_SPI1>;
528 clock-names = "parent-clk", "sel-clk", "spi-clk";
533 compatible = "mediatek,mt7623-spi",
534 "mediatek,mt2701-spi";
535 #address-cells = <1>;
537 reg = <0 0x11017000 0 0x1000>;
538 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_LOW>;
539 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
540 <&topckgen CLK_TOP_SPI2_SEL>,
541 <&pericfg CLK_PERI_SPI2>;
542 clock-names = "parent-clk", "sel-clk", "spi-clk";
546 afe: audio-controller@11220000 {
547 compatible = "mediatek,mt7623-audio",
548 "mediatek,mt2701-audio";
549 reg = <0 0x11220000 0 0x2000>,
550 <0 0x112a0000 0 0x20000>;
551 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
552 power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
554 clocks = <&infracfg CLK_INFRA_AUDIO>,
555 <&topckgen CLK_TOP_AUD_MUX1_SEL>,
556 <&topckgen CLK_TOP_AUD_MUX2_SEL>,
557 <&topckgen CLK_TOP_AUD_MUX1_DIV>,
558 <&topckgen CLK_TOP_AUD_MUX2_DIV>,
559 <&topckgen CLK_TOP_AUD_48K_TIMING>,
560 <&topckgen CLK_TOP_AUD_44K_TIMING>,
561 <&topckgen CLK_TOP_AUDPLL_MUX_SEL>,
562 <&topckgen CLK_TOP_APLL_SEL>,
563 <&topckgen CLK_TOP_AUD1PLL_98M>,
564 <&topckgen CLK_TOP_AUD2PLL_90M>,
565 <&topckgen CLK_TOP_HADDS2PLL_98M>,
566 <&topckgen CLK_TOP_HADDS2PLL_294M>,
567 <&topckgen CLK_TOP_AUDPLL>,
568 <&topckgen CLK_TOP_AUDPLL_D4>,
569 <&topckgen CLK_TOP_AUDPLL_D8>,
570 <&topckgen CLK_TOP_AUDPLL_D16>,
571 <&topckgen CLK_TOP_AUDPLL_D24>,
572 <&topckgen CLK_TOP_AUDINTBUS_SEL>,
574 <&topckgen CLK_TOP_SYSPLL1_D4>,
575 <&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
576 <&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
577 <&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
578 <&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
579 <&topckgen CLK_TOP_AUD_K5_SRC_SEL>,
580 <&topckgen CLK_TOP_AUD_K6_SRC_SEL>,
581 <&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
582 <&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
583 <&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
584 <&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
585 <&topckgen CLK_TOP_AUD_K5_SRC_DIV>,
586 <&topckgen CLK_TOP_AUD_K6_SRC_DIV>,
587 <&topckgen CLK_TOP_AUD_I2S1_MCLK>,
588 <&topckgen CLK_TOP_AUD_I2S2_MCLK>,
589 <&topckgen CLK_TOP_AUD_I2S3_MCLK>,
590 <&topckgen CLK_TOP_AUD_I2S4_MCLK>,
591 <&topckgen CLK_TOP_AUD_I2S5_MCLK>,
592 <&topckgen CLK_TOP_AUD_I2S6_MCLK>,
593 <&topckgen CLK_TOP_ASM_M_SEL>,
594 <&topckgen CLK_TOP_ASM_H_SEL>,
595 <&topckgen CLK_TOP_UNIVPLL2_D4>,
596 <&topckgen CLK_TOP_UNIVPLL2_D2>,
597 <&topckgen CLK_TOP_SYSPLL_D5>;
599 clock-names = "infra_sys_audio_clk",
600 "top_audio_mux1_sel",
601 "top_audio_mux2_sel",
602 "top_audio_mux1_div",
603 "top_audio_mux2_div",
604 "top_audio_48k_timing",
605 "top_audio_44k_timing",
606 "top_audpll_mux_sel",
610 "top_hadds2_pll_98M",
611 "top_hadds2_pll_294M",
620 "top_aud_k1_src_sel",
621 "top_aud_k2_src_sel",
622 "top_aud_k3_src_sel",
623 "top_aud_k4_src_sel",
624 "top_aud_k5_src_sel",
625 "top_aud_k6_src_sel",
626 "top_aud_k1_src_div",
627 "top_aud_k2_src_div",
628 "top_aud_k3_src_div",
629 "top_aud_k4_src_div",
630 "top_aud_k5_src_div",
631 "top_aud_k6_src_div",
646 compatible = "mediatek,mt7623-mmc",
647 "mediatek,mt8135-mmc";
648 reg = <0 0x11230000 0 0x1000>;
649 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>;
650 clocks = <&pericfg CLK_PERI_MSDC30_0>,
651 <&topckgen CLK_TOP_MSDC30_0_SEL>;
652 clock-names = "source", "hclk";
657 compatible = "mediatek,mt7623-mmc",
658 "mediatek,mt8135-mmc";
659 reg = <0 0x11240000 0 0x1000>;
660 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_LOW>;
661 clocks = <&pericfg CLK_PERI_MSDC30_1>,
662 <&topckgen CLK_TOP_MSDC30_1_SEL>;
663 clock-names = "source", "hclk";
667 hifsys: syscon@1a000000 {
668 compatible = "mediatek,mt7623-hifsys",
669 "mediatek,mt2701-hifsys",
671 reg = <0 0x1a000000 0 0x1000>;
677 compatible = "mediatek,mt7623-xhci",
678 "mediatek,mt8173-xhci";
679 reg = <0 0x1a1c0000 0 0x1000>,
680 <0 0x1a1c4700 0 0x0100>;
681 reg-names = "mac", "ippc";
682 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_LOW>;
683 clocks = <&hifsys CLK_HIFSYS_USB0PHY>,
684 <&topckgen CLK_TOP_ETHIF_SEL>;
685 clock-names = "sys_ck", "free_ck";
686 power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
687 phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>;
691 u3phy1: usb-phy@1a1c4000 {
692 compatible = "mediatek,mt7623-u3phy",
693 "mediatek,mt2701-u3phy";
694 reg = <0 0x1a1c4000 0 0x0700>;
696 clock-names = "u3phya_ref";
697 #address-cells = <2>;
702 u2port0: usb-phy@1a1c4800 {
703 reg = <0 0x1a1c4800 0 0x0100>;
708 u3port0: usb-phy@1a1c4900 {
709 reg = <0 0x1a1c4900 0 0x0700>;
716 compatible = "mediatek,mt7623-xhci",
717 "mediatek,mt8173-xhci";
718 reg = <0 0x1a240000 0 0x1000>,
719 <0 0x1a244700 0 0x0100>;
720 reg-names = "mac", "ippc";
721 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_LOW>;
722 clocks = <&hifsys CLK_HIFSYS_USB1PHY>,
723 <&topckgen CLK_TOP_ETHIF_SEL>;
724 clock-names = "sys_ck", "free_ck";
725 power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
726 phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>;
730 u3phy2: usb-phy@1a244000 {
731 compatible = "mediatek,mt7623-u3phy",
732 "mediatek,mt2701-u3phy";
733 reg = <0 0x1a244000 0 0x0700>;
735 clock-names = "u3phya_ref";
736 #address-cells = <2>;
741 u2port1: usb-phy@1a244800 {
742 reg = <0 0x1a244800 0 0x0100>;
747 u3port1: usb-phy@1a244900 {
748 reg = <0 0x1a244900 0 0x0700>;
754 ethsys: syscon@1b000000 {
755 compatible = "mediatek,mt7623-ethsys",
756 "mediatek,mt2701-ethsys",
758 reg = <0 0x1b000000 0 0x1000>;
763 eth: ethernet@1b100000 {
764 compatible = "mediatek,mt7623-eth",
765 "mediatek,mt2701-eth",
767 reg = <0 0x1b100000 0 0x20000>;
768 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW>,
769 <GIC_SPI 199 IRQ_TYPE_LEVEL_LOW>,
770 <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
771 clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
772 <ðsys CLK_ETHSYS_ESW>,
773 <ðsys CLK_ETHSYS_GP1>,
774 <ðsys CLK_ETHSYS_GP2>,
775 <&apmixedsys CLK_APMIXED_TRGPLL>;
776 clock-names = "ethif", "esw", "gp1", "gp2", "trgpll";
777 resets = <ðsys MT2701_ETHSYS_FE_RST>,
778 <ðsys MT2701_ETHSYS_GMAC_RST>,
779 <ðsys MT2701_ETHSYS_PPE_RST>;
780 reset-names = "fe", "gmac", "ppe";
781 power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
782 mediatek,ethsys = <ðsys>;
783 mediatek,pctl = <&syscfg_pctl_a>;
784 #address-cells = <1>;
789 crypto: crypto@1b240000 {
790 compatible = "mediatek,mt7623-crypto";
791 reg = <0 0x1b240000 0 0x20000>;
792 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>,
793 <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>,
794 <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>,
795 <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>,
796 <GIC_SPI 97 IRQ_TYPE_LEVEL_LOW>;
797 clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
798 <ðsys CLK_ETHSYS_CRYPTO>;
799 clock-names = "ethif","cryp";
800 power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;