1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2014 MediaTek Inc.
4 * Author: Howard Chen <ibanezchen@gmail.com>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include "skeleton.dtsi"
13 compatible = "mediatek,mt6592";
14 interrupt-parent = <&sysirq>;
22 compatible = "arm,cortex-a7";
27 compatible = "arm,cortex-a7";
32 compatible = "arm,cortex-a7";
37 compatible = "arm,cortex-a7";
42 compatible = "arm,cortex-a7";
47 compatible = "arm,cortex-a7";
52 compatible = "arm,cortex-a7";
57 compatible = "arm,cortex-a7";
62 system_clk: dummy13m {
63 compatible = "fixed-clock";
64 clock-frequency = <13000000>;
69 compatible = "fixed-clock";
70 clock-frequency = <32000>;
75 compatible = "fixed-clock";
76 clock-frequency = <26000000>;
80 timer: timer@10008000 {
81 compatible = "mediatek,mt6577-timer";
82 reg = <0x10008000 0x80>;
83 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>;
84 clocks = <&system_clk>, <&rtc_clk>;
85 clock-names = "system-clk", "rtc-clk";
88 sysirq: interrupt-controller@10200220 {
89 compatible = "mediatek,mt6592-sysirq", "mediatek,mt6577-sysirq";
91 #interrupt-cells = <3>;
92 interrupt-parent = <&gic>;
93 reg = <0x10200220 0x1c>;
96 gic: interrupt-controller@10211000 {
97 compatible = "arm,cortex-a7-gic";
99 #interrupt-cells = <3>;
100 interrupt-parent = <&gic>;
101 reg = <0x10211000 0x1000>,
105 uart0: serial@11002000 {
106 compatible = "mediatek,mt6577-uart";
107 reg = <0x11002000 0x400>;
108 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
109 clocks = <&uart_clk>;
113 uart1: serial@11003000 {
114 compatible = "mediatek,mt6577-uart";
115 reg = <0x11003000 0x400>;
116 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
117 clocks = <&uart_clk>;
121 uart2: serial@11004000 {
122 compatible = "mediatek,mt6577-uart";
123 reg = <0x11004000 0x400>;
124 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
125 clocks = <&uart_clk>;
129 uart3: serial@11005000 {
130 compatible = "mediatek,mt6577-uart";
131 reg = <0x11005000 0x400>;
132 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
133 clocks = <&uart_clk>;