2 * Copyright (c) 2015 MediaTek Inc.
3 * Author: Erin.Lo <erin.lo@mediatek.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
15 #include <dt-bindings/interrupt-controller/irq.h>
16 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 #include "skeleton64.dtsi"
18 #include "mt2701-pinfunc.h"
21 compatible = "mediatek,mt2701";
22 interrupt-parent = <&sysirq>;
27 enable-method = "mediatek,mt81xx-tz-smp";
31 compatible = "arm,cortex-a7";
36 compatible = "arm,cortex-a7";
41 compatible = "arm,cortex-a7";
46 compatible = "arm,cortex-a7";
56 trustzone-bootinfo@80002000 {
57 compatible = "mediatek,trustzone-bootinfo";
58 reg = <0 0x80002000 0 0x1000>;
62 system_clk: dummy13m {
63 compatible = "fixed-clock";
64 clock-frequency = <13000000>;
69 compatible = "fixed-clock";
70 clock-frequency = <32000>;
75 compatible = "fixed-clock";
76 clock-frequency = <26000000>;
81 compatible = "arm,armv7-timer";
82 interrupt-parent = <&gic>;
83 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
84 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
85 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
86 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
89 pio: pinctrl@10005000 {
90 compatible = "mediatek,mt2701-pinctrl";
91 reg = <0 0x1000b000 0 0x1000>;
92 mediatek,pctl-regmap = <&syscfg_pctl_a>;
97 #interrupt-cells = <2>;
98 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
99 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
102 syscfg_pctl_a: syscfg@10005000 {
103 compatible = "mediatek,mt2701-pctl-a-syscfg", "syscon";
104 reg = <0 0x10005000 0 0x1000>;
107 watchdog: watchdog@10007000 {
108 compatible = "mediatek,mt2701-wdt",
109 "mediatek,mt6589-wdt";
110 reg = <0 0x10007000 0 0x100>;
113 timer: timer@10008000 {
114 compatible = "mediatek,mt2701-timer",
115 "mediatek,mt6577-timer";
116 reg = <0 0x10008000 0 0x80>;
117 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
118 clocks = <&system_clk>, <&rtc_clk>;
119 clock-names = "system-clk", "rtc-clk";
122 sysirq: interrupt-controller@10200100 {
123 compatible = "mediatek,mt2701-sysirq",
124 "mediatek,mt6577-sysirq";
125 interrupt-controller;
126 #interrupt-cells = <3>;
127 interrupt-parent = <&gic>;
128 reg = <0 0x10200100 0 0x1c>;
131 gic: interrupt-controller@10211000 {
132 compatible = "arm,cortex-a7-gic";
133 interrupt-controller;
134 #interrupt-cells = <3>;
135 interrupt-parent = <&gic>;
136 reg = <0 0x10211000 0 0x1000>,
137 <0 0x10212000 0 0x1000>,
138 <0 0x10214000 0 0x2000>,
139 <0 0x10216000 0 0x2000>;
142 uart0: serial@11002000 {
143 compatible = "mediatek,mt2701-uart",
144 "mediatek,mt6577-uart";
145 reg = <0 0x11002000 0 0x400>;
146 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
147 clocks = <&uart_clk>;
151 uart1: serial@11003000 {
152 compatible = "mediatek,mt2701-uart",
153 "mediatek,mt6577-uart";
154 reg = <0 0x11003000 0 0x400>;
155 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
156 clocks = <&uart_clk>;
160 uart2: serial@11004000 {
161 compatible = "mediatek,mt2701-uart",
162 "mediatek,mt6577-uart";
163 reg = <0 0x11004000 0 0x400>;
164 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
165 clocks = <&uart_clk>;
169 uart3: serial@11005000 {
170 compatible = "mediatek,mt2701-uart",
171 "mediatek,mt6577-uart";
172 reg = <0 0x11005000 0 0x400>;
173 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
174 clocks = <&uart_clk>;
178 mmsys: syscon@14000000 {
179 compatible = "mediatek,mt2701-mmsys", "syscon";
180 reg = <0 0x14000000 0 0x1000>;
184 imgsys: syscon@15000000 {
185 compatible = "mediatek,mt2701-imgsys", "syscon";
186 reg = <0 0x15000000 0 0x1000>;
190 vdecsys: syscon@16000000 {
191 compatible = "mediatek,mt2701-vdecsys", "syscon";
192 reg = <0 0x16000000 0 0x1000>;
196 hifsys: syscon@1a000000 {
197 compatible = "mediatek,mt2701-hifsys", "syscon";
198 reg = <0 0x1a000000 0 0x1000>;
203 ethsys: syscon@1b000000 {
204 compatible = "mediatek,mt2701-ethsys", "syscon";
205 reg = <0 0x1b000000 0 0x1000>;
210 bdpsys: syscon@1c000000 {
211 compatible = "mediatek,mt2701-bdpsys", "syscon";
212 reg = <0 0x1c000000 0 0x1000>;