1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2015 MediaTek Inc.
4 * Author: Erin Lo <erin.lo@mediatek.com>
12 model = "MediaTek MT2701 evaluation board";
13 compatible = "mediatek,mt2701-evb", "mediatek,mt2701";
16 reg = <0 0x80000000 0 0x40000000>;
20 compatible = "mediatek,mt2701-cs42448-machine";
21 mediatek,platform = <&afe>;
22 /* CS42448 Machine name */
24 "Line Out Jack", "AOUT1L",
25 "Line Out Jack", "AOUT1R",
26 "Line Out Jack", "AOUT2L",
27 "Line Out Jack", "AOUT2R",
28 "Line Out Jack", "AOUT3L",
29 "Line Out Jack", "AOUT3R",
30 "Line Out Jack", "AOUT4L",
31 "Line Out Jack", "AOUT4R",
36 "AIN3L", "Satellite Tuner In",
37 "AIN3R", "Satellite Tuner In",
40 mediatek,audio-codec = <&cs42448>;
41 mediatek,audio-codec-bt-mrg = <&bt_sco_codec>;
42 pinctrl-names = "default";
43 pinctrl-0 = <&aud_pins_default>;
44 i2s1-in-sel-gpio1 = <&pio 53 0>;
45 i2s1-in-sel-gpio2 = <&pio 54 0>;
49 bt_sco_codec:bt_sco_codec {
50 compatible = "linux,bt-sco";
53 backlight_lcd: backlight_lcd {
54 compatible = "pwm-backlight";
55 pwms = <&bls 0 100000>;
57 0 16 32 48 64 80 96 112
58 128 144 160 176 192 208 224 240
61 default-brightness-level = <9>;
71 pinctrl-names = "default";
72 pinctrl-0 = <&pwm_bls_gpio>;
76 pinctrl-names = "default";
77 pinctrl-0 = <&i2c0_pins_a>;
82 pinctrl-names = "default";
83 pinctrl-0 = <&i2c1_pins_a>;
88 pinctrl-names = "default";
89 pinctrl-0 = <&i2c2_pins_a>;
92 compatible = "cirrus,cs42448";
94 clocks = <&topckgen CLK_TOP_AUD_I2S1_MCLK>;
100 i2c0_pins_a: i2c0@0 {
102 pinmux = <MT2701_PIN_75_SDA0__FUNC_SDA0>,
103 <MT2701_PIN_76_SCL0__FUNC_SCL0>;
108 i2c1_pins_a: i2c1@0 {
110 pinmux = <MT2701_PIN_57_SDA1__FUNC_SDA1>,
111 <MT2701_PIN_58_SCL1__FUNC_SCL1>;
116 i2c2_pins_a: i2c2@0 {
118 pinmux = <MT2701_PIN_77_SDA2__FUNC_SDA2>,
119 <MT2701_PIN_78_SCL2__FUNC_SCL2>;
124 pwm_bls_gpio: pwm_bls_gpio {
126 pinmux = <MT2701_PIN_208_AUD_EXT_CK1__FUNC_DISP_PWM>;
132 pinmux = <MT2701_PIN_53_SPI0_CSN__FUNC_SPI0_CS>,
133 <MT2701_PIN_54_SPI0_CK__FUNC_SPI0_CK>,
134 <MT2701_PIN_55_SPI0_MI__FUNC_SPI0_MI>,
135 <MT2701_PIN_56_SPI0_MO__FUNC_SPI0_MO>;
140 aud_pins_default: audiodefault {
142 pinmux = <MT2701_PIN_49_I2S0_DATA__FUNC_I2S0_DATA>,
143 <MT2701_PIN_72_I2S0_DATA_IN__FUNC_I2S0_DATA_IN>,
144 <MT2701_PIN_73_I2S0_LRCK__FUNC_I2S0_LRCK>,
145 <MT2701_PIN_74_I2S0_BCK__FUNC_I2S0_BCK>,
146 <MT2701_PIN_126_I2S0_MCLK__FUNC_I2S0_MCLK>,
147 <MT2701_PIN_33_I2S1_DATA__FUNC_I2S1_DATA>,
148 <MT2701_PIN_34_I2S1_DATA_IN__FUNC_I2S1_DATA_IN>,
149 <MT2701_PIN_35_I2S1_BCK__FUNC_I2S1_BCK>,
150 <MT2701_PIN_36_I2S1_LRCK__FUNC_I2S1_LRCK>,
151 <MT2701_PIN_37_I2S1_MCLK__FUNC_I2S1_MCLK>,
152 <MT2701_PIN_203_PWM0__FUNC_I2S2_DATA>,
153 <MT2701_PIN_204_PWM1__FUNC_I2S3_DATA>,
154 <MT2701_PIN_53_SPI0_CSN__FUNC_GPIO53>,
155 <MT2701_PIN_54_SPI0_CK__FUNC_GPIO54>,
156 <MT2701_PIN_18_PCM_CLK__FUNC_MRG_CLK>,
157 <MT2701_PIN_19_PCM_SYNC__FUNC_MRG_SYNC>,
158 <MT2701_PIN_20_PCM_RX__FUNC_MRG_TX>,
159 <MT2701_PIN_21_PCM_TX__FUNC_MRG_RX>;
160 drive-strength = <MTK_DRIVE_12mA>;
167 pinmux = <MT2701_PIN_7_SPI1_CSN__FUNC_SPI1_CS>,
168 <MT2701_PIN_8_SPI1_MI__FUNC_SPI1_MI>,
169 <MT2701_PIN_9_SPI1_MO__FUNC_SPI1_MO>,
170 <MT2701_PIN_199_SPI1_CLK__FUNC_SPI1_CK>;
177 pinmux = <MT2701_PIN_101_SPI2_CSN__FUNC_SPI2_CS>,
178 <MT2701_PIN_102_SPI2_MI__FUNC_SPI2_MI>,
179 <MT2701_PIN_103_SPI2_MO__FUNC_SPI2_MO>,
180 <MT2701_PIN_104_SPI2_CLK__FUNC_SPI2_CK>;
187 pinctrl-names = "default";
188 pinctrl-0 = <&spi_pins_a>;
193 pinctrl-names = "default";
194 pinctrl-0 = <&spi_pins_b>;
199 pinctrl-names = "default";
200 pinctrl-0 = <&spi_pins_c>;
205 pinctrl-names = "default";
206 pinctrl-0 = <&nor_pins_default>;
209 compatible = "jedec,spi-nor";
215 nor_pins_default: nor {
217 pinmux = <MT2701_PIN_240_EXT_XCS__FUNC_EXT_XCS>,
218 <MT2701_PIN_241_EXT_SCK__FUNC_EXT_SCK>,
219 <MT2701_PIN_239_EXT_SDIO0__FUNC_EXT_SDIO0>,
220 <MT2701_PIN_238_EXT_SDIO1__FUNC_EXT_SDIO1>,
221 <MT2701_PIN_237_EXT_SDIO2__FUNC_EXT_SDIO2>,
222 <MT2701_PIN_236_EXT_SDIO3__FUNC_EXT_SDIO3>;
223 drive-strength = <MTK_DRIVE_4mA>;