1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (c) 2020 thingy.jp.
4 * Author: Daniel Palmer <daniel@thingy.jp>
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/mstar-msc313-mpll.h>
14 interrupt-parent = <&gic>;
22 compatible = "arm,cortex-a7";
25 clock-names = "cpuclk";
30 compatible = "arm,armv7-timer";
31 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2)
32 | IRQ_TYPE_LEVEL_LOW)>,
33 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2)
34 | IRQ_TYPE_LEVEL_LOW)>,
35 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2)
36 | IRQ_TYPE_LEVEL_LOW)>,
37 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2)
38 | IRQ_TYPE_LEVEL_LOW)>;
40 * we shouldn't need this but the vendor
43 clock-frequency = <6000000>;
44 arm,cpu-registers-not-fw-configured;
48 compatible = "arm,cortex-a7-pmu";
49 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
50 interrupt-affinity = <&cpu0>;
56 compatible = "fixed-clock";
57 clock-frequency = <24000000>;
62 compatible = "fixed-clock";
63 clock-frequency = <32768>;
67 xtal_div2: xtal_div2 {
69 compatible = "fixed-factor-clock";
77 compatible = "simple-bus";
80 ranges = <0x16001000 0x16001000 0x00007000>,
81 <0x1f000000 0x1f000000 0x00400000>,
82 <0xa0000000 0xa0000000 0x20000>;
84 gic: interrupt-controller@16001000 {
85 compatible = "arm,cortex-a7-gic";
86 reg = <0x16001000 0x1000>,
90 #interrupt-cells = <3>;
92 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2)
93 | IRQ_TYPE_LEVEL_LOW)>;
97 compatible = "simple-bus";
98 reg = <0x1f000000 0x00400000>;
101 ranges = <0x0 0x1f000000 0x00400000>;
103 pmsleep: syscon@1c00 {
104 compatible = "mstar,msc313-pmsleep", "syscon";
105 reg = <0x1c00 0x100>;
109 compatible = "syscon-reboot";
116 compatible = "mstar,msc313-rtc";
118 clocks = <&xtal_div2>;
119 interrupts-extended = <&intc_irq GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
123 compatible = "mstar,msc313e-wdt";
125 clocks = <&xtal_div2>;
129 intc_fiq: interrupt-controller@201310 {
130 compatible = "mstar,mst-intc";
131 reg = <0x201310 0x40>;
132 #interrupt-cells = <3>;
133 interrupt-controller;
134 interrupt-parent = <&gic>;
135 mstar,irqs-map-range = <96 127>;
138 intc_irq: interrupt-controller@201350 {
139 compatible = "mstar,mst-intc";
140 reg = <0x201350 0x40>;
141 #interrupt-cells = <3>;
142 interrupt-controller;
143 interrupt-parent = <&gic>;
144 mstar,irqs-map-range = <32 95>;
148 l3bridge: l3bridge@204400 {
149 compatible = "mstar,l3bridge";
150 reg = <0x204400 0x200>;
154 compatible = "mstar,msc313-mpll";
156 reg = <0x206000 0x200>;
160 cpupll: cpupll@206400 {
161 compatible = "mstar,msc313-cpupll";
162 reg = <0x206400 0x200>;
164 clocks = <&mpll MSTAR_MSC313_MPLL_DIV2>;
169 reg = <0x207800 0x200>;
171 #interrupt-cells = <2>;
172 interrupt-controller;
173 interrupt-parent = <&intc_fiq>;
177 pm_uart: uart@221000 {
178 compatible = "ns16550a";
179 reg = <0x221000 0x100>;
181 interrupts-extended = <&intc_irq GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
182 clock-frequency = <172000000>;
188 compatible = "mmio-sram";
189 reg = <0xa0000000 0x10000>;