1 // SPDX-License-Identifier: GPL-2.0 OR MIT
3 * Copyright 2014 Carlo Caione <carlo@caione.org>
6 #include <dt-bindings/clock/meson8b-clkc.h>
7 #include <dt-bindings/gpio/meson8-gpio.h>
8 #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
9 #include <dt-bindings/reset/amlogic,meson8b-reset.h>
13 model = "Amlogic Meson8 SoC";
14 compatible = "amlogic,meson8";
22 compatible = "arm,cortex-a9";
23 next-level-cache = <&L2>;
25 enable-method = "amlogic,meson8-smp";
26 resets = <&clkc CLKC_RESET_CPU0_SOFT_RESET>;
27 operating-points-v2 = <&cpu_opp_table>;
28 clocks = <&clkc CLKID_CPUCLK>;
33 compatible = "arm,cortex-a9";
34 next-level-cache = <&L2>;
36 enable-method = "amlogic,meson8-smp";
37 resets = <&clkc CLKC_RESET_CPU1_SOFT_RESET>;
38 operating-points-v2 = <&cpu_opp_table>;
39 clocks = <&clkc CLKID_CPUCLK>;
44 compatible = "arm,cortex-a9";
45 next-level-cache = <&L2>;
47 enable-method = "amlogic,meson8-smp";
48 resets = <&clkc CLKC_RESET_CPU2_SOFT_RESET>;
49 operating-points-v2 = <&cpu_opp_table>;
50 clocks = <&clkc CLKID_CPUCLK>;
55 compatible = "arm,cortex-a9";
56 next-level-cache = <&L2>;
58 enable-method = "amlogic,meson8-smp";
59 resets = <&clkc CLKC_RESET_CPU3_SOFT_RESET>;
60 operating-points-v2 = <&cpu_opp_table>;
61 clocks = <&clkc CLKID_CPUCLK>;
65 cpu_opp_table: opp-table {
66 compatible = "operating-points-v2";
70 opp-hz = /bits/ 64 <96000000>;
71 opp-microvolt = <825000>;
74 opp-hz = /bits/ 64 <192000000>;
75 opp-microvolt = <825000>;
78 opp-hz = /bits/ 64 <312000000>;
79 opp-microvolt = <825000>;
82 opp-hz = /bits/ 64 <408000000>;
83 opp-microvolt = <825000>;
86 opp-hz = /bits/ 64 <504000000>;
87 opp-microvolt = <825000>;
90 opp-hz = /bits/ 64 <600000000>;
91 opp-microvolt = <850000>;
94 opp-hz = /bits/ 64 <720000000>;
95 opp-microvolt = <850000>;
98 opp-hz = /bits/ 64 <816000000>;
99 opp-microvolt = <875000>;
102 opp-hz = /bits/ 64 <1008000000>;
103 opp-microvolt = <925000>;
106 opp-hz = /bits/ 64 <1200000000>;
107 opp-microvolt = <975000>;
110 opp-hz = /bits/ 64 <1416000000>;
111 opp-microvolt = <1025000>;
114 opp-hz = /bits/ 64 <1608000000>;
115 opp-microvolt = <1100000>;
119 opp-hz = /bits/ 64 <1800000000>;
120 opp-microvolt = <1125000>;
124 opp-hz = /bits/ 64 <1992000000>;
125 opp-microvolt = <1150000>;
129 gpu_opp_table: gpu-opp-table {
130 compatible = "operating-points-v2";
133 opp-hz = /bits/ 64 <182142857>;
134 opp-microvolt = <1150000>;
137 opp-hz = /bits/ 64 <318750000>;
138 opp-microvolt = <1150000>;
141 opp-hz = /bits/ 64 <425000000>;
142 opp-microvolt = <1150000>;
145 opp-hz = /bits/ 64 <510000000>;
146 opp-microvolt = <1150000>;
149 opp-hz = /bits/ 64 <637500000>;
150 opp-microvolt = <1150000>;
156 compatible = "arm,cortex-a9-pmu";
157 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
158 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
159 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
160 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
161 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
165 #address-cells = <1>;
169 /* 2 MiB reserved for Hardware ROM Firmware? */
171 reg = <0x0 0x200000>;
176 * 1 MiB reserved for the "ARM Power Firmware": this is ARM
177 * code which is responsible for system suspend. It loads a
178 * piece of ARC code ("arc_power" in the vendor u-boot tree)
179 * into SRAM, executes that and shuts down the (last) ARM core.
180 * The arc_power firmware then checks various wakeup sources
181 * (IR remote receiver, HDMI CEC, WIFI and Bluetooth wakeup or
182 * simply the power key) and re-starts the ARM core once it
183 * detects a wakeup request.
185 power-firmware@4f00000 {
186 reg = <0x4f00000 0x100000>;
191 mmcbus: bus@c8000000 {
192 compatible = "simple-bus";
193 reg = <0xc8000000 0x8000>;
194 #address-cells = <1>;
196 ranges = <0x0 0xc8000000 0x8000>;
199 compatible = "simple-bus";
200 reg = <0x6000 0x400>;
201 #address-cells = <1>;
203 ranges = <0x0 0x6000 0x400>;
205 canvas: video-lut@20 {
206 compatible = "amlogic,meson8-canvas",
214 compatible = "simple-bus";
215 reg = <0xd0000000 0x200000>;
216 #address-cells = <1>;
218 ranges = <0x0 0xd0000000 0x200000>;
221 compatible = "amlogic,meson8-mali", "arm,mali-450";
222 reg = <0xc0000 0x40000>;
223 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
224 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
225 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
226 <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
227 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
228 <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
229 <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
230 <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
231 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
232 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
233 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
234 <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
235 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
236 <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,
237 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
238 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
239 interrupt-names = "gp", "gpmmu", "pp", "pmu",
240 "pp0", "ppmmu0", "pp1", "ppmmu1",
241 "pp2", "ppmmu2", "pp4", "ppmmu4",
242 "pp5", "ppmmu5", "pp6", "ppmmu6";
243 resets = <&reset RESET_MALI>;
245 clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
246 clock-names = "bus", "core";
248 assigned-clocks = <&clkc CLKID_MALI>;
249 assigned-clock-rates = <318750000>;
251 operating-points-v2 = <&gpu_opp_table>;
258 compatible = "amlogic,meson8-pmu", "syscon";
262 pinctrl_aobus: pinctrl@84 {
263 compatible = "amlogic,meson8-aobus-pinctrl";
265 #address-cells = <1>;
269 gpio_ao: ao-bank@14 {
273 reg-names = "mux", "pull", "gpio";
276 gpio-ranges = <&pinctrl_aobus 0 0 16>;
279 uart_ao_a_pins: uart_ao_a {
281 groups = "uart_tx_ao_a", "uart_rx_ao_a";
282 function = "uart_ao";
287 i2c_ao_pins: i2c_mst_ao {
289 groups = "i2c_mst_sck_ao", "i2c_mst_sda_ao";
290 function = "i2c_mst_ao";
295 ir_recv_pins: remote {
297 groups = "remote_input";
303 pwm_f_ao_pins: pwm-f-ao {
306 function = "pwm_f_ao";
314 reset: reset-controller@4404 {
315 compatible = "amlogic,meson8b-reset";
320 analog_top: analog-top@81a8 {
321 compatible = "amlogic,meson8-analog-top", "syscon";
326 compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm";
333 compatible = "amlogic,meson8-clk-measure";
337 pinctrl_cbus: pinctrl@9880 {
338 compatible = "amlogic,meson8-cbus-pinctrl";
340 #address-cells = <1>;
349 reg-names = "mux", "pull", "pull-enable", "gpio";
352 gpio-ranges = <&pinctrl_cbus 0 0 120>;
357 groups = "sd_d0_a", "sd_d1_a", "sd_d2_a",
358 "sd_d3_a", "sd_clk_a", "sd_cmd_a";
366 groups = "sd_d0_b", "sd_d1_b", "sd_d2_b",
367 "sd_d3_b", "sd_clk_b", "sd_cmd_b";
375 groups = "sd_d0_c", "sd_d1_c", "sd_d2_c",
376 "sd_d3_c", "sd_clk_c", "sd_cmd_c";
384 groups = "nor_d", "nor_q", "nor_c", "nor_cs";
392 groups = "eth_tx_clk_50m", "eth_tx_en",
393 "eth_txd1", "eth_txd0",
394 "eth_rx_clk_in", "eth_rx_dv",
395 "eth_rxd1", "eth_rxd0", "eth_mdio",
397 function = "ethernet";
410 uart_a1_pins: uart-a1 {
412 groups = "uart_tx_a1",
419 uart_a1_cts_rts_pins: uart-a1-cts-rts {
421 groups = "uart_cts_a1",
432 compatible = "amlogic,meson8-smp-sram";
438 compatible = "amlogic,meson8-efuse";
439 clocks = <&clkc CLKID_EFUSE>;
440 clock-names = "core";
442 temperature_calib: calib@1f4 {
443 /* only the upper two bytes are relevant */
449 clocks = <&clkc CLKID_ETH>;
450 clock-names = "stmmaceth";
454 compatible = "amlogic,meson8-gpio-intc", "amlogic,meson-gpio-intc";
459 clkc: clock-controller {
460 compatible = "amlogic,meson8-clkc";
467 compatible = "amlogic,meson8-rng", "amlogic,meson-rng";
468 clocks = <&clkc CLKID_RNG0>;
469 clock-names = "core";
473 clocks = <&clkc CLKID_CLK81>;
477 clocks = <&clkc CLKID_CLK81>;
481 clocks = <&clkc CLKID_CLK81>;
485 arm,data-latency = <3 3 3>;
486 arm,tag-latency = <2 2 2>;
487 arm,filter-ranges = <0x100000 0xc0000000>;
489 prefetch-instr = <1>;
495 compatible = "arm,cortex-a9-scu";
500 compatible = "arm,cortex-a9-global-timer";
502 interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
503 clocks = <&clkc CLKID_PERIPH>;
506 * the arm_global_timer driver currently does not handle clock
507 * rate changes. Keep it disabled for now.
513 compatible = "arm,cortex-a9-twd-timer";
515 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
516 clocks = <&clkc CLKID_PERIPH>;
521 compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm";
525 compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm";
529 compatible = "amlogic,meson8-rtc";
530 resets = <&reset RESET_RTC>;
534 compatible = "amlogic,meson8-saradc", "amlogic,meson-saradc";
535 clocks = <&clkc CLKID_XTAL>,
536 <&clkc CLKID_SAR_ADC>;
537 clock-names = "clkin", "core";
538 amlogic,hhi-sysctrl = <&hhi>;
539 nvmem-cells = <&temperature_calib>;
540 nvmem-cell-names = "temperature_calib";
544 compatible = "amlogic,meson8-sdio", "amlogic,meson-mx-sdio";
545 clocks = <&clkc CLKID_SDIO>, <&clkc CLKID_CLK81>;
546 clock-names = "core", "clkin";
550 clocks = <&clkc CLKID_CLK81>;
554 clocks = <&clkc CLKID_XTAL>, <&clkc CLKID_CLK81>;
555 clock-names = "xtal", "pclk";
559 compatible = "amlogic,meson8-uart", "amlogic,meson-uart";
560 clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_CLK81>;
561 clock-names = "baud", "xtal", "pclk";
565 compatible = "amlogic,meson8-uart", "amlogic,meson-uart";
566 clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART0>;
567 clock-names = "baud", "xtal", "pclk";
571 compatible = "amlogic,meson8-uart", "amlogic,meson-uart";
572 clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART1>;
573 clock-names = "baud", "xtal", "pclk";
577 compatible = "amlogic,meson8-uart", "amlogic,meson-uart";
578 clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART2>;
579 clock-names = "baud", "xtal", "pclk";
583 compatible = "amlogic,meson8-usb", "snps,dwc2";
584 clocks = <&clkc CLKID_USB0_DDR_BRIDGE>;
589 compatible = "amlogic,meson8-usb", "snps,dwc2";
590 clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
595 compatible = "amlogic,meson8-usb2-phy", "amlogic,meson-mx-usb2-phy";
596 clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>;
597 clock-names = "usb_general", "usb";
598 resets = <&reset RESET_USB_OTG>;
602 compatible = "amlogic,meson8-usb2-phy", "amlogic,meson-mx-usb2-phy";
603 clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>;
604 clock-names = "usb_general", "usb";
605 resets = <&reset RESET_USB_OTG>;