1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
3 * Copyright 2018-2022 TQ-Systems GmbH
4 * Author: Markus Niebel <Markus.Niebel@tq-group.com>
8 model = "TQ-Systems MBA6ULx Baseboard";
21 backlight: backlight {
22 compatible = "pwm-backlight";
23 power-supply = <®_mba6ul_3v3>;
24 enable-gpios = <&expander_out0 4 GPIO_ACTIVE_HIGH>;
29 compatible = "gpio-beeper";
30 gpios = <&expander_out1 6 GPIO_ACTIVE_HIGH>;
33 gpio_buttons: gpio-keys {
34 compatible = "gpio-keys";
35 pinctrl-names = "default";
36 pinctrl-0 = <&pinctrl_buttons>;
41 gpios = <&expander_in0 0 GPIO_ACTIVE_LOW>;
47 gpios = <&expander_in0 1 GPIO_ACTIVE_LOW>;
53 gpios = <&expander_in0 2 GPIO_ACTIVE_LOW>;
58 linux,code = <KEY_POWER>;
59 gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
65 compatible = "gpio-leds";
70 gpios = <&expander_out1 4 GPIO_ACTIVE_HIGH>;
71 linux,default-trigger = "default-on";
76 gpios = <&expander_out1 5 GPIO_ACTIVE_HIGH>;
77 linux,default-trigger = "heartbeat";
81 reg_lcd_pwr: regulator-lcd-pwr {
82 compatible = "regulator-fixed";
83 regulator-name = "lcd-pwr";
84 gpio = <&expander_out0 1 GPIO_ACTIVE_HIGH>;
89 reg_mba6ul_3v3: regulator-mba6ul-3v3 {
90 compatible = "regulator-fixed";
91 regulator-name = "supply-mba6ul-3v3";
92 regulator-min-microvolt = <3300000>;
93 regulator-max-microvolt = <3300000>;
97 reg_mba6ul_5v0: regulator-mba6ul-5v0 {
98 compatible = "regulator-fixed";
99 regulator-name = "supply-mba6ul-5v0";
100 regulator-min-microvolt = <5000000>;
101 regulator-max-microvolt = <5000000>;
105 reg_mpcie: regulator-mpcie-3v3 {
106 compatible = "regulator-fixed";
107 regulator-name = "mpcie-3v3";
108 regulator-min-microvolt = <3300000>;
109 regulator-max-microvolt = <3300000>;
110 gpio = <&expander_out0 2 GPIO_ACTIVE_HIGH>;
113 startup-delay-us = <500000>;
114 vin-supply = <®_mba6ul_3v3>;
117 reg_otg2vbus_5v0: regulator-otg2-vbus-5v0 {
118 compatible = "regulator-fixed";
119 gpio = <&expander_out1 0 GPIO_ACTIVE_HIGH>;
121 regulator-name = "otg2-vbus-supply-5v0";
122 regulator-min-microvolt = <5000000>;
123 regulator-max-microvolt = <5000000>;
124 vin-supply = <®_mpcie>;
128 #address-cells = <1>;
133 compatible = "shared-dma-pool";
141 compatible = "fsl,imx-audio-tlv320aic32x4";
142 model = "imx-audio-tlv320aic32x4";
143 ssi-controller = <&sai1>;
144 audio-codec = <&tlv320aic32x4>;
145 audio-asrc = <&asrc>;
150 pinctrl-names = "default";
151 pinctrl-0 = <&pinctrl_flexcan1>;
152 xceiver-supply = <®_mba6ul_3v3>;
157 pinctrl-names = "default";
158 pinctrl-0 = <&pinctrl_flexcan2>;
159 xceiver-supply = <®_mba6ul_3v3>;
164 assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
165 assigned-clock-rates = <768000000>;
169 pinctrl-names = "default";
170 pinctrl-0 = <&pinctrl_ecspi2>;
176 pinctrl-names = "default";
177 pinctrl-0 = <&pinctrl_enet1>;
179 phy-handle = <ðphy0>;
180 phy-supply = <®_mba6ul_3v3>;
181 phy-reset-gpios = <&expander_out1 1 GPIO_ACTIVE_LOW>;
182 phy-reset-duration = <25>;
183 phy-reset-post-delay = <1>;
188 pinctrl-names = "default";
189 pinctrl-0 = <&pinctrl_enet2>, <&pinctrl_enet2_mdc>;
191 phy-handle = <ðphy1>;
192 phy-supply = <®_mba6ul_3v3>;
193 phy-reset-gpios = <&expander_out1 2 GPIO_ACTIVE_LOW>;
194 phy-reset-duration = <25>;
195 phy-reset-post-delay = <1>;
199 #address-cells = <1>;
202 ethphy0: ethernet-phy@0 {
203 compatible = "ethernet-phy-ieee802.3-c22";
204 clocks = <&clks IMX6UL_CLK_ENET_REF>;
209 ethphy1: ethernet-phy@1 {
210 compatible = "ethernet-phy-ieee802.3-c22";
211 clocks = <&clks IMX6UL_CLK_ENET2_REF_125M>;
219 tlv320aic32x4: audio-codec@18 {
220 compatible = "ti,tlv320aic32x4";
222 clocks = <&clks IMX6UL_CLK_SAI1>;
223 clock-names = "mclk";
224 ldoin-supply = <®_mba6ul_3v3>;
225 iov-supply = <®_mba6ul_3v3>;
228 jc42: temperature-sensor@19 {
229 compatible = "nxp,se97", "jedec,jc-42.4-temp";
233 expander_out0: gpio-expander@20 {
234 compatible = "nxp,pca9554";
240 expander_in0: gpio-expander@21 {
241 compatible = "nxp,pca9554";
243 pinctrl-names = "default";
244 pinctrl-0 = <&pinctrl_expander_in0>;
245 interrupt-parent = <&gpio4>;
246 interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
247 interrupt-controller;
248 #interrupt-cells = <2>;
265 expander_out1: gpio-expander@22 {
266 compatible = "nxp,pca9554";
272 analog_touch: touchscreen@41 {
273 compatible = "st,stmpe811";
275 interrupts = <21 IRQ_TYPE_EDGE_FALLING>;
276 interrupt-parent = <&gpio4>;
277 interrupt-controller;
281 compatible = "st,stmpe-ts";
282 st,adc-freq = <1>; /* 3.25 MHz ADC clock speed */
283 st,ave-ctrl = <3>; /* 8 sample average control */
284 st,fraction-z = <7>; /* 7 length fractional part in z */
286 * 50 mA typical 80 mA max touchscreen drivers
287 * current limit value
290 st,mod-12b = <1>; /* 12-bit ADC */
291 st,ref-sel = <0>; /* internal ADC reference */
292 st,sample-time = <4>; /* ADC converstion time: 80 clocks */
293 st,settling = <3>; /* 1 ms panel driver settling time */
294 st,touch-det-delay = <5>; /* 5 ms touch detect interrupt delay */
298 /* NXP SE97BTP with temperature sensor + eeprom */
300 compatible = "nxp,se97b", "atmel,24c02";
307 pinctrl-names = "default";
308 pinctrl-0 = <&pinctrl_pwm2>;
313 pinctrl-names = "default";
314 pinctrl-0 = <&pinctrl_sai1>;
315 assigned-clocks = <&clks IMX6UL_CLK_SAI1_SEL>,
316 <&clks IMX6UL_CLK_SAI1>;
317 assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
318 assigned-clock-rates = <0>, <24000000>;
319 fsl,sai-mclk-direction-output;
324 pinctrl-names = "default";
325 pinctrl-0 = <&pinctrl_uart1>;
330 pinctrl-names = "default";
331 pinctrl-0 = <&pinctrl_uart3>;
336 pinctrl-names = "default";
337 pinctrl-0 = <&pinctrl_uart6>;
338 /* for DTE mode, add below change */
340 /* pinctrl-0 = <&pinctrl_uart6dte>; */
342 linux,rs485-enabled-at-boot-time;
343 rs485-rts-active-low;
350 pinctrl-names = "default";
351 pinctrl-0 = <&pinctrl_usb_otg1>;
353 over-current-active-low;
354 /* we implement only dual role but not a fully featured OTG */
363 /* id, pwr, oc pins not connected */
365 disable-over-current;
366 vbus-supply = <®_otg2vbus_5v0>;
372 pinctrl-names = "default";
373 pinctrl-0 = <&pinctrl_usdhc1>;
374 cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
375 wp-gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>;
377 vmmc-supply = <®_mba6ul_3v3>;
378 vqmmc-supply = <®_vccsd>;
386 pinctrl-names = "default";
387 pinctrl-0 = <&pinctrl_wdog1>;
388 fsl,ext-reset-output;
393 pinctrl_buttons: buttonsgrp {
395 MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x100b0
399 pinctrl_ecspi2: ecspi2grp {
401 MX6UL_PAD_UART4_TX_DATA__ECSPI2_SCLK 0x1b020
402 MX6UL_PAD_UART5_RX_DATA__ECSPI2_MISO 0x1b020
403 MX6UL_PAD_UART5_TX_DATA__ECSPI2_MOSI 0x1b020
404 MX6UL_PAD_UART4_RX_DATA__ECSPI2_SS0 0x1b020
408 pinctrl_enet1: enet1grp {
410 MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
411 MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
412 MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
413 MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
414 MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
415 MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
416 MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
417 MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b0a8
421 pinctrl_enet2: enet2grp {
423 MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
424 MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
425 MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
426 MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
427 MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0a0
428 MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0a0
429 MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
430 MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b0a8
434 pinctrl_enet2_mdc: enet2mdcgrp {
437 MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
438 MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
442 pinctrl_expander_in0: expanderin0grp {
444 MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x1b0b1
448 pinctrl_flexcan1: flexcan1grp {
450 MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020
451 MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020
455 pinctrl_flexcan2: flexcan2grp {
457 MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020
458 MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020
462 pinctrl_pwm2: pwm2grp {
464 /* 100 k PD, DSE 120 OHM, SPPEED LO */
465 MX6UL_PAD_GPIO1_IO09__PWM2_OUT 0x00003050
469 pinctrl_sai1: sai1grp {
471 MX6UL_PAD_CSI_DATA05__SAI1_TX_BCLK 0x1b0b1
472 MX6UL_PAD_CSI_DATA04__SAI1_TX_SYNC 0x1b0b1
473 MX6UL_PAD_CSI_DATA07__SAI1_TX_DATA 0x1f0b8
474 MX6UL_PAD_CSI_DATA06__SAI1_RX_DATA 0x110b0
475 MX6UL_PAD_CSI_DATA01__SAI1_MCLK 0x1b0b1
479 pinctrl_uart1: uart1grp {
481 MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
482 MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
486 pinctrl_uart3: uart3grp {
488 MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1
489 MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1
493 pinctrl_uart6: uart6grp {
495 MX6UL_PAD_CSI_MCLK__UART6_DCE_TX 0x1b0b1
496 MX6UL_PAD_CSI_PIXCLK__UART6_DCE_RX 0x1b0b1
497 MX6UL_PAD_CSI_VSYNC__UART6_DCE_RTS 0x1b0b1
498 MX6UL_PAD_CSI_HSYNC__UART6_DCE_CTS 0x1b0b1
502 pinctrl_uart6dte: uart6dte {
504 MX6UL_PAD_CSI_PIXCLK__UART6_DTE_TX 0x1b0b1
505 MX6UL_PAD_CSI_MCLK__UART6_DTE_RX 0x1b0b1
506 MX6UL_PAD_CSI_HSYNC__UART6_DTE_RTS 0x1b0b1
507 MX6UL_PAD_CSI_VSYNC__UART6_DTE_CTS 0x1b0b1
511 pinctrl_usb_otg1: usbotg1grp {
513 MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x00017059
514 MX6UL_PAD_GPIO1_IO01__USB_OTG1_OC 0x0001b0b0
515 MX6UL_PAD_GPIO1_IO04__USB_OTG1_PWR 0x0001b099
519 pinctrl_usdhc1: usdhc1grp {
521 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x00017069
522 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x00017059
523 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x00017059
524 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x00017059
525 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x00017059
526 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x00017059
528 MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x0001b099
530 MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x0001b099
534 pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
536 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x00017069
537 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x000170b9
538 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x000170b9
539 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x000170b9
540 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x000170b9
541 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x000170b9
543 MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x0001b099
545 MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x0001b099
549 pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
551 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x00017069
552 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x000170f9
553 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x000170f9
554 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x000170f9
555 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x000170f9
556 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x000170f9
558 MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x0001b099
560 MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x0001b099
564 pinctrl_wdog1: wdog1grp {
566 MX6UL_PAD_GPIO1_IO08__WDOG1_WDOG_B 0x0001b099