1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright 2013-2014 Freescale Semiconductor, Inc.
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/thermal/thermal.h>
12 interrupt-parent = <&gic>;
34 compatible = "arm,cortex-a7";
37 clocks = <&clockgen 1 0>;
42 compatible = "arm,cortex-a7";
45 clocks = <&clockgen 1 0>;
51 device_type = "memory";
52 reg = <0x0 0x0 0x0 0x0>;
56 compatible = "fixed-clock";
58 clock-frequency = <100000000>;
59 clock-output-names = "sysclk";
63 compatible = "arm,armv7-timer";
64 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
65 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
66 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
67 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
71 compatible = "arm,cortex-a7-pmu";
72 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
73 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
74 interrupt-affinity = <&cpu0>, <&cpu1>;
78 compatible = "syscon-reboot";
85 compatible = "simple-bus";
89 interrupt-parent = <&gic>;
92 ddr: memory-controller@1080000 {
93 compatible = "fsl,qoriq-memory-controller";
94 reg = <0x0 0x1080000 0x0 0x1000>;
95 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
99 gic: interrupt-controller@1400000 {
100 compatible = "arm,gic-400", "arm,cortex-a7-gic";
101 #interrupt-cells = <3>;
102 interrupt-controller;
103 reg = <0x0 0x1401000 0x0 0x1000>,
104 <0x0 0x1402000 0x0 0x2000>,
105 <0x0 0x1404000 0x0 0x2000>,
106 <0x0 0x1406000 0x0 0x2000>;
107 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
111 msi1: msi-controller@1570e00 {
112 compatible = "fsl,ls1021a-msi";
113 reg = <0x0 0x1570e00 0x0 0x8>;
115 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
118 msi2: msi-controller@1570e08 {
119 compatible = "fsl,ls1021a-msi";
120 reg = <0x0 0x1570e08 0x0 0x8>;
122 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
125 ifc: memory-controller@1530000 {
126 compatible = "fsl,ifc";
127 reg = <0x0 0x1530000 0x0 0x10000>;
128 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
133 compatible = "fsl,ls1021a-dcfg", "syscon";
134 reg = <0x0 0x1ee0000 0x0 0x1000>;
139 compatible = "fsl,ls1021a-qspi";
140 #address-cells = <1>;
142 reg = <0x0 0x1550000 0x0 0x10000>,
143 <0x0 0x40000000 0x0 0x20000000>;
144 reg-names = "QuadSPI", "QuadSPI-memory";
145 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
146 clock-names = "qspi_en", "qspi";
147 clocks = <&clockgen 4 1>, <&clockgen 4 1>;
151 esdhc: esdhc@1560000 {
152 compatible = "fsl,ls1021a-esdhc", "fsl,esdhc";
153 reg = <0x0 0x1560000 0x0 0x10000>;
154 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
155 clock-frequency = <0>;
156 voltage-ranges = <1800 1800 3300 3300>;
164 compatible = "fsl,ls1021a-ahci";
165 reg = <0x0 0x3200000 0x0 0x10000>,
166 <0x0 0x20220520 0x0 0x4>;
167 reg-names = "ahci", "sata-ecc";
168 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
169 clocks = <&clockgen 4 1>;
175 compatible = "fsl,ls1021a-scfg", "syscon";
176 reg = <0x0 0x1570000 0x0 0x10000>;
178 #address-cells = <1>;
180 ranges = <0x0 0x0 0x1570000 0x10000>;
182 extirq: interrupt-controller@1ac {
183 compatible = "fsl,ls1021a-extirq";
184 #interrupt-cells = <2>;
185 #address-cells = <0>;
186 interrupt-controller;
189 <0 0 &gic GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
190 <1 0 &gic GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
191 <2 0 &gic GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
192 <3 0 &gic GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
193 <4 0 &gic GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
194 <5 0 &gic GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
195 interrupt-map-mask = <0x7 0x0>;
199 crypto: crypto@1700000 {
200 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
202 #address-cells = <1>;
204 reg = <0x0 0x1700000 0x0 0x100000>;
205 ranges = <0x0 0x0 0x1700000 0x100000>;
206 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
210 compatible = "fsl,sec-v5.0-job-ring",
211 "fsl,sec-v4.0-job-ring";
212 reg = <0x10000 0x10000>;
213 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
217 compatible = "fsl,sec-v5.0-job-ring",
218 "fsl,sec-v4.0-job-ring";
219 reg = <0x20000 0x10000>;
220 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
224 compatible = "fsl,sec-v5.0-job-ring",
225 "fsl,sec-v4.0-job-ring";
226 reg = <0x30000 0x10000>;
227 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
231 compatible = "fsl,sec-v5.0-job-ring",
232 "fsl,sec-v4.0-job-ring";
233 reg = <0x40000 0x10000>;
234 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
239 clockgen: clocking@1ee1000 {
240 compatible = "fsl,ls1021a-clockgen";
241 reg = <0x0 0x1ee1000 0x0 0x1000>;
247 compatible = "fsl,qoriq-tmu";
248 reg = <0x0 0x1f00000 0x0 0x10000>;
249 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
250 fsl,tmu-range = <0xb0000 0x9002c 0x6004e 0x30066>;
251 fsl,tmu-calibration = <0x00000000 0x00000020>,
252 <0x00000001 0x00000024>,
253 <0x00000002 0x0000002a>,
254 <0x00000003 0x00000032>,
255 <0x00000004 0x00000038>,
256 <0x00000005 0x0000003e>,
257 <0x00000006 0x00000043>,
258 <0x00000007 0x0000004a>,
259 <0x00000008 0x00000050>,
260 <0x00000009 0x00000059>,
261 <0x0000000a 0x0000005f>,
262 <0x0000000b 0x00000066>,
264 <0x00010000 0x00000023>,
265 <0x00010001 0x0000002b>,
266 <0x00010002 0x00000033>,
267 <0x00010003 0x0000003a>,
268 <0x00010004 0x00000042>,
269 <0x00010005 0x0000004a>,
270 <0x00010006 0x00000054>,
271 <0x00010007 0x0000005c>,
272 <0x00010008 0x00000065>,
273 <0x00010009 0x0000006f>,
275 <0x00020000 0x00000029>,
276 <0x00020001 0x00000033>,
277 <0x00020002 0x0000003d>,
278 <0x00020003 0x00000048>,
279 <0x00020004 0x00000054>,
280 <0x00020005 0x00000060>,
281 <0x00020006 0x0000006c>,
283 <0x00030000 0x00000025>,
284 <0x00030001 0x00000033>,
285 <0x00030002 0x00000043>,
286 <0x00030003 0x00000055>;
287 #thermal-sensor-cells = <1>;
291 compatible = "fsl,ls1021a-v1.0-dspi";
292 #address-cells = <1>;
294 reg = <0x0 0x2100000 0x0 0x10000>;
295 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
296 clock-names = "dspi";
297 clocks = <&clockgen 4 1>;
298 spi-num-chipselects = <6>;
304 compatible = "fsl,ls1021a-v1.0-dspi";
305 #address-cells = <1>;
307 reg = <0x0 0x2110000 0x0 0x10000>;
308 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
309 clock-names = "dspi";
310 clocks = <&clockgen 4 1>;
311 spi-num-chipselects = <6>;
317 compatible = "fsl,vf610-i2c";
318 #address-cells = <1>;
320 reg = <0x0 0x2180000 0x0 0x10000>;
321 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
322 clocks = <&clockgen 4 1>;
323 dma-names = "rx", "tx";
324 dmas = <&edma0 1 38>, <&edma0 1 39>;
329 compatible = "fsl,vf610-i2c";
330 #address-cells = <1>;
332 reg = <0x0 0x2190000 0x0 0x10000>;
333 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
334 clocks = <&clockgen 4 1>;
335 dma-names = "rx", "tx";
336 dmas = <&edma0 1 36>, <&edma0 1 37>;
341 compatible = "fsl,vf610-i2c";
342 #address-cells = <1>;
344 reg = <0x0 0x21a0000 0x0 0x10000>;
345 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
346 clocks = <&clockgen 4 1>;
347 dma-names = "rx", "tx";
348 dmas = <&edma0 1 34>, <&edma0 1 35>;
352 uart0: serial@21c0500 {
353 compatible = "fsl,16550-FIFO64", "ns16550a";
354 reg = <0x0 0x21c0500 0x0 0x100>;
355 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
356 clock-frequency = <0>;
361 uart1: serial@21c0600 {
362 compatible = "fsl,16550-FIFO64", "ns16550a";
363 reg = <0x0 0x21c0600 0x0 0x100>;
364 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
365 clock-frequency = <0>;
370 uart2: serial@21d0500 {
371 compatible = "fsl,16550-FIFO64", "ns16550a";
372 reg = <0x0 0x21d0500 0x0 0x100>;
373 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
374 clock-frequency = <0>;
379 uart3: serial@21d0600 {
380 compatible = "fsl,16550-FIFO64", "ns16550a";
381 reg = <0x0 0x21d0600 0x0 0x100>;
382 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
383 clock-frequency = <0>;
388 counter0: counter@29d0000 {
389 compatible = "fsl,ftm-quaddec";
390 reg = <0x0 0x29d0000 0x0 0x10000>;
395 counter1: counter@29e0000 {
396 compatible = "fsl,ftm-quaddec";
397 reg = <0x0 0x29e0000 0x0 0x10000>;
402 counter2: counter@29f0000 {
403 compatible = "fsl,ftm-quaddec";
404 reg = <0x0 0x29f0000 0x0 0x10000>;
409 counter3: counter@2a00000 {
410 compatible = "fsl,ftm-quaddec";
411 reg = <0x0 0x2a00000 0x0 0x10000>;
416 gpio0: gpio@2300000 {
417 compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
418 reg = <0x0 0x2300000 0x0 0x10000>;
419 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
422 interrupt-controller;
423 #interrupt-cells = <2>;
426 gpio1: gpio@2310000 {
427 compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
428 reg = <0x0 0x2310000 0x0 0x10000>;
429 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
432 interrupt-controller;
433 #interrupt-cells = <2>;
436 gpio2: gpio@2320000 {
437 compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
438 reg = <0x0 0x2320000 0x0 0x10000>;
439 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
442 interrupt-controller;
443 #interrupt-cells = <2>;
446 gpio3: gpio@2330000 {
447 compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
448 reg = <0x0 0x2330000 0x0 0x10000>;
449 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
452 interrupt-controller;
453 #interrupt-cells = <2>;
456 lpuart0: serial@2950000 {
457 compatible = "fsl,ls1021a-lpuart";
458 reg = <0x0 0x2950000 0x0 0x1000>;
459 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
465 lpuart1: serial@2960000 {
466 compatible = "fsl,ls1021a-lpuart";
467 reg = <0x0 0x2960000 0x0 0x1000>;
468 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
469 clocks = <&clockgen 4 1>;
474 lpuart2: serial@2970000 {
475 compatible = "fsl,ls1021a-lpuart";
476 reg = <0x0 0x2970000 0x0 0x1000>;
477 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
478 clocks = <&clockgen 4 1>;
483 lpuart3: serial@2980000 {
484 compatible = "fsl,ls1021a-lpuart";
485 reg = <0x0 0x2980000 0x0 0x1000>;
486 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
487 clocks = <&clockgen 4 1>;
492 lpuart4: serial@2990000 {
493 compatible = "fsl,ls1021a-lpuart";
494 reg = <0x0 0x2990000 0x0 0x1000>;
495 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
496 clocks = <&clockgen 4 1>;
501 lpuart5: serial@29a0000 {
502 compatible = "fsl,ls1021a-lpuart";
503 reg = <0x0 0x29a0000 0x0 0x1000>;
504 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
505 clocks = <&clockgen 4 1>;
511 compatible = "fsl,vf610-ftm-pwm";
513 reg = <0x0 0x29d0000 0x0 0x10000>;
514 clock-names = "ftm_sys", "ftm_ext",
515 "ftm_fix", "ftm_cnt_clk_en";
516 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
517 <&clockgen 4 1>, <&clockgen 4 1>;
523 compatible = "fsl,vf610-ftm-pwm";
525 reg = <0x0 0x29e0000 0x0 0x10000>;
526 clock-names = "ftm_sys", "ftm_ext",
527 "ftm_fix", "ftm_cnt_clk_en";
528 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
529 <&clockgen 4 1>, <&clockgen 4 1>;
535 compatible = "fsl,vf610-ftm-pwm";
537 reg = <0x0 0x29f0000 0x0 0x10000>;
538 clock-names = "ftm_sys", "ftm_ext",
539 "ftm_fix", "ftm_cnt_clk_en";
540 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
541 <&clockgen 4 1>, <&clockgen 4 1>;
547 compatible = "fsl,vf610-ftm-pwm";
549 reg = <0x0 0x2a00000 0x0 0x10000>;
550 clock-names = "ftm_sys", "ftm_ext",
551 "ftm_fix", "ftm_cnt_clk_en";
552 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
553 <&clockgen 4 1>, <&clockgen 4 1>;
559 compatible = "fsl,vf610-ftm-pwm";
561 reg = <0x0 0x2a10000 0x0 0x10000>;
562 clock-names = "ftm_sys", "ftm_ext",
563 "ftm_fix", "ftm_cnt_clk_en";
564 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
565 <&clockgen 4 1>, <&clockgen 4 1>;
571 compatible = "fsl,vf610-ftm-pwm";
573 reg = <0x0 0x2a20000 0x0 0x10000>;
574 clock-names = "ftm_sys", "ftm_ext",
575 "ftm_fix", "ftm_cnt_clk_en";
576 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
577 <&clockgen 4 1>, <&clockgen 4 1>;
583 compatible = "fsl,vf610-ftm-pwm";
585 reg = <0x0 0x2a30000 0x0 0x10000>;
586 clock-names = "ftm_sys", "ftm_ext",
587 "ftm_fix", "ftm_cnt_clk_en";
588 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
589 <&clockgen 4 1>, <&clockgen 4 1>;
595 compatible = "fsl,vf610-ftm-pwm";
597 reg = <0x0 0x2a40000 0x0 0x10000>;
598 clock-names = "ftm_sys", "ftm_ext",
599 "ftm_fix", "ftm_cnt_clk_en";
600 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
601 <&clockgen 4 1>, <&clockgen 4 1>;
606 wdog0: watchdog@2ad0000 {
607 compatible = "fsl,imx21-wdt";
608 reg = <0x0 0x2ad0000 0x0 0x10000>;
609 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
610 clocks = <&clockgen 4 1>;
611 clock-names = "wdog-en";
616 #sound-dai-cells = <0>;
617 compatible = "fsl,vf610-sai";
618 reg = <0x0 0x2b50000 0x0 0x10000>;
619 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
620 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
621 <&clockgen 4 1>, <&clockgen 4 1>;
622 clock-names = "bus", "mclk1", "mclk2", "mclk3";
623 dma-names = "tx", "rx";
624 dmas = <&edma0 1 47>,
630 #sound-dai-cells = <0>;
631 compatible = "fsl,vf610-sai";
632 reg = <0x0 0x2b60000 0x0 0x10000>;
633 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
634 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
635 <&clockgen 4 1>, <&clockgen 4 1>;
636 clock-names = "bus", "mclk1", "mclk2", "mclk3";
637 dma-names = "tx", "rx";
638 dmas = <&edma0 1 45>,
643 edma0: edma@2c00000 {
645 compatible = "fsl,vf610-edma";
646 reg = <0x0 0x2c00000 0x0 0x10000>,
647 <0x0 0x2c10000 0x0 0x10000>,
648 <0x0 0x2c20000 0x0 0x10000>;
649 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
650 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
651 interrupt-names = "edma-tx", "edma-err";
654 clock-names = "dmamux0", "dmamux1";
655 clocks = <&clockgen 4 1>,
660 compatible = "fsl,ls1021a-dcu";
661 reg = <0x0 0x2ce0000 0x0 0x10000>;
662 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
663 clocks = <&clockgen 4 0>,
665 clock-names = "dcu", "pix";
670 mdio0: mdio@2d24000 {
671 compatible = "gianfar";
672 device_type = "mdio";
673 #address-cells = <1>;
675 reg = <0x0 0x2d24000 0x0 0x4000>,
676 <0x0 0x2d10030 0x0 0x4>;
679 mdio1: mdio@2d64000 {
680 compatible = "gianfar";
681 device_type = "mdio";
682 #address-cells = <1>;
684 reg = <0x0 0x2d64000 0x0 0x4000>,
685 <0x0 0x2d50030 0x0 0x4>;
689 compatible = "fsl,etsec-ptp";
690 reg = <0x0 0x2d10e00 0x0 0xb0>;
691 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
692 fsl,tclk-period = <5>;
694 fsl,tmr-add = <0xaaaaaaab>;
695 fsl,tmr-fiper1 = <999999995>;
696 fsl,tmr-fiper2 = <999999995>;
697 fsl,max-adj = <499999999>;
701 enet0: ethernet@2d10000 {
702 compatible = "fsl,etsec2";
703 device_type = "network";
704 #address-cells = <2>;
706 interrupt-parent = <&gic>;
712 queue-group@2d10000 {
713 #address-cells = <2>;
715 reg = <0x0 0x2d10000 0x0 0x1000>;
716 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
717 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
718 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
721 queue-group@2d14000 {
722 #address-cells = <2>;
724 reg = <0x0 0x2d14000 0x0 0x1000>;
725 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
726 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
727 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
731 enet1: ethernet@2d50000 {
732 compatible = "fsl,etsec2";
733 device_type = "network";
734 #address-cells = <2>;
736 interrupt-parent = <&gic>;
741 queue-group@2d50000 {
742 #address-cells = <2>;
744 reg = <0x0 0x2d50000 0x0 0x1000>;
745 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
746 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
747 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
750 queue-group@2d54000 {
751 #address-cells = <2>;
753 reg = <0x0 0x2d54000 0x0 0x1000>;
754 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
755 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
756 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
760 enet2: ethernet@2d90000 {
761 compatible = "fsl,etsec2";
762 device_type = "network";
763 #address-cells = <2>;
765 interrupt-parent = <&gic>;
770 queue-group@2d90000 {
771 #address-cells = <2>;
773 reg = <0x0 0x2d90000 0x0 0x1000>;
774 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
775 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
776 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
779 queue-group@2d94000 {
780 #address-cells = <2>;
782 reg = <0x0 0x2d94000 0x0 0x1000>;
783 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
784 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
785 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
790 compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
791 reg = <0x0 0x8600000 0x0 0x1000>;
792 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
798 compatible = "snps,dwc3";
799 reg = <0x0 0x3100000 0x0 0x10000>;
800 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
802 snps,quirk-frame-length-adjustment = <0x20>;
803 snps,dis_rxdet_inp3_quirk;
804 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
808 compatible = "fsl,ls1021a-pcie";
809 reg = <0x00 0x03400000 0x0 0x00010000>, /* controller registers */
810 <0x40 0x00000000 0x0 0x00002000>; /* configuration space */
811 reg-names = "regs", "config";
812 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
813 fsl,pcie-scfg = <&scfg 0>;
814 #address-cells = <3>;
818 bus-range = <0x0 0xff>;
819 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000>, /* downstream I/O */
820 <0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
821 msi-parent = <&msi1>, <&msi2>;
822 #interrupt-cells = <1>;
823 interrupt-map-mask = <0 0 0 7>;
824 interrupt-map = <0000 0 0 1 &gic GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
825 <0000 0 0 2 &gic GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
826 <0000 0 0 3 &gic GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
827 <0000 0 0 4 &gic GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
832 compatible = "fsl,ls1021a-pcie";
833 reg = <0x00 0x03500000 0x0 0x00010000>, /* controller registers */
834 <0x48 0x00000000 0x0 0x00002000>; /* configuration space */
835 reg-names = "regs", "config";
836 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
837 fsl,pcie-scfg = <&scfg 1>;
838 #address-cells = <3>;
842 bus-range = <0x0 0xff>;
843 ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000>, /* downstream I/O */
844 <0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
845 msi-parent = <&msi1>, <&msi2>;
846 #interrupt-cells = <1>;
847 interrupt-map-mask = <0 0 0 7>;
848 interrupt-map = <0000 0 0 1 &gic GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
849 <0000 0 0 2 &gic GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
850 <0000 0 0 3 &gic GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
851 <0000 0 0 4 &gic GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
856 compatible = "fsl,ls1021ar2-flexcan";
857 reg = <0x0 0x2a70000 0x0 0x1000>;
858 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
859 clocks = <&clockgen 4 1>, <&clockgen 4 1>;
860 clock-names = "ipg", "per";
865 compatible = "fsl,ls1021ar2-flexcan";
866 reg = <0x0 0x2a80000 0x0 0x1000>;
867 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
868 clocks = <&clockgen 4 1>, <&clockgen 4 1>;
869 clock-names = "ipg", "per";
874 compatible = "fsl,ls1021ar2-flexcan";
875 reg = <0x0 0x2a90000 0x0 0x1000>;
876 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
877 clocks = <&clockgen 4 1>, <&clockgen 4 1>;
878 clock-names = "ipg", "per";
883 compatible = "fsl,ls1021ar2-flexcan";
884 reg = <0x0 0x2aa0000 0x0 0x1000>;
885 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
886 clocks = <&clockgen 4 1>, <&clockgen 4 1>;
887 clock-names = "ipg", "per";
891 ocram1: sram@10000000 {
892 compatible = "mmio-sram";
893 reg = <0x0 0x10000000 0x0 0x10000>;
894 #address-cells = <1>;
896 ranges = <0x0 0x0 0x10000000 0x10000>;
899 ocram2: sram@10010000 {
900 compatible = "mmio-sram";
901 reg = <0x0 0x10010000 0x0 0x10000>;
902 #address-cells = <1>;
904 ranges = <0x0 0x0 0x10010000 0x10000>;
907 qdma: dma-controller@8390000 {
908 compatible = "fsl,ls1021a-qdma";
909 reg = <0x0 0x8388000 0x0 0x1000>, /* Controller regs */
910 <0x0 0x8389000 0x0 0x1000>, /* Status regs */
911 <0x0 0x838a000 0x0 0x2000>; /* Block regs */
912 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
913 <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
914 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
915 interrupt-names = "qdma-error",
916 "qdma-queue0", "qdma-queue1";
920 block-offset = <0x1000>;
921 fsl,dma-queues = <2>;
923 queue-sizes = <64 64>;
927 rcpm: power-controller@1ee2140 {
928 compatible = "fsl,ls1021a-rcpm", "fsl,qoriq-rcpm-2.1+";
929 reg = <0x0 0x1ee2140 0x0 0x8>;
930 #fsl,rcpm-wakeup-cells = <2>;
931 #power-domain-cells = <0>;
934 ftm_alarm0: timer0@29d0000 {
935 compatible = "fsl,ls1021a-ftm-alarm";
936 reg = <0x0 0x29d0000 0x0 0x10000>;
938 fsl,rcpm-wakeup = <&rcpm 0x0 0x20000000>;
939 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
945 cpu_thermal: cpu-thermal {
946 polling-delay-passive = <1000>;
947 polling-delay = <5000>;
949 thermal-sensors = <&tmu 0>;
952 cpu_alert: cpu-alert {
953 temperature = <85000>;
958 temperature = <95000>;
968 <&cpu0 THERMAL_NO_LIMIT
970 <&cpu1 THERMAL_NO_LIMIT