arch/arm/boot/dts/ls1021a.dtsi

   1 /*
   2  * Copyright 2013-2014 Freescale Semiconductor, Inc.
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of
  12  *     the License, or (at your option) any later version.
  13  *
  14  *     This file is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  *     You should have received a copy of the GNU General Public
  20  *     License along with this file; if not, write to the Free
  21  *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
  22  *     MA 02110-1301 USA
  23  *
  24  * Or, alternatively,
  25  *
  26  *  b) Permission is hereby granted, free of charge, to any person
  27  *     obtaining a copy of this software and associated documentation
  28  *     files (the "Software"), to deal in the Software without
  29  *     restriction, including without limitation the rights to use,
  30  *     copy, modify, merge, publish, distribute, sublicense, and/or
  31  *     sell copies of the Software, and to permit persons to whom the
  32  *     Software is furnished to do so, subject to the following
  33  *     conditions:
  34  *
  35  *     The above copyright notice and this permission notice shall be
  36  *     included in all copies or substantial portions of the Software.
  37  *
  38  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  39  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  40  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  41  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  42  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  43  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  44  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  45  *     OTHER DEALINGS IN THE SOFTWARE.
  46  */
  47
  48 #include <dt-bindings/interrupt-controller/arm-gic.h>
  49 #include <dt-bindings/thermal/thermal.h>
  50
  51 / {
  52         #address-cells = <2>;
  53         #size-cells = <2>;
  54         compatible = "fsl,ls1021a";
  55         interrupt-parent = <&gic>;
  56
  57         aliases {
  58                 crypto = &crypto;
  59                 ethernet0 = &enet0;
  60                 ethernet1 = &enet1;
  61                 ethernet2 = &enet2;
  62                 rtc1 = &ftm_alarm0;
  63                 serial0 = &lpuart0;
  64                 serial1 = &lpuart1;
  65                 serial2 = &lpuart2;
  66                 serial3 = &lpuart3;
  67                 serial4 = &lpuart4;
  68                 serial5 = &lpuart5;
  69                 sysclk = &sysclk;
  70         };
  71
  72         cpus {
  73                 #address-cells = <1>;
  74                 #size-cells = <0>;
  75
  76                 cpu0: cpu@f00 {
  77                         compatible = "arm,cortex-a7";
  78                         device_type = "cpu";
  79                         reg = <0xf00>;
  80                         clocks = <&clockgen 1 0>;
  81                         #cooling-cells = <2>;
  82                 };
  83
  84                 cpu1: cpu@f01 {
  85                         compatible = "arm,cortex-a7";
  86                         device_type = "cpu";
  87                         reg = <0xf01>;
  88                         clocks = <&clockgen 1 0>;
  89                         #cooling-cells = <2>;
  90                 };
  91         };
  92
  93         memory {
  94                 device_type = "memory";
  95                 reg = <0x0 0x0 0x0 0x0>;
  96         };
  97
  98         sysclk: sysclk {
  99                 compatible = "fixed-clock";
 100                 #clock-cells = <0>;
 101                 clock-frequency = <100000000>;
 102                 clock-output-names = "sysclk";
 103         };
 104
 105         timer {
 106                 compatible = "arm,armv7-timer";
 107                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 108                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 109                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 110                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
 111         };
 112
 113         pmu {
 114                 compatible = "arm,cortex-a7-pmu";
 115                 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
 116                              <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
 117                 interrupt-affinity = <&cpu0>, <&cpu1>;
 118         };
 119
 120         reboot {
 121                 compatible = "syscon-reboot";
 122                 regmap = <&dcfg>;
 123                 offset = <0xb0>;
 124                 mask = <0x02>;
 125         };
 126
 127         soc {
 128                 compatible = "simple-bus";
 129                 #address-cells = <2>;
 130                 #size-cells = <2>;
 131                 device_type = "soc";
 132                 interrupt-parent = <&gic>;
 133                 ranges;
 134
 135                 ddr: memory-controller@1080000 {
 136                         compatible = "fsl,qoriq-memory-controller";
 137                         reg = <0x0 0x1080000 0x0 0x1000>;
 138                         interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
 139                         big-endian;
 140                 };
 141
 142                 gic: interrupt-controller@1400000 {
 143                         compatible = "arm,gic-400", "arm,cortex-a7-gic";
 144                         #interrupt-cells = <3>;
 145                         interrupt-controller;
 146                         reg = <0x0 0x1401000 0x0 0x1000>,
 147                               <0x0 0x1402000 0x0 0x2000>,
 148                               <0x0 0x1404000 0x0 0x2000>,
 149                               <0x0 0x1406000 0x0 0x2000>;
 150                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
 151
 152                 };
 153
 154                 msi1: msi-controller@1570e00 {
 155                         compatible = "fsl,ls1021a-msi";
 156                         reg = <0x0 0x1570e00 0x0 0x8>;
 157                         msi-controller;
 158                         interrupts =  <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
 159                 };
 160
 161                 msi2: msi-controller@1570e08 {
 162                         compatible = "fsl,ls1021a-msi";
 163                         reg = <0x0 0x1570e08 0x0 0x8>;
 164                         msi-controller;
 165                         interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
 166                 };
 167
 168                 ifc: ifc@1530000 {
 169                         compatible = "fsl,ifc", "simple-bus";
 170                         reg = <0x0 0x1530000 0x0 0x10000>;
 171                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 172                 };
 173
 174                 dcfg: dcfg@1ee0000 {
 175                         compatible = "fsl,ls1021a-dcfg", "syscon";
 176                         reg = <0x0 0x1ee0000 0x0 0x1000>;
 177                         big-endian;
 178                 };
 179
 180                 qspi: spi@1550000 {
 181                         compatible = "fsl,ls1021a-qspi";
 182                         #address-cells = <1>;
 183                         #size-cells = <0>;
 184                         reg = <0x0 0x1550000 0x0 0x10000>,
 185                               <0x0 0x40000000 0x0 0x20000000>;
 186                         reg-names = "QuadSPI", "QuadSPI-memory";
 187                         interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
 188                         clock-names = "qspi_en", "qspi";
 189                         clocks = <&clockgen 4 1>, <&clockgen 4 1>;
 190                         status = "disabled";
 191                 };
 192
 193                 esdhc: esdhc@1560000 {
 194                         compatible = "fsl,ls1021a-esdhc", "fsl,esdhc";
 195                         reg = <0x0 0x1560000 0x0 0x10000>;
 196                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 197                         clock-frequency = <0>;
 198                         voltage-ranges = <1800 1800 3300 3300>;
 199                         sdhci,auto-cmd12;
 200                         big-endian;
 201                         bus-width = <4>;
 202                         status = "disabled";
 203                 };
 204
 205                 sata: sata@3200000 {
 206                         compatible = "fsl,ls1021a-ahci";
 207                         reg = <0x0 0x3200000 0x0 0x10000>,
 208                               <0x0 0x20220520 0x0 0x4>;
 209                         reg-names = "ahci", "sata-ecc";
 210                         interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 211                         clocks = <&clockgen 4 1>;
 212                         dma-coherent;
 213                         status = "disabled";
 214                 };
 215
 216                 scfg: scfg@1570000 {
 217                         compatible = "fsl,ls1021a-scfg", "syscon";
 218                         reg = <0x0 0x1570000 0x0 0x10000>;
 219                         big-endian;
 220                         #address-cells = <1>;
 221                         #size-cells = <1>;
 222                         ranges = <0x0 0x0 0x1570000 0x10000>;
 223
 224                         extirq: interrupt-controller@1ac {
 225                                 compatible = "fsl,ls1021a-extirq";
 226                                 #interrupt-cells = <2>;
 227                                 #address-cells = <0>;
 228                                 interrupt-controller;
 229                                 reg = <0x1ac 4>;
 230                                 interrupt-map =
 231                                         <0 0 &gic GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
 232                                         <1 0 &gic GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
 233                                         <2 0 &gic GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
 234                                         <3 0 &gic GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
 235                                         <4 0 &gic GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
 236                                         <5 0 &gic GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
 237                                 interrupt-map-mask = <0xffffffff 0x0>;
 238                         };
 239                 };
 240
 241                 crypto: crypto@1700000 {
 242                         compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
 243                         fsl,sec-era = <7>;
 244                         #address-cells = <1>;
 245                         #size-cells = <1>;
 246                         reg              = <0x0 0x1700000 0x0 0x100000>;
 247                         ranges           = <0x0 0x0 0x1700000 0x100000>;
 248                         interrupts       = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 249                         dma-coherent;
 250
 251                         sec_jr0: jr@10000 {
 252                                 compatible = "fsl,sec-v5.0-job-ring",
 253                                      "fsl,sec-v4.0-job-ring";
 254                                 reg = <0x10000 0x10000>;
 255                                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 256                         };
 257
 258                         sec_jr1: jr@20000 {
 259                                 compatible = "fsl,sec-v5.0-job-ring",
 260                                      "fsl,sec-v4.0-job-ring";
 261                                 reg = <0x20000 0x10000>;
 262                                 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
 263                         };
 264
 265                         sec_jr2: jr@30000 {
 266                                 compatible = "fsl,sec-v5.0-job-ring",
 267                                      "fsl,sec-v4.0-job-ring";
 268                                 reg = <0x30000 0x10000>;
 269                                 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 270                         };
 271
 272                         sec_jr3: jr@40000 {
 273                                 compatible = "fsl,sec-v5.0-job-ring",
 274                                      "fsl,sec-v4.0-job-ring";
 275                                 reg = <0x40000 0x10000>;
 276                                 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 277                         };
 278
 279                 };
 280
 281                 clockgen: clocking@1ee1000 {
 282                         compatible = "fsl,ls1021a-clockgen";
 283                         reg = <0x0 0x1ee1000 0x0 0x1000>;
 284                         #clock-cells = <2>;
 285                         clocks = <&sysclk>;
 286                 };
 287
 288                 tmu: tmu@1f00000 {
 289                         compatible = "fsl,qoriq-tmu";
 290                         reg = <0x0 0x1f00000 0x0 0x10000>;
 291                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 292                         fsl,tmu-range = <0xb0000 0x9002c 0x6004e 0x30066>;
 293                         fsl,tmu-calibration = <0x00000000 0x00000020
 294                                                0x00000001 0x00000024
 295                                                0x00000002 0x0000002a
 296                                                0x00000003 0x00000032
 297                                                0x00000004 0x00000038
 298                                                0x00000005 0x0000003e
 299                                                0x00000006 0x00000043
 300                                                0x00000007 0x0000004a
 301                                                0x00000008 0x00000050
 302                                                0x00000009 0x00000059
 303                                                0x0000000a 0x0000005f
 304                                                0x0000000b 0x00000066
 305
 306                                                0x00010000 0x00000023
 307                                                0x00010001 0x0000002b
 308                                                0x00010002 0x00000033
 309                                                0x00010003 0x0000003a
 310                                                0x00010004 0x00000042
 311                                                0x00010005 0x0000004a
 312                                                0x00010006 0x00000054
 313                                                0x00010007 0x0000005c
 314                                                0x00010008 0x00000065
 315                                                0x00010009 0x0000006f
 316
 317                                                0x00020000 0x00000029
 318                                                0x00020001 0x00000033
 319                                                0x00020002 0x0000003d
 320                                                0x00020003 0x00000048
 321                                                0x00020004 0x00000054
 322                                                0x00020005 0x00000060
 323                                                0x00020006 0x0000006c
 324
 325                                                0x00030000 0x00000025
 326                                                0x00030001 0x00000033
 327                                                0x00030002 0x00000043
 328                                                0x00030003 0x00000055>;
 329                         #thermal-sensor-cells = <1>;
 330                 };
 331
 332                 dspi0: spi@2100000 {
 333                         compatible = "fsl,ls1021a-v1.0-dspi";
 334                         #address-cells = <1>;
 335                         #size-cells = <0>;
 336                         reg = <0x0 0x2100000 0x0 0x10000>;
 337                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 338                         clock-names = "dspi";
 339                         clocks = <&clockgen 4 1>;
 340                         spi-num-chipselects = <6>;
 341                         big-endian;
 342                         status = "disabled";
 343                 };
 344
 345                 dspi1: spi@2110000 {
 346                         compatible = "fsl,ls1021a-v1.0-dspi";
 347                         #address-cells = <1>;
 348                         #size-cells = <0>;
 349                         reg = <0x0 0x2110000 0x0 0x10000>;
 350                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 351                         clock-names = "dspi";
 352                         clocks = <&clockgen 4 1>;
 353                         spi-num-chipselects = <6>;
 354                         big-endian;
 355                         status = "disabled";
 356                 };
 357
 358                 i2c0: i2c@2180000 {
 359                         compatible = "fsl,vf610-i2c";
 360                         #address-cells = <1>;
 361                         #size-cells = <0>;
 362                         reg = <0x0 0x2180000 0x0 0x10000>;
 363                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 364                         clock-names = "i2c";
 365                         clocks = <&clockgen 4 1>;
 366                         dma-names = "tx", "rx";
 367                         dmas = <&edma0 1 39>, <&edma0 1 38>;
 368                         status = "disabled";
 369                 };
 370
 371                 i2c1: i2c@2190000 {
 372                         compatible = "fsl,vf610-i2c";
 373                         #address-cells = <1>;
 374                         #size-cells = <0>;
 375                         reg = <0x0 0x2190000 0x0 0x10000>;
 376                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 377                         clock-names = "i2c";
 378                         clocks = <&clockgen 4 1>;
 379                         dma-names = "tx", "rx";
 380                         dmas = <&edma0 1 37>, <&edma0 1 36>;
 381                         status = "disabled";
 382                 };
 383
 384                 i2c2: i2c@21a0000 {
 385                         compatible = "fsl,vf610-i2c";
 386                         #address-cells = <1>;
 387                         #size-cells = <0>;
 388                         reg = <0x0 0x21a0000 0x0 0x10000>;
 389                         interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 390                         clock-names = "i2c";
 391                         clocks = <&clockgen 4 1>;
 392                         dma-names = "tx", "rx";
 393                         dmas = <&edma0 1 35>, <&edma0 1 34>;
 394                         status = "disabled";
 395                 };
 396
 397                 uart0: serial@21c0500 {
 398                         compatible = "fsl,16550-FIFO64", "ns16550a";
 399                         reg = <0x0 0x21c0500 0x0 0x100>;
 400                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 401                         clock-frequency = <0>;
 402                         fifo-size = <15>;
 403                         status = "disabled";
 404                 };
 405
 406                 uart1: serial@21c0600 {
 407                         compatible = "fsl,16550-FIFO64", "ns16550a";
 408                         reg = <0x0 0x21c0600 0x0 0x100>;
 409                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 410                         clock-frequency = <0>;
 411                         fifo-size = <15>;
 412                         status = "disabled";
 413                 };
 414
 415                 uart2: serial@21d0500 {
 416                         compatible = "fsl,16550-FIFO64", "ns16550a";
 417                         reg = <0x0 0x21d0500 0x0 0x100>;
 418                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 419                         clock-frequency = <0>;
 420                         fifo-size = <15>;
 421                         status = "disabled";
 422                 };
 423
 424                 uart3: serial@21d0600 {
 425                         compatible = "fsl,16550-FIFO64", "ns16550a";
 426                         reg = <0x0 0x21d0600 0x0 0x100>;
 427                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 428                         clock-frequency = <0>;
 429                         fifo-size = <15>;
 430                         status = "disabled";
 431                 };
 432
 433                 counter0: counter@29d0000 {
 434                         compatible = "fsl,ftm-quaddec";
 435                         reg = <0x0 0x29d0000 0x0 0x10000>;
 436                         big-endian;
 437                         status = "disabled";
 438                 };
 439
 440                 counter1: counter@29e0000 {
 441                         compatible = "fsl,ftm-quaddec";
 442                         reg = <0x0 0x29e0000 0x0 0x10000>;
 443                         big-endian;
 444                         status = "disabled";
 445                 };
 446
 447                 counter2: counter@29f0000 {
 448                         compatible = "fsl,ftm-quaddec";
 449                         reg = <0x0 0x29f0000 0x0 0x10000>;
 450                         big-endian;
 451                         status = "disabled";
 452                 };
 453
 454                 counter3: counter@2a00000 {
 455                         compatible = "fsl,ftm-quaddec";
 456                         reg = <0x0 0x2a00000 0x0 0x10000>;
 457                         big-endian;
 458                         status = "disabled";
 459                 };
 460
 461                 gpio0: gpio@2300000 {
 462                         compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
 463                         reg = <0x0 0x2300000 0x0 0x10000>;
 464                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 465                         gpio-controller;
 466                         #gpio-cells = <2>;
 467                         interrupt-controller;
 468                         #interrupt-cells = <2>;
 469                 };
 470
 471                 gpio1: gpio@2310000 {
 472                         compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
 473                         reg = <0x0 0x2310000 0x0 0x10000>;
 474                         interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 475                         gpio-controller;
 476                         #gpio-cells = <2>;
 477                         interrupt-controller;
 478                         #interrupt-cells = <2>;
 479                 };
 480
 481                 gpio2: gpio@2320000 {
 482                         compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
 483                         reg = <0x0 0x2320000 0x0 0x10000>;
 484                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 485                         gpio-controller;
 486                         #gpio-cells = <2>;
 487                         interrupt-controller;
 488                         #interrupt-cells = <2>;
 489                 };
 490
 491                 gpio3: gpio@2330000 {
 492                         compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
 493                         reg = <0x0 0x2330000 0x0 0x10000>;
 494                         interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
 495                         gpio-controller;
 496                         #gpio-cells = <2>;
 497                         interrupt-controller;
 498                         #interrupt-cells = <2>;
 499                 };
 500
 501                 lpuart0: serial@2950000 {
 502                         compatible = "fsl,ls1021a-lpuart";
 503                         reg = <0x0 0x2950000 0x0 0x1000>;
 504                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 505                         clocks = <&sysclk>;
 506                         clock-names = "ipg";
 507                         status = "disabled";
 508                 };
 509
 510                 lpuart1: serial@2960000 {
 511                         compatible = "fsl,ls1021a-lpuart";
 512                         reg = <0x0 0x2960000 0x0 0x1000>;
 513                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 514                         clocks = <&clockgen 4 1>;
 515                         clock-names = "ipg";
 516                         status = "disabled";
 517                 };
 518
 519                 lpuart2: serial@2970000 {
 520                         compatible = "fsl,ls1021a-lpuart";
 521                         reg = <0x0 0x2970000 0x0 0x1000>;
 522                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 523                         clocks = <&clockgen 4 1>;
 524                         clock-names = "ipg";
 525                         status = "disabled";
 526                 };
 527
 528                 lpuart3: serial@2980000 {
 529                         compatible = "fsl,ls1021a-lpuart";
 530                         reg = <0x0 0x2980000 0x0 0x1000>;
 531                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 532                         clocks = <&clockgen 4 1>;
 533                         clock-names = "ipg";
 534                         status = "disabled";
 535                 };
 536
 537                 lpuart4: serial@2990000 {
 538                         compatible = "fsl,ls1021a-lpuart";
 539                         reg = <0x0 0x2990000 0x0 0x1000>;
 540                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 541                         clocks = <&clockgen 4 1>;
 542                         clock-names = "ipg";
 543                         status = "disabled";
 544                 };
 545
 546                 lpuart5: serial@29a0000 {
 547                         compatible = "fsl,ls1021a-lpuart";
 548                         reg = <0x0 0x29a0000 0x0 0x1000>;
 549                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 550                         clocks = <&clockgen 4 1>;
 551                         clock-names = "ipg";
 552                         status = "disabled";
 553                 };
 554
 555                 pwm0: pwm@29d0000 {
 556                         compatible = "fsl,vf610-ftm-pwm";
 557                         #pwm-cells = <3>;
 558                         reg = <0x0 0x29d0000 0x0 0x10000>;
 559                         clock-names = "ftm_sys", "ftm_ext",
 560                                 "ftm_fix", "ftm_cnt_clk_en";
 561                         clocks = <&clockgen 4 1>, <&clockgen 4 1>,
 562                                 <&clockgen 4 1>, <&clockgen 4 1>;
 563                         big-endian;
 564                         status = "disabled";
 565                 };
 566
 567                 pwm1: pwm@29e0000 {
 568                         compatible = "fsl,vf610-ftm-pwm";
 569                         #pwm-cells = <3>;
 570                         reg = <0x0 0x29e0000 0x0 0x10000>;
 571                         clock-names = "ftm_sys", "ftm_ext",
 572                                 "ftm_fix", "ftm_cnt_clk_en";
 573                         clocks = <&clockgen 4 1>, <&clockgen 4 1>,
 574                                 <&clockgen 4 1>, <&clockgen 4 1>;
 575                         big-endian;
 576                         status = "disabled";
 577                 };
 578
 579                 pwm2: pwm@29f0000 {
 580                         compatible = "fsl,vf610-ftm-pwm";
 581                         #pwm-cells = <3>;
 582                         reg = <0x0 0x29f0000 0x0 0x10000>;
 583                         clock-names = "ftm_sys", "ftm_ext",
 584                                 "ftm_fix", "ftm_cnt_clk_en";
 585                         clocks = <&clockgen 4 1>, <&clockgen 4 1>,
 586                                 <&clockgen 4 1>, <&clockgen 4 1>;
 587                         big-endian;
 588                         status = "disabled";
 589                 };
 590
 591                 pwm3: pwm@2a00000 {
 592                         compatible = "fsl,vf610-ftm-pwm";
 593                         #pwm-cells = <3>;
 594                         reg = <0x0 0x2a00000 0x0 0x10000>;
 595                         clock-names = "ftm_sys", "ftm_ext",
 596                                 "ftm_fix", "ftm_cnt_clk_en";
 597                         clocks = <&clockgen 4 1>, <&clockgen 4 1>,
 598                                 <&clockgen 4 1>, <&clockgen 4 1>;
 599                         big-endian;
 600                         status = "disabled";
 601                 };
 602
 603                 pwm4: pwm@2a10000 {
 604                         compatible = "fsl,vf610-ftm-pwm";
 605                         #pwm-cells = <3>;
 606                         reg = <0x0 0x2a10000 0x0 0x10000>;
 607                         clock-names = "ftm_sys", "ftm_ext",
 608                                 "ftm_fix", "ftm_cnt_clk_en";
 609                         clocks = <&clockgen 4 1>, <&clockgen 4 1>,
 610                                 <&clockgen 4 1>, <&clockgen 4 1>;
 611                         big-endian;
 612                         status = "disabled";
 613                 };
 614
 615                 pwm5: pwm@2a20000 {
 616                         compatible = "fsl,vf610-ftm-pwm";
 617                         #pwm-cells = <3>;
 618                         reg = <0x0 0x2a20000 0x0 0x10000>;
 619                         clock-names = "ftm_sys", "ftm_ext",
 620                                 "ftm_fix", "ftm_cnt_clk_en";
 621                         clocks = <&clockgen 4 1>, <&clockgen 4 1>,
 622                                 <&clockgen 4 1>, <&clockgen 4 1>;
 623                         big-endian;
 624                         status = "disabled";
 625                 };
 626
 627                 pwm6: pwm@2a30000 {
 628                         compatible = "fsl,vf610-ftm-pwm";
 629                         #pwm-cells = <3>;
 630                         reg = <0x0 0x2a30000 0x0 0x10000>;
 631                         clock-names = "ftm_sys", "ftm_ext",
 632                                 "ftm_fix", "ftm_cnt_clk_en";
 633                         clocks = <&clockgen 4 1>, <&clockgen 4 1>,
 634                                 <&clockgen 4 1>, <&clockgen 4 1>;
 635                         big-endian;
 636                         status = "disabled";
 637                 };
 638
 639                 pwm7: pwm@2a40000 {
 640                         compatible = "fsl,vf610-ftm-pwm";
 641                         #pwm-cells = <3>;
 642                         reg = <0x0 0x2a40000 0x0 0x10000>;
 643                         clock-names = "ftm_sys", "ftm_ext",
 644                                 "ftm_fix", "ftm_cnt_clk_en";
 645                         clocks = <&clockgen 4 1>, <&clockgen 4 1>,
 646                                 <&clockgen 4 1>, <&clockgen 4 1>;
 647                         big-endian;
 648                         status = "disabled";
 649                 };
 650
 651                 wdog0: watchdog@2ad0000 {
 652                         compatible = "fsl,imx21-wdt";
 653                         reg = <0x0 0x2ad0000 0x0 0x10000>;
 654                         interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 655                         clocks = <&clockgen 4 1>;
 656                         clock-names = "wdog-en";
 657                         big-endian;
 658                 };
 659
 660                 sai1: sai@2b50000 {
 661                         #sound-dai-cells = <0>;
 662                         compatible = "fsl,vf610-sai";
 663                         reg = <0x0 0x2b50000 0x0 0x10000>;
 664                         interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
 665                         clocks = <&clockgen 4 1>, <&clockgen 4 1>,
 666                                  <&clockgen 4 1>, <&clockgen 4 1>;
 667                         clock-names = "bus", "mclk1", "mclk2", "mclk3";
 668                         dma-names = "tx", "rx";
 669                         dmas = <&edma0 1 47>,
 670                                <&edma0 1 46>;
 671                         status = "disabled";
 672                 };
 673
 674                 sai2: sai@2b60000 {
 675                         #sound-dai-cells = <0>;
 676                         compatible = "fsl,vf610-sai";
 677                         reg = <0x0 0x2b60000 0x0 0x10000>;
 678                         interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
 679                         clocks = <&clockgen 4 1>, <&clockgen 4 1>,
 680                                  <&clockgen 4 1>, <&clockgen 4 1>;
 681                         clock-names = "bus", "mclk1", "mclk2", "mclk3";
 682                         dma-names = "tx", "rx";
 683                         dmas = <&edma0 1 45>,
 684                                <&edma0 1 44>;
 685                         status = "disabled";
 686                 };
 687
 688                 edma0: edma@2c00000 {
 689                         #dma-cells = <2>;
 690                         compatible = "fsl,vf610-edma";
 691                         reg = <0x0 0x2c00000 0x0 0x10000>,
 692                               <0x0 0x2c10000 0x0 0x10000>,
 693                               <0x0 0x2c20000 0x0 0x10000>;
 694                         interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
 695                                      <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
 696                         interrupt-names = "edma-tx", "edma-err";
 697                         dma-channels = <32>;
 698                         big-endian;
 699                         clock-names = "dmamux0", "dmamux1";
 700                         clocks = <&clockgen 4 1>,
 701                                  <&clockgen 4 1>;
 702                 };
 703
 704                 dcu: dcu@2ce0000 {
 705                         compatible = "fsl,ls1021a-dcu";
 706                         reg = <0x0 0x2ce0000 0x0 0x10000>;
 707                         interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
 708                         clocks = <&clockgen 4 0>,
 709                                 <&clockgen 4 0>;
 710                         clock-names = "dcu", "pix";
 711                         big-endian;
 712                         status = "disabled";
 713                 };
 714
 715                 mdio0: mdio@2d24000 {
 716                         compatible = "gianfar";
 717                         device_type = "mdio";
 718                         #address-cells = <1>;
 719                         #size-cells = <0>;
 720                         reg = <0x0 0x2d24000 0x0 0x4000>,
 721                               <0x0 0x2d10030 0x0 0x4>;
 722                 };
 723
 724                 mdio1: mdio@2d64000 {
 725                         compatible = "gianfar";
 726                         device_type = "mdio";
 727                         #address-cells = <1>;
 728                         #size-cells = <0>;
 729                         reg = <0x0 0x2d64000 0x0 0x4000>,
 730                               <0x0 0x2d50030 0x0 0x4>;
 731                 };
 732
 733                 ptp_clock@2d10e00 {
 734                         compatible = "fsl,etsec-ptp";
 735                         reg = <0x0 0x2d10e00 0x0 0xb0>;
 736                         interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
 737                         fsl,tclk-period = <5>;
 738                         fsl,tmr-prsc    = <2>;
 739                         fsl,tmr-add     = <0xaaaaaaab>;
 740                         fsl,tmr-fiper1  = <999999995>;
 741                         fsl,tmr-fiper2  = <999999995>;
 742                         fsl,max-adj     = <499999999>;
 743                         fsl,extts-fifo;
 744                 };
 745
 746                 enet0: ethernet@2d10000 {
 747                         compatible = "fsl,etsec2";
 748                         device_type = "network";
 749                         #address-cells = <2>;
 750                         #size-cells = <2>;
 751                         interrupt-parent = <&gic>;
 752                         model = "eTSEC";
 753                         fsl,magic-packet;
 754                         ranges;
 755                         dma-coherent;
 756
 757                         queue-group@2d10000 {
 758                                 #address-cells = <2>;
 759                                 #size-cells = <2>;
 760                                 reg = <0x0 0x2d10000 0x0 0x1000>;
 761                                 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
 762                                         <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
 763                                         <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
 764                         };
 765
 766                         queue-group@2d14000  {
 767                                 #address-cells = <2>;
 768                                 #size-cells = <2>;
 769                                 reg = <0x0 0x2d14000 0x0 0x1000>;
 770                                 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
 771                                         <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
 772                                         <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
 773                         };
 774                 };
 775
 776                 enet1: ethernet@2d50000 {
 777                         compatible = "fsl,etsec2";
 778                         device_type = "network";
 779                         #address-cells = <2>;
 780                         #size-cells = <2>;
 781                         interrupt-parent = <&gic>;
 782                         model = "eTSEC";
 783                         ranges;
 784                         dma-coherent;
 785
 786                         queue-group@2d50000  {
 787                                 #address-cells = <2>;
 788                                 #size-cells = <2>;
 789                                 reg = <0x0 0x2d50000 0x0 0x1000>;
 790                                 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
 791                                         <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
 792                                         <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
 793                         };
 794
 795                         queue-group@2d54000  {
 796                                 #address-cells = <2>;
 797                                 #size-cells = <2>;
 798                                 reg = <0x0 0x2d54000 0x0 0x1000>;
 799                                 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
 800                                         <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
 801                                         <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
 802                         };
 803                 };
 804
 805                 enet2: ethernet@2d90000 {
 806                         compatible = "fsl,etsec2";
 807                         device_type = "network";
 808                         #address-cells = <2>;
 809                         #size-cells = <2>;
 810                         interrupt-parent = <&gic>;
 811                         model = "eTSEC";
 812                         ranges;
 813                         dma-coherent;
 814
 815                         queue-group@2d90000  {
 816                                 #address-cells = <2>;
 817                                 #size-cells = <2>;
 818                                 reg = <0x0 0x2d90000 0x0 0x1000>;
 819                                 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
 820                                         <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
 821                                         <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
 822                         };
 823
 824                         queue-group@2d94000  {
 825                                 #address-cells = <2>;
 826                                 #size-cells = <2>;
 827                                 reg = <0x0 0x2d94000 0x0 0x1000>;
 828                                 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
 829                                         <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
 830                                         <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
 831                         };
 832                 };
 833
 834                 usb2: usb@8600000 {
 835                         compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
 836                         reg = <0x0 0x8600000 0x0 0x1000>;
 837                         interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
 838                         dr_mode = "host";
 839                         phy_type = "ulpi";
 840                 };
 841
 842                 usb3: usb@3100000 {
 843                         compatible = "snps,dwc3";
 844                         reg = <0x0 0x3100000 0x0 0x10000>;
 845                         interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 846                         dr_mode = "host";
 847                         snps,quirk-frame-length-adjustment = <0x20>;
 848                         snps,dis_rxdet_inp3_quirk;
 849                         snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
 850                 };
 851
 852                 pcie@3400000 {
 853                         compatible = "fsl,ls1021a-pcie";
 854                         reg = <0x00 0x03400000 0x0 0x00010000   /* controller registers */
 855                                0x40 0x00000000 0x0 0x00002000>; /* configuration space */
 856                         reg-names = "regs", "config";
 857                         interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
 858                         fsl,pcie-scfg = <&scfg 0>;
 859                         #address-cells = <3>;
 860                         #size-cells = <2>;
 861                         device_type = "pci";
 862                         num-viewport = <6>;
 863                         bus-range = <0x0 0xff>;
 864                         ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000   /* downstream I/O */
 865                                   0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 866                         msi-parent = <&msi1>, <&msi2>;
 867                         #interrupt-cells = <1>;
 868                         interrupt-map-mask = <0 0 0 7>;
 869                         interrupt-map = <0000 0 0 1 &gic GIC_SPI 91  IRQ_TYPE_LEVEL_HIGH>,
 870                                         <0000 0 0 2 &gic GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
 871                                         <0000 0 0 3 &gic GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
 872                                         <0000 0 0 4 &gic GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
 873                         status = "disabled";
 874                 };
 875
 876                 pcie@3500000 {
 877                         compatible = "fsl,ls1021a-pcie";
 878                         reg = <0x00 0x03500000 0x0 0x00010000   /* controller registers */
 879                                0x48 0x00000000 0x0 0x00002000>; /* configuration space */
 880                         reg-names = "regs", "config";
 881                         interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
 882                         fsl,pcie-scfg = <&scfg 1>;
 883                         #address-cells = <3>;
 884                         #size-cells = <2>;
 885                         device_type = "pci";
 886                         num-viewport = <6>;
 887                         bus-range = <0x0 0xff>;
 888                         ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000   /* downstream I/O */
 889                                   0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 890                         msi-parent = <&msi1>, <&msi2>;
 891                         #interrupt-cells = <1>;
 892                         interrupt-map-mask = <0 0 0 7>;
 893                         interrupt-map = <0000 0 0 1 &gic GIC_SPI 92  IRQ_TYPE_LEVEL_HIGH>,
 894                                         <0000 0 0 2 &gic GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
 895                                         <0000 0 0 3 &gic GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
 896                                         <0000 0 0 4 &gic GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
 897                         status = "disabled";
 898                 };
 899
 900                 can0: can@2a70000 {
 901                         compatible = "fsl,ls1021ar2-flexcan";
 902                         reg = <0x0 0x2a70000 0x0 0x1000>;
 903                         interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
 904                         clocks = <&clockgen 4 1>, <&clockgen 4 1>;
 905                         clock-names = "ipg", "per";
 906                         big-endian;
 907                 };
 908
 909                 can1: can@2a80000 {
 910                         compatible = "fsl,ls1021ar2-flexcan";
 911                         reg = <0x0 0x2a80000 0x0 0x1000>;
 912                         interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
 913                         clocks = <&clockgen 4 1>, <&clockgen 4 1>;
 914                         clock-names = "ipg", "per";
 915                         big-endian;
 916                 };
 917
 918                 can2: can@2a90000 {
 919                         compatible = "fsl,ls1021ar2-flexcan";
 920                         reg = <0x0 0x2a90000 0x0 0x1000>;
 921                         interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
 922                         clocks = <&clockgen 4 1>, <&clockgen 4 1>;
 923                         clock-names = "ipg", "per";
 924                         big-endian;
 925                 };
 926
 927                 can3: can@2aa0000 {
 928                         compatible = "fsl,ls1021ar2-flexcan";
 929                         reg = <0x0 0x2aa0000 0x0 0x1000>;
 930                         interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
 931                         clocks = <&clockgen 4 1>, <&clockgen 4 1>;
 932                         clock-names = "ipg", "per";
 933                         big-endian;
 934                 };
 935
 936                 ocram1: sram@10000000 {
 937                         compatible = "mmio-sram";
 938                         reg = <0x0 0x10000000 0x0 0x10000>;
 939                         #address-cells = <1>;
 940                         #size-cells = <1>;
 941                         ranges = <0x0 0x0 0x10000000 0x10000>;
 942                 };
 943
 944                 ocram2: sram@10010000 {
 945                         compatible = "mmio-sram";
 946                         reg = <0x0 0x10010000 0x0 0x10000>;
 947                         #address-cells = <1>;
 948                         #size-cells = <1>;
 949                         ranges = <0x0 0x0 0x10010000 0x10000>;
 950                 };
 951
 952                 qdma: dma-controller@8390000 {
 953                         compatible = "fsl,ls1021a-qdma";
 954                         reg = <0x0 0x8388000 0x0 0x1000>, /* Controller regs */
 955                               <0x0 0x8389000 0x0 0x1000>, /* Status regs */
 956                               <0x0 0x838a000 0x0 0x2000>; /* Block regs */
 957                         interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
 958                                      <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
 959                                      <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 960                         interrupt-names = "qdma-error",
 961                                 "qdma-queue0", "qdma-queue1";
 962                         dma-channels = <8>;
 963                         block-number = <1>;
 964                         block-offset = <0x1000>;
 965                         fsl,dma-queues = <2>;
 966                         status-sizes = <64>;
 967                         queue-sizes = <64 64>;
 968                         big-endian;
 969                 };
 970
 971                 rcpm: power-controller@1ee2140 {
 972                         compatible = "fsl,ls1021a-rcpm", "fsl,qoriq-rcpm-2.1+";
 973                         reg = <0x0 0x1ee2140 0x0 0x8>;
 974                         #fsl,rcpm-wakeup-cells = <2>;
 975                 };
 976
 977                 ftm_alarm0: timer0@29d0000 {
 978                         compatible = "fsl,ls1021a-ftm-alarm";
 979                         reg = <0x0 0x29d0000 0x0 0x10000>;
 980                         reg-names = "ftm";
 981                         fsl,rcpm-wakeup = <&rcpm 0x0 0x20000000>;
 982                         interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
 983                         big-endian;
 984                 };
 985         };
 986
 987         thermal-zones {
 988                 cpu_thermal: cpu-thermal {
 989                         polling-delay-passive = <1000>;
 990                         polling-delay = <5000>;
 991
 992                         thermal-sensors = <&tmu 0>;
 993
 994                         trips {
 995                                 cpu_alert: cpu-alert {
 996                                         temperature = <85000>;
 997                                         hysteresis = <2000>;
 998                                         type = "passive";
 999                                 };
1000                                 cpu_crit: cpu-crit {
1001                                         temperature = <95000>;
1002                                         hysteresis = <2000>;
1003                                         type = "critical";
1004                                 };
1005                         };
1006
1007                         cooling-maps {
1008                                 map0 {
1009                                         trip = <&cpu_alert>;
1010                                         cooling-device =
1011                                                 <&cpu0 THERMAL_NO_LIMIT
1012                                                 THERMAL_NO_LIMIT>,
1013                                                 <&cpu1 THERMAL_NO_LIMIT
1014                                                 THERMAL_NO_LIMIT>;
1015                                 };
1016                         };
1017                 };
1018         };
1019 };