1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright 2016-2018 NXP Semiconductors
3 * Copyright 2019 Vladimir Oltean <olteanv@gmail.com>
7 #include "ls1021a.dtsi"
10 model = "NXP LS1021A-TSN Board";
11 compatible = "fsl,ls1021a-tsn", "fsl,ls1021a";
13 sys_mclk: clock-mclk {
14 compatible = "fixed-clock";
16 clock-frequency = <24576000>;
19 reg_vdda_codec: regulator-3V3 {
20 compatible = "regulator-fixed";
21 regulator-name = "3P3V";
22 regulator-min-microvolt = <3300000>;
23 regulator-max-microvolt = <3300000>;
27 reg_vddio_codec: regulator-2V5 {
28 compatible = "regulator-fixed";
29 regulator-name = "2P5V";
30 regulator-min-microvolt = <2500000>;
31 regulator-max-microvolt = <2500000>;
40 /* ADG704BRMZ 1:4 SPI mux/demux */
41 sja1105: ethernet-switch@1 {
45 compatible = "nxp,sja1105t";
47 spi-max-frequency = <12000000>;
48 /* Sample data on trailing clock edge */
50 /* SPI controller settings for SJA1105 timing requirements */
51 fsl,spi-cs-sck-delay = <1000>;
52 fsl,spi-sck-cs-delay = <1000>;
59 /* ETH5 written on chassis */
61 phy-handle = <&rgmii_phy6>;
62 phy-mode = "rgmii-id";
67 /* ETH2 written on chassis */
69 phy-handle = <&rgmii_phy3>;
70 phy-mode = "rgmii-id";
75 /* ETH3 written on chassis */
77 phy-handle = <&rgmii_phy4>;
78 phy-mode = "rgmii-id";
83 /* ETH4 written on chassis */
85 phy-handle = <&rgmii_phy5>;
86 phy-mode = "rgmii-id";
91 /* Internal port connected to eth2 */
94 rx-internal-delay-ps = <0>;
95 tx-internal-delay-ps = <0>;
108 tbi-handle = <&tbi0>;
109 phy-handle = <&sgmii_phy2>;
115 tbi-handle = <&tbi1>;
116 phy-handle = <&sgmii_phy1>;
121 /* RGMII delays added via PCB traces */
139 /* 3 axis accelerometer */
141 compatible = "fsl,fxls8471";
145 /* Audio codec (SAI2) */
147 compatible = "fsl,sgtl5000";
148 VDDIO-supply = <®_vddio_codec>;
149 VDDA-supply = <®_vdda_codec>;
150 #sound-dai-cells = <0>;
151 clocks = <&sys_mclk>;
155 /* Current sensing circuit for 1V VDDCORE PMIC rail */
157 compatible = "ti,ina220";
158 shunt-resistor = <1000>;
162 /* Current sensing circuit for 12V VCC rail */
164 compatible = "ti,ina220";
165 shunt-resistor = <1000>;
169 /* Thermal monitor - case */
170 temperature-sensor@48 {
171 compatible = "national,lm75";
175 /* Thermal monitor - chip */
176 temperature-sensor@4c {
177 compatible = "ti,tmp451";
182 compatible = "atmel,24c32";
186 /* Unsupported devices:
187 * - FXAS21002C Gyroscope at 0x20
188 * - TI ADS7924 4-channel ADC at 0x49
206 sgmii_phy1: ethernet-phy@1 {
208 /* SGMII1_PHY_INT_B: connected to IRQ2, active low */
209 interrupts-extended = <&extirq 2 IRQ_TYPE_LEVEL_LOW>;
213 sgmii_phy2: ethernet-phy@2 {
215 /* SGMII2_PHY_INT_B: connected to IRQ2, active low */
216 interrupts-extended = <&extirq 2 IRQ_TYPE_LEVEL_LOW>;
219 /* BCM5464 quad PHY */
220 rgmii_phy3: ethernet-phy@3 {
224 rgmii_phy4: ethernet-phy@4 {
228 rgmii_phy5: ethernet-phy@5 {
232 rgmii_phy6: ethernet-phy@6 {
236 /* SGMII PCS for enet0 */
239 device_type = "tbi-phy";
244 /* SGMII PCS for enet1 */
247 device_type = "tbi-phy";
255 /* Rev. A uses 64MB flash, Rev. B & C use 32MB flash */
256 compatible = "jedec,spi-nor";
257 spi-max-frequency = <20000000>;
258 #address-cells = <1>;
263 compatible = "fixed-partitions";
264 #address-cells = <1>;
274 reg = <0x40000 0x300000>;
278 label = "U-Boot Env";
279 reg = <0x340000 0x100000>;