1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright 2013-2014 Freescale Semiconductor, Inc.
8 #include "ls1021a.dtsi"
11 model = "LS1021A QDS Board";
12 compatible = "fsl,ls1021a-qds", "fsl,ls1021a";
15 enet0_rgmii_phy = &rgmii_phy1;
16 enet1_rgmii_phy = &rgmii_phy2;
17 enet2_rgmii_phy = &rgmii_phy3;
18 enet0_sgmii_phy = &sgmii_phy1c;
19 enet1_sgmii_phy = &sgmii_phy1d;
22 sys_mclk: clock-mclk {
23 compatible = "fixed-clock";
25 clock-frequency = <24576000>;
29 compatible = "regulator-fixed";
30 regulator-name = "3P3V";
31 regulator-min-microvolt = <3300000>;
32 regulator-max-microvolt = <3300000>;
37 compatible = "simple-audio-card";
38 simple-audio-card,format = "i2s";
39 simple-audio-card,widgets =
40 "Microphone", "Microphone Jack",
41 "Headphone", "Headphone Jack",
42 "Speaker", "Speaker Ext",
43 "Line", "Line In Jack";
44 simple-audio-card,routing =
45 "MIC_IN", "Microphone Jack",
46 "Microphone Jack", "Mic Bias",
47 "LINE_IN", "Line In Jack",
48 "Headphone Jack", "HP_OUT",
49 "Speaker Ext", "LINE_OUT";
51 simple-audio-card,cpu {
57 simple-audio-card,codec {
69 dspiflash: at45db021d@0 {
72 compatible = "atmel,at45db021d", "atmel,at45", "atmel,dataflash";
73 spi-max-frequency = <16000000>;
82 phy-handle = <&sgmii_phy1c>;
83 phy-connection-type = "sgmii";
89 phy-handle = <&sgmii_phy1d>;
90 phy-connection-type = "sgmii";
95 phy-handle = <&rgmii_phy3>;
96 phy-connection-type = "rgmii-id";
108 compatible = "nxp,pca9547";
110 #address-cells = <1>;
114 #address-cells = <1>;
119 compatible = "dallas,ds3232";
121 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
126 #address-cells = <1>;
131 compatible = "ti,ina220";
133 shunt-resistor = <1000>;
137 compatible = "ti,ina220";
139 shunt-resistor = <1000>;
144 #address-cells = <1>;
149 compatible = "atmel,24c512";
154 compatible = "atmel,24c512";
159 compatible = "adi,adt7461a";
165 #address-cells = <1>;
170 #sound-dai-cells = <0>;
171 compatible = "fsl,sgtl5000";
173 VDDA-supply = <®_3p3v>;
174 VDDIO-supply = <®_3p3v>;
175 clocks = <&sys_mclk>;
182 #address-cells = <2>;
184 /* NOR, NAND Flashes and FPGA on board */
185 ranges = <0x0 0x0 0x0 0x60000000 0x08000000>,
186 <0x2 0x0 0x0 0x7e800000 0x00010000>,
187 <0x3 0x0 0x0 0x7fb00000 0x00000100>;
191 #address-cells = <1>;
193 compatible = "cfi-flash";
194 reg = <0x0 0x0 0x8000000>;
201 compatible = "fsl,ifc-nand";
202 reg = <0x2 0x0 0x10000>;
205 fpga: board-control@3,0 {
206 #address-cells = <1>;
208 compatible = "simple-mfd";
209 reg = <0x3 0x0 0x0000100>;
212 ranges = <0 3 0 0x100>;
215 compatible = "mdio-mux-mmioreg";
216 mdio-parent-bus = <&mdio0>;
217 #address-cells = <1>;
219 reg = <0x54 1>; /* BRDCFG4 */
220 mux-mask = <0xe0>; /* EMI1[2:0] */
223 ls1021amdio0: mdio@0 {
225 #address-cells = <1>;
227 rgmii_phy1: ethernet-phy@1 {
232 ls1021amdio1: mdio@20 {
234 #address-cells = <1>;
236 rgmii_phy2: ethernet-phy@2 {
241 ls1021amdio2: mdio@40 {
243 #address-cells = <1>;
245 rgmii_phy3: ethernet-phy@3 {
250 ls1021amdio3: mdio@60 {
252 #address-cells = <1>;
254 sgmii_phy1c: ethernet-phy@1c {
259 ls1021amdio4: mdio@80 {
261 #address-cells = <1>;
263 sgmii_phy1d: ethernet-phy@1d {
278 device_type = "tbi-phy";
286 compatible = "jedec,spi-nor";
287 #address-cells = <1>;
289 spi-max-frequency = <20000000>;
291 spi-rx-bus-width = <4>;
292 spi-tx-bus-width = <4>;